MSP430 Teaching Materials

Transcription

1 MSP430 Teaching Materials Lecture 6 Data Acquisition Texas Instruments Incorporated University of Beira Interior (PT) Pedro Dinis Gaspar, António Espírito Santo, Bruno Ribeiro, Humberto Santos University of Beira Interior, Electromechanical Engineering Department

2 Contents (1/3) UBI Introduction Operational Amplifiers Introduction to Operational Amplifiers (Op-Amps) Internal Structure Architectures of Operational Amplifiers Registers Configuration of Topologies Analogue-to-Digital Converter (ADC) Introduction to Analogue-to-Digital Conversion ADC Specifications DC performance AC performance ADC Architectures 2

3 Contents (2/3) UBI Successive Approximation Register (SAR) converter Introduction to Successive Approximation Register (SAR) Analogue-to-Digital Converter (ADC) ADC10 ADC12 Sigma-Delta (SD) converter Introduction to Sigma-Delta ADC : Delta modulator Digital filter Decimation digital filter MSP430 SD16(A) Sigma-Delta ADC 3

4 Contents (3/3) UBI Slope converter Comparator-Based Slope ADC: Single- and dual- slope ADC Resistive sensors measurements Voltage measurements Comparator_A Introduction to Comparator_A Features Voltage reference generator Comparator_A interrupts Comparator_A registers 4

5 Introduction (1/4) UBI Most engineering applications require some form of data processing: measurement, control, calculation, communication or data recording; These operations, either grouped or isolated, are built into the measuring instruments; The measuring equipment must maintain: Compatibility and communication between measuring devices; Acceptable error margin; Noise and interference immunity; Predictable measurement uncertainty; Suitable type of control (analogue/digital); Mathematical processing capacity; 5

6 Introduction (2/4) UBI Data acquisition system components: Sensors: Convert analogue measurements of physical quantities (e.g. temperature, pressure, humidity, velocity, flowrate, linear motion, position) into electrical signals (voltage or current). 6

7 Introduction (3/4) Data acquisition system components: Signal conditioning (filtering and amplification): The operations required to convert the measured analogue signal measured to the electrical signal range of the analogue-to-digital converter (ADC) may involve filtering, amplification, attenuation or impedance transformation. Analogue-to-Digital Converter (ADC): Input: Signal to be measured; Output: A digital code compatible with the digital processing system; Requires: Sample-and-hold: Used to take a snapshot of the continuously changing input signal and maintain the value over the sample interval set by a clock system; A sampling frequency based on the Nyquist theorem. 7

8 Introduction (4/4) Data acquisition system components: Analogue-to-Digital Converter (ADC) (continued): Sample-and-Hold: (Note) Not necessary for Sigma- Delta (SD) converters, nor for slope converters, nor for all flash converters and is automatically implemented as part of the structure of capacitive successive approximation Register (SAR) converters on the MSP430. The specifications of these converters will be described in the following sections. 8

9 Operational Amplifiers (1/2) UBI Some devices in the MSP430 family provide analogue signal amplification in the form of operational amplifiers; The main op-amp characteristics are: Signal protection from interference (voltage level increase); Good signal transfer due to high impedance inputs and low impedance output; Improvement to signal precision by adjustment of the voltage level at the ADC input. There are different types of op-amps: Single Supply; Dual Supply; CMOS or Bipolar or mixed; Rail-to-Rail In; Rail-to-Rail Out. 9

10 Operational Amplifiers (2/2) UBI All op-amps (OAs) included in the MSP430 devices are Single Supply and CMOS; The MSP430FG4618 has three op-amps; The MSP430F2274 has two op-amps; Main op-amp features: Selectable gain bandwidth: 500 khz, 1.4 MHz, 2.2 MHz; Class AB output for ma range drive; Integrated charge pump for rail-to-rail input range and superior offset behaviour (FG only); User-configurable feedback and interconnects: Internal R ladder; Internally chainable (minimises external passive components); Internal connections to the ADC and DAC. 10

11 Internal Structure (1/3) UBI The internal structure of each op-amp allows: Flexible feedback networking; Flexible modes (optimized current consumption and performance; User configurable as: General purpose; Unity gain buffer; Voltage comparator; Inverting programmable gain amplifier (PGA); Non-inverting programmable gain amplifier (PGA); Differential amplifier. 11

12 Internal Structure (2/3) UBI Op-Amp internal structure: 12

13 Internal Structure (3/3) UBI An OA consists of: Two inputs: Inverting input, V 1 ; Non inverting input, V 2. Single output, V 0 : Represented by E 0 = A VD V D :»E 0 : input differential signal, V D = V 2 V 1 ;»A VD : Open-loop differential gain (ideally: infinity). High input impedance, Z IN (ideally: infinity); Low output impedance, Z 0 (ideally: zero); Input offset voltage, V IO : Output voltage is displaced from 0 V (ideally: zero); Null input currents, I 1 and I 2 (ideally: zero). 13

14 Architecture of Operational Amplifiers (1/8) UBI Inverting topology: Resistor R f is connected from the output V 0 back to the inverting input, to control the gain of the OA with negative feedback; V IN applied to the inverting input; Gain of the inverting OA: A VD = R f / R 1 ; Output has a 180º phase shift from the input. Note: The single supply circuitry shown is only applicable for negative input voltages, and input signal is loaded by R 1. 14

15 Operational Amplifiers architectures (2/8) UBI Non-inverting topology: Resistor R f is connected from the output V 0 back to the inverting input to control the gain of the OA with negative feedback; V IN applied to the non inverting input; Gain of the non-inverting OA: A VD = 1 + R f / R 1. 15

16 Architecture of Operational Amplifiers (3/8) UBI Non-inverting topology (continued): Output in phase with the input; Buffer (isolation between the circuit and the charge); Power amplifier; Impedance transformer; Input impedance: to ; Suitable for amplifying signals with high Z IN. 16

17 Architecture of Operational Amplifiers (4/8) UBI Unity gain buffer (voltage follower) topology: Non-inverting amplifier with R f = 0 and R 1 equal to infinity (Note: often used with R f for better dynamic performance); A VD = 1 + R f /R 1 = 1 (unity gain amplifier); V 0 = V IN. 17

18 Architecture of Operational Amplifiers (5/8) UBI Differential topology: Inverting and non-inverting topologies combined; Output signal is the amplification of the difference between the two input signals: A VD = R f /R 1 ; V 0 = A VD (V 2 V 1 ); 18

19 Architecture of Operational Amplifiers (6/8) UBI Differential topology: Common-Mode Rejection Ratio (CMRR): Common mode noise is the voltage picked up on the leads connecting the sensor to the amplifier may be 100 to 1000 times greater than the magnitude of the sensor signal itself; The CMRR of the OA ensures that any signal appearing on both inputs at the same time will be attenuated considerably at the output; CMRR [db] = 20log 10 (A VD /A CM ); where: A CM : Amplification for Common Mode; A CM =(R 1 xr 3 R f xr 2 )/[R 1 x(r 2 +R 3 )]. 19

20 Architecture of Operational Amplifiers (7/8) UBI Two OpAmp Differential topology: A VD = R 2 /R 1 V 0 = A VD (V 2 V 1 ) 20

21 Architecture of Operational Amplifiers (8/8) UBI Three OpAmp Differential topology: A VD = R 2 /R 1 V 0 = A VD (V 2 V 1 ) 21

22 Registers (1/2) OAxCTL0, OpAmp Control Register OANx OAPx OAPMx OAADC1 OAADC0 Bit Description 7-6 OANx OA Inverting input signal select: OAN1 OAN0 = 00 OAxI0 OAN1 OAN0 = 01 OAxI1 OAN1 OAN0 = 10 DAC0 internal OAN1 OAN0 = 11 DAC1 internal 5-4 OAPx OA Non-inverting input signal select: OAP1 OAP0 = 00 OAxI0 OAP1 OAP0 = 01 OAxI1 OAP1 OAP0 = 10 DAC0 internal OAP1 OAP0 = 11 DAC1 internal 3-2 OAPMx Selection of the slew rate vs. current consumption for the OA: OAPM1 OAPM0 = 00 Off OAPM1 OAPM0 = 01 Slow OAPM1 OAPM0 = 10 Medium OAPM1 OAPM0 = 11 Fast 1 OAADC1 OA output select (OAFCx > 0): OAADC1 = 1 OAx output connected to internal /external A1 (OA0), A3 (OA1), or A5 (OA2) signals 0 OAADC0 OA output select (OAPMx > 0): OAADC0 = 1 OAx output connected to internal A12 (OA0), A13 (OA1), or A14 (OA2) signals 22

23 Bit Registers (2/2) OAxCTL1, OpAmp Control Register OAFBRx OAFCx Reserved OARRIP Description 7-5 OAFBRx OAx feedback resistor: OAFBR2 OAFBR1 OAFBR0 = 000 (Gain): A VD = 1 OAFBR2 OAFBR1 OAFBR0 = 001 (Gain): A VD = 1.33 OAFBR2 OAFBR1 OAFBR0 = 010 (Gain): A VD = 2 OAFBR2 OAFBR1 OAFBR0 = 011 (Gain): A VD = 2.67 OAFBR2 OAFBR1 OAFBR0 = 100 (Gain): A VD = 4 OAFBR2 OAFBR1 OAFBR0 = 101 (Gain): A VD = 4.33 OAFBR2 OAFBR1 OAFBR0 = 110 (Gain): A VD = 8 OAFBR2 OAFBR1 OAFBR0 = 111 (Gain): A VD = OAFCx OAx function control: OAFC2 OAFC1 OAFC0 = 000 General purpose OAFC2 OAFC1 OAFC0 = 001 Unity gain buffer OAFC2 OAFC1 OAFC0 = 010 Reserved OAFC2 OAFC1 OAFC0 = 011 Comparing Op-Amp OAFC2 OAFC1 OAFC0 = 100 Non-inverting PGA OAFC2 OAFC1 OAFC0 = 101 Reserved OAFC2 OAFC1 OAFC0 = 110 Inverting PGA OAFC2 OAFC1 OAFC0 = 111 Differential Op-Amp 0 OARRIP OA rail-to-rail input off: OARRIP = 0 OAx input signal range is rail-to-rail OARRIP = 1 OAx input signal range is limited 23

24 Configuration of Topology (1/11) UBI Op-Amp (OA) module topologies configuration: OAFCx bits Op-Amp (OA) module topology 000 General-purpose op-amp 001 Unity gain buffer 010 Reserved 011 Voltage comparator 100 Non-inverting programmable amplifier 101 Reserved 110 Inverting programmable amplifier 111 Differential amplifier OARRIP = 1: (V SS - 0.1V) {min} to (V CC + 0.1) {max} Charge pump at input stage is turned on OARRIP = 0: (V SS - 0.1V) {min} to (V CC - 1.2) {max} Appropriate for Gains > 2. 24

25 Configuration of Topology (2/11) UBI General-purpose op-amp (OAFCx = 000): Closed loop configuration; Connection from output to inverting input; Requires external resistors; OAxCTL0 bits define the signal routing; OAx inputs are selected with the OAPx and OANx bits; OAx output is internally connected to the ADC12 input. 25

26 Configuration of Topology (3/11) Inverting amplifier topology (OAFCx = 110): V Output voltage: V 1 0 ref R R f 1 V IN R R f 1 Configuration of the OAxCTL1 register: Using internal resistors: A VD = to A VD = -15; The OAx input signal range can be rail-to-rail or limited (OARRIP bit). 26

27 Configuration of Topology (4/11) Non-inverting amplifier topology (OAFCx = 100) Output voltage: R f V0 VIN 1 R 1 V ref R R f 1 Configuration of the OAxCTL1 register: Using internal resistors: A VD =1 to A VD =16; The OAx input signal range can be rail-to-rail or limited (OARRIP bit). 27

28 Configuration of Topology (5/11) Unity gain buffer (OAFCx = 001): Closed loop configuration; OAx output connected internally to R BOTTOM and input OAx; Non-inverting input is available (OAPx bits); External connection for the inverting input is disabled; OAx output is internally connected to ADC12 input (OAxCTL0). 28

29 Configuration of Topology (6/11) Voltage comparator (OAFCx = 011): Open loop configuration; OAx output is isolated from R ladder; R TOP is connected to AV SS ; R BOTTOM is connected to AV CC ; OAxTAP signal connected to the input OAx: comparator with a programmable threshold voltage (OAFBRx bits); Non-inverting input is selected by the OAPx bits; Hysteresis can be added (external positive feedback resistor); The external connection for the inverting input is disabled; OAx output is internally connected to ADC12 input (OAxCTL0). 29

30 Configuration of Topology (7/11) Differential amplifier (OAFCx = 111): Internal routing of the OA signals: 2-OpAmp or 3-OpAmp. Two-OpAmp: OAx output connected to R TOP by routing through another OAx in the Inverting PGA mode. R BOTTOM is unconnected providing a unity gain buffer (combined with the remaining OAx to form the differential amplifier). The OAx output is internally connected to the ADC12 input channel as selected by the OAxCTL0 bits. 30

31 Topologies Configuration (8/11) Two OpAmp Differential amplifier (OAFCx = 111): Configuration of control registers: Registers Configuration OA0CTL0 00 xx xx 00 OA0CTL x OA1CTL0 10 xx xx xx OA1CTL1 xx x1 10 0x Configuration of gain: OA1 OAFBRx bits Gain

32 Configuration of Topology (9/11) Two-OpAmp Differential amplifier (OAFCx = 111): 32

33 Configuration of Topology (10/11) Three-OpAmp Differential amplifier (OAFCx = 111): Configuration of control registers: Configuration of gain: Registers Configuration OA0CTL0 00 xx xx 00 OA0CTL1 xx x0 01 0x OA1CTL0 00 xx xx 00 OA1CTL x OA2CTL xx xx OA2CTL1 xx x1 10 0x OA0/OA2 OAFBRx bits Gain

34 Configuration of Topology (11/11) Three-OpAmp Differential amplifier (OAFCx = 111): 34

35 Analogue-to-Digital Conversion (1/2) UBI The analogue world (the real one) interfaces with digital systems through ADCs; The ADC takes the voltage from the acquisition system (after signal conditioning) and converts it to an equivalent digital code; The ADC ideal transfer function for a 3 bit ADC is given by: The digital code can be displayed, processed, stored or transmitted. 35

36 Analogue-to-Digital Conversion (2/2) UBI There are sufficient analogue peripherals in a number of MSP430 family devices to realize a complete signal chain; Analogue class of applications: Is more or less defined by bandwidth range; Require an established resolution range. 36

37 ADC Specifications (1/3) Resolution, R: The smallest change to the analogue voltage that can be converted into a digital code; The Least Significant Bit (LSB): R 1 n 2 The resolution only specifies the width of the digital output word, not the performance; Most MSP430 devices offer a high-precision ADC: Slope; 10, 12 or 14 Bit SAR; 16 Bit Sigma-Delta. 37

38 ADC Specifications (2/3) Accuracy: Degree of conformity of a digital code representing the analogue voltage to its actual (true) value; Can express as the degree of truth. 38

39 ADC Specifications (3/3) Performance: Depends on the following specifications: Speed; Accuracy, also depends on the circuitry type: DC:» Differential Non-Linearity (DNL);» Integral Non-Linearity (INL);» Offset error,» Gain error AC:» Signal-to-noise ratio (SNR);» Signal-to-noise and distortion ratio (SINAD);» Total harmonic distortion (THD);» Spurious-free dynamic range (SFDR) 39

40 ADC Specifications DC performance (1/9) Differential Non-Linearity (DNL): Determines how far an output code is from a neighbouring output code. The distance is measured as a V IN converted to LSBs; No DNL error requires that: as the V IN is swept over its range, all output code combinations will appear at the converter output; DNL error < ± 1 LSB ensures no missing codes. 40

41 ADC Specifications DC performance (2/9) Integral Non-Linearity (INL): Is the integral of the DNL errors; Represents the difference between the measured converter result and the ideal transfer-function value. 41

42 ADC Specifications DC performance (3/9) DNL, INL and noise impact on the dynamic range: INL, DNL and Noise errors cover the entire range; Impact on the Effective Number of Bits (ENOB); Not easily calibrated or corrected; Affects accuracy. 42

43 ADC Specifications DC performance (4/9) Offset error: In bipolar systems, the offset error shifts the transfer function but does not reduce the number of available codes. 43

44 ADC Specifications DC performance (5/9) Gain error: Full-scale error minus the offset error, measured at the last ADC transition on the transfer-function curve and compared with the ideal ADC transfer function; May (or not) include errors in the voltage reference of the ADC. 44

45 ADC Specifications DC performance (6/9) Offset and gain errors impact on the dynamic range: 45

46 ADC Specifications DC performance (7/9) Offset (a) and gain (b) errors calibration: Bipolar systems: Shift the analogue input (x) and digital output (y) axes of the transfer function so that the negative full-scale point aligns with the zero point: y = a + (1+b) x Apply zero volts to the ADC input and perform a conversion. The conversion result represents the bipolar zero offset error. Perform a gain adjustment. 46

47 ADC Specifications DC performance (8/9) Offset (a) and gain (b) errors calibration: Unipolar systems: Previous methodology is applicable if the offset is positive; Gain error can be corrected by software considering a linear function in terms of the ideal transfer function slope (m 1 ) and measured (m 2 ): y = (m 1 /m 2 )x Both offset and gain errors reduction techniques will imply partial loss of the ADC range. 47

48 ADC Specifications DC performance (9/9) Code-Edge Noise: Amount of noise that appears right at a code transition of the transfer function; Voltage Reference (internal or external): Besides the settling time, the source of the reference voltage errors is related to the following specifications: Temperature drift: Affects the performance of an ADC converter based on resolution; Voltage noise: Specified as either an RMS value or a peak-topeak value; Load regulation: Current drawn by other components will affect the voltage reference; Temperature effects (offset drift and gain drift). Copyright 2008 Texas Instruments 48

49 ADC Specifications AC performance (1/6) AC parameters: Harmonics occur at multiples of the input frequency: 49

50 ADC Specifications AC performance (2/6) Signal-to-noise ratio (SNR): Signal-to-noise ratio without distortion components; Determines where the average noise floor of the converter is, setting an ADC performance limit for noise. 50

51 ADC Specifications AC performance (3/6) Signal-to-noise ratio (SNR): For an n bit ADC sine wave input is given by: SNR 6.02 n 1.76 [ db] Can be improved with oversampling: Lowers the average noise floor of the ADC; Spreads the noise over more frequencies (equalise total noise). 51

52 ADC Specifications AC performance (4/6) Signal-to-noise ratio (SNR): Oversampling an ADC is a common principle to increase resolution; It reduces the noise at any one frequency point. A 2x oversampling reduces the noise floor by 3 db, which corresponds to a ½ bit resolution increase; Oversampling by k times provides a SNR given by: SNR 6.02 n 1.76 f s 10log [ db] 10 2 f max 52

53 ADC Specifications AC performance (5/6) Signal-to-noise and distortion ratio (SINAD): Similar to SNR; Includes the harmonic content [total harmonic distortion], from DC to the Nyquist frequency; Is defined as the ratio of the RMS value of an input sine wave to the RMS value of the noise of the converter; Writing the equation in terms of n, provides the number of bits that are obtained as a function of the RMS noise (effective number of bits, ENOB): n SINAD 1.76 /

54 ADC Specifications AC performance (6/6) Total harmonic distortion (THD): Gets increasingly worse as the input frequency increases; Primary reason for ENOB degradation with frequency is that SINAD decreases as the frequency increases toward the Nyquist limit. Spurious-free dynamic range (SFDR): Defined as the ratio of the RMS value of an input sine wave to the RMS value of the largest trace observed in the frequency domain using a FFT plot; If the distortion component is much larger than the signal of interest, the ADC will not convert small input signals, thus limiting its dynamic range. 54

55 ADC Architectures (1/3) There are many different ADC architectures: Successive Approximation (SAR); Sigma Delta (SD or ); Slope or Dual Slope; Pipeline; Flash...as in quick, not memory. 55

56 ADC Architectures (2/3) The selection of an MSP430 ADC will depend on: Voltage range to be measured; Maximum frequency for A IN ; Minimum resolution needed vs. analogue input variation; The need for differential inputs; Voltage reference range; The need for multiple channels for different analogue inputs. ADC architecture Resolution Conversion rate SAR 18 bit < 5 Msps SD 24 bit bit < 625 ksps < 10 Msps Pipeline 16 bit < 500 Msps Advantages Zero-cycle latency Low latency-time High accuracy Low power Simple operation High resolution High stability Low power Moderate cost Higher speeds Higher bandwidth Disadvantages Sample rates 2-5 MHz Cycle-latency Low speed Lower resolution Delay/Data latency Power requirements 56

57 ADC Architectures (3/3) UBI ADC architectures included in the MSP430 devices populated in the hardware development tools: 10 Bit SAR: MSP430F2274 ez430-rf2500; 12 Bit SAR: MSP430FG4618 Experimenter s board; 16 Bit Sigma-Delta: MSP430F2013 ez430-f2013 and Experimenter s board. 57

58 Introduction to SAR ADC (1/4) Successive Approximation Register (SAR) converters are well-suited to general purpose applications and are used in a wide range signal interfacing applications: Data loggers; Temperature sensors; Bridge sensors (resistive e.g. strain gauges); General purpose. 58

59 SAR block diagram: Introduction to SAR ADC (2/4) 59

60 Introduction to SAR ADC (3/4) SAR concept: Determines the digital word by approximating the analogue input signal using an iterative process, as follows: Discharge the capacitor array to the comparator s V offset ; Sample the input voltage (V S ) and hold; Switch all of the capacitors in the array to V S ; Switch the capacitors to charge the comparator's input; Initiate a binary search: Switch the MSB capacitor to V REF (ADC s FS range):» Divided 1:1 between it and the rest of the array;» Input voltage to the comparator is - V S + V REF /2;» V S > V REF /2 Comparator output: MSB = 1;» V S < V REF /2 Comparator output: MSB = 0; Switch the other capacitors in a decreasing charge capacity order from 16C to C. 60

61 SAR concept: Introduction to SAR ADC (4/4) 61

62 ADC10 (1/2) Description The ADC10 module of the MSP430F2274 supports fast 10- bit analogue-to-digital conversions; The module contains: 10-bit SAR core; Sample select control; Reference generator; Data transfer controller (DTC) for automatic conversion result handling (ADC samples conversion and storage without CPU intervention). 62

63 ADC10 block diagram: ADC10 (2/2) Description 63

64 ADC10 Features Greater than 200 ksps maximum conversion rate; Monotonic 10-bit converter with no missing codes; Sample-and-hold with programmable sample periods; Conversion initiated by software or Timer_A; Software on-chip reference voltage generation (1.5 V or 2.5 V) Software selectable internal or external reference; Eight external input channels; Conversion channels for internal temperature sensor, V CC, and external references; Selectable conversion clock source; Single-channel, repeated single-channel, sequence, and repeated sequence conversion modes; ADC core and reference voltage (powered down separately); Data transfer controller (automatic storage of results). 64

65 ADC10 10 bit ADC core 10 bit ADC core (enable with ADC10ON bit): Converts an analogue input to its 10-bit digital representation; Stores the result in the ADC10MEM register; The analogue conversion range is limited by the upper and lower limits: V R+ ; V R- The digital output (N ADC ) is: Full scale: N ADC = 03FFh, when the input signal V R+ -0.5LSB; Zero: N ADC = 0000h, when the input signal V R LSB. Conversion results: Binary format: V N ADC 1023 V in R V V R R Two s-complement format. 65

66 ADC10 Conversion clock The ADC10CLK is used both as the conversion clock and to generate the sampling period; Each available ADC10 source clock is selected using the ADC10SSELx bits: SMCLK; MCLK; ACLK; Internal oscillator ADC10OSC; Each clock source can be divided from 1-8 (ADC10DIVx bits). The ADC10CLK must remain active until the end of a conversion. 66

67 ADC10 Sample and conversion timing An A/D conversion is initiated by the rising edge of SHI. The sources of SHI (SHSx bits selection) can be: ADC10SC bit; Timer_A Output Unit 1, Output Unit 0, or Output Unit 2. The SHTx bits select the sample period, t sample, to be 4, 8, 16, or 64 ADC10CLK cycles: 67

68 ADC10 (1/2) Conversion modes Conversion modes (selected by the CONSEQx bits): Single channel, single-conversion: A single conversion for the channel selected by INCHx bits is performed, with the result being stored in the ADC10MEM registers; Sequence of channels: One conversion in multiple channels, beginning with the channel selected by INCHx bits and decrementing to channel A0, looping through a specified number of ADC10MEM registers and stopping after the conversion of channel A0. 68

69 ADC10 (2/2) Conversion modes Conversion modes (selected by the CONSEQx bits): Repeat single channel: A single channel selected by INCHx bits is converted repeatedly until stopped and the result is stored in the ADC10MEM register; Repeat sequence of-channels: Repeated conversions for multiple channels, beginning with the channel selected by INCHx bits and decrementing to channel A0. Each ADC result is written to ADC10MEM. The sequence ends after conversion of channel A0, and the next trigger signal re-starts the sequence. 69

70 ADC10 (1/2) Data Transfer Controller (DTC) DTC (ADC10DTC1 0): Automatically transfers the conversion results from ADC10MEM to other on-chip memory locations each time the ADC10 completes a conversion and loads the result to ADC10MEM. Requires one CPU MCLK: If the CPU is active during this period, it will be halted to ensure the transfer is completed; Ensure that no active conversion or sequence is in progress (ADC10 busy) during DTC transfer initiation. 70

71 ADC10 (2/2) Data Transfer Controller (DTC) The Data Transfer Controller (DTC) can be configured for: One-Block Transfer Mode (ADC10TB = 0): The value n in ADC10DTC1 defines the total number of transfers for a block; First block address range {Start: ADC10SA; End: ADC10SA+2n 2}; Two-Block Transfer Mode (ADC10TB = 1): The value n in ADC10DTC1 defines the number of transfers for one block; First block address range {Start: ADC10SA ; End: ADC10SA+2n 2}; Second block address range: {Start: SA+2n ; End: SA+4n 2}. 71

72 ADC10 Integrated temperature sensor Input channel selected as INCHx = 1010; Transfer function relating the input voltage, V Temperature [V] to the temperature, T [ºC], is given by: V Temperature T Considerations: The sampling period must be greater than 30 μs; Large offset error, must be calibrated; Automatically turns on the on-chip reference generator. 72

73 ADC10 ADC10 interrupts One interrupt and one interrupt vector are associated with the ADC10 function: When the DTC is not used (ADC10DTC1 = 0): ADC10IFG is set when conversion results are loaded into ADC10MEM; When DTC is used (ADC10DTC1 > 0): ADC10IFG is set when a block transfer completes and the internal transfer counter n = 0. When ADC10IE = 1 and GIE = 1, the ADC10IFG flag generates an interrupt request. 73

74 ADC10 (1/7) Registers ADC10CTL0, ADC10 Control Register 0 (high byte) SREFx ADC10SHTx ADC10SR REFOUT REFBURST Bit Description SREFx Select voltage reference: V R+ V R SREF2 SREF1 SREF0 = 000 V CC V SS SREF2 SREF1 SREF0 = 001 V REF+ V SS SREF2 SREF1 SREF0 = 010 Ve REF+ V SS SREF2 SREF1 SREF0 = 011 Buffered Ve REF+ V SS SREF2 SREF1 SREF0 = 100 V CC V REF /Ve REF SREF2 SREF1 SREF0 = 101 V REF+ V REF /Ve REF SREF2 SREF1 SREF0 = 110 Ve REF+ V REF /Ve REF SREF2 SREF1 SREF0 = 111 Buffered Ve REF+ V REF /Ve REF ADC10SHTx ADC10 sample-and-hold time: ADC10SHT1 ADC10SHT0 = 00 4 x ADC10CLKs ADC10SHT1 ADC10SHT0 = 01 8 x ADC10CLKs ADC10SHT1 ADC10SHT0 = x ADC10CLKs ADC10SHT1 ADC10SHT0 = x ADC10CLKs 10 ADC10SR ADC10 sampling rate: ADC10SR = 0 Reference buffer supports up to ~200 ksps ADC10SR = 1 Reference buffer supports up to ~50 ksps 9 REFOUT Reference voltage output (pin V REF+ ): REFOUT = 0 Disable REFOUT = 1 Enable 8 REFBURST Controls the operation of the internal reference buffer: REFBURST = 0 Reference buffer on continuously allowing the reference voltage to be present outside the device continuously. REFBURST = 1 Reference buffer automatically disabled when the ADC10 is not actively converting, and automatically re-enabled when during sample-and-conversion. Copyright 2008 Texas Instruments 74

75 ADC10 (2/7) Registers ADC10CTL0, ADC10 Control Register 0 (low byte) MSC REF2_5V REFON ADC10ON ADC10IE ADC10IFG ENC ADC10SC Bit Description 7 MSC Multiple sample and conversion (Valid for sequence or repeated modes): MSC = 0 Requires a rising edge of the SHI signal to trigger each sample-and-conversion. MSC = 1 After the first rising edge of the SHI signal that triggers the sampling timer the further sample-and-conversions are performed automatically as soon as the prior conversion is completed 6 REF2_5V Reference-generator voltage select (REFON bit must also be set): REF2_5V = 0 Reference voltage = 1.5 V REF2_5V = 1 Reference voltage = 2.5 V 5 REFON Reference generator: REFON = 0 Reference generator disable REFON = 1 Reference generator enable 4 ADC10ON ADC10 on: ADC10ON = 0 ADC10 off ADC10ON = 1 ADC10 on 3 ADC10IE ADC10 interrupt enable ADC10IE = 0 Interrupt disabled ADC10IE = 1 Interrupt enabled 2 ADC10IFG ADC10 interrupt flag: ADC10IFG = 0 No interrupt pending (interrupt request is accepted, or it may be reset by software) ADC10IFG = 1 Interrupt pending (ADC10MEM is loaded with a conversion result or when a block of DTC transfers is completed) 1 ENC Enable conversion: ENC = 0 ADC10 disabled ENC = 1 ADC10 enabled 0 ADC10SC Start conversion: ADC10SC = 0 No sample-and-conversion start ADC10SC = 1 Start sample-and-conversion Copyright 2008 Texas Instruments 75

76 ADC10 (3/7) Registers ADC10CTL1, ADC10 Control Register 1 (high byte) INCHx SHSx ADC10DF ISSH Bit Description INCHx Input channel select: INCH3 INCH2 INCH1 INCH0 = 0000 A0 INCH3 INCH2 INCH1 INCH0 = 0001 A1 INCH3 INCH2 INCH1 INCH0 = 0010 A2 INCH3 INCH2 INCH1 INCH0 = 0011 A3 INCH3 INCH2 INCH1 INCH0 = 0100 A4 INCH3 INCH2 INCH1 INCH0 = 0101 A5 INCH3 INCH2 INCH1 INCH0 = 0110 A6 INCH3 INCH2 INCH1 INCH0 = 0111 A7 INCH3 INCH2 INCH1 INCH0 = 1000 Ve REF+ INCH3 INCH2 INCH1 INCH0 = 1001 V REF /Ve REF INCH3 INCH2 INCH1 INCH0 = 1010 Temperature sensor INCH3 INCH2 INCH1 INCH0 = 1011 (V CC V SS )/2 INCH3 INCH2 INCH1 INCH0 = 1100 (V CC V SS )/2 or A12* INCH3 INCH2 INCH1 INCH0 = 1101 (V CC V SS )/2 or A13 * INCH3 INCH2 INCH1 INCH0 = 1110 (V CC V SS )/2 or A14 * INCH3 INCH2 INCH1 INCH0 = 1111 (V CC V SS )/2 or A15 * * on MSP430x22xx devices SHSx Sample-and-hold source: SHS1 SHS0 = 00 bit ADC10SC SHS1 SHS0 = 01 TIMER_A Output Unit 1 SHS1 SHS0 = 10 TIMER_A Output Unit 0 SHS1 SHS0 = 11 TIMER_A Output Unit 2 9 ADC10DF ADC10 data format: ADC10DF = 0 Binary ADC10DF = 1 Two s complement 8 ISSH Invert signal sample-and-hold ISSH = 0 The sample-input signal is not inverted ISSH = 1 The sample-input signal is inverted Copyright 2008 Texas Instruments 76

77 ADC10 (4/7) Registers ADC10CTL1, ADC10 Control Register 1 (low byte) ADC10DIVx ADC10SSELx CONSEQx ADC10BUSY Bit Description 7 5 ADC10DIVx ADC10 clock divider: ADC10DIV2 ADC10DIV1 ADC10DIV0 = 000 / 1 ADC10DIV2 ADC10DIV1 ADC10DIV0 = 001 / 2 ADC10DIV2 ADC10DIV1 ADC10DIV0 = 010 / 3 ADC10DIV2 ADC10DIV1 ADC10DIV0 = 011 / 4 ADC10DIV2 ADC10DIV1 ADC10DIV0 = 100 / 5 ADC10DIV2 ADC10DIV1 ADC10DIV0 = 101 / 6 ADC10DIV2 ADC10DIV1 ADC10DIV0 = 110 / 7 ADC10DIV2 ADC10DIV1 ADC10DIV0 = 111 / ADC10SSELx ADC10 clock source: ADC10SSEL1 ADC10SSEL0 = 00 ADC10OSC ADC10SSEL1 ADC10SSEL0 = 01 ACLK ADC10SSEL1 ADC10SSEL0 = 10 MCLK ADC10SSEL1 ADC10SSEL0 = 11 SMCLK 2 1 CONSEQx Conversion sequence mode: CONSEQ1 CONSEQ0 = 00 Single-channel, single-conversion CONSEQ1 CONSEQ0 = 01 Sequence-of-channels CONSEQ1 CONSEQ0 = 10 Repeat-single-channel CONSEQ1 CONSEQ0 = 11 Repeat-sequence-of-channel 0 ADC10BUSY ADC10 busy: ADC10BUSY = 0 No operation is active ADC10BUSY = 1 Sequence, sample, or conversion is active Copyright 2008 Texas Instruments 77

78 ADC10 (5/7) Registers ADC10AE0, Analogue (Input) Enable Control Register 0 Enables the analogue input of the ADC10: BIT0 => A0, BIT1 => A1, and so on. ADC10AE1, Analogue (Input) Enable Control Register 1 ( F2274) Additional analogue input enable control register. BIT4 => A12, BIT5 => A13, BIT6 => A14, and BIT7 => A15. ADC10MEM, Conversion-Memory Register Loaded with the conversion results; Numerical result format: Binary: Bits = 0. The results in the least significant 10 bits. 2 s complement: The results in the most significant 10 bits. Bits 5-0 = 0. 78

79 ADC10 (6/7) Registers ADC10DTC0, Data Transfer Control Register Reserved ADC10TB ADC10CT ADC10B1 ADC10FETCH Bit Description 3 ADC10TB ADC10 block mode: ADC10TB = 0 One-block transfer mode ADC10TB = 1 Two-block transfer mode 2 ADC10CT ADC10 continuous transfer ADC10CT = 0 Data transfer stops when a block(s) transfer is completed ADC10CT = 1 Data is transferred continuously 1 ADC10B1 block filled with ADC10 conversion results (two-block mode): ADC10B1 = 0 Block 2 is filled ADC10B1 = 1 Block 1 is filled 0 ADC10FETCH Normally set ADC10FETCH = 0 79

80 ADC10 (7/7) Registers ADC10DTC1, Data Transfer Control Register 1 This 8-bit register defines the number of transfers for each block; ADC10DTC1 = 0 DTC is disabled; ADC10DTC1 = 01h 0FFh Number of transfers per block. ADC10SA, Start Address Register for Data Transfer This 16-bit register defines the ADC10 start address for the DTC. It uses only the 15 most significant bits. Bit 0 is always read as 0. 80

81 ADC12 (1/2) Introduction The ADC12 module of the MSP430F2013 supports fast 12- bit analogue-to-digital conversions; The module contains: 12-bit SAR core; Sample select control; Reference current generator. 81

82 ADC12 block diagram: ADC12 (2/2) Introduction 82

83 ADC12 ADC12 Features It has same basic features as the ADC10, with the following differences: Monotonic 12-bit converter with no missing codes; Interrupt vector register for fast decoding of 18 ADC interrupts; Registers for storage of 16 conversion results; No Data Transfer Controller (DTC); 16 control registers ADC12MCTLx for free choice of channels on sequential modes; Can also convert some channels more than once in one loop (e.g. placing two measurements of the same voltage and one measurement of current in between to calculate power). 83

84 ADC12 12 bit ADC core 12 bit ADC core (enable with ADC12ON bit): Converts an analogue input to its 12-bit digital representation; Stores the result in a ADC12MEM register. The conversion is limited by the upper and lower limits: V R+ ; V R- The digital output (N ADC ) is: Full scale: N ADC = 0FFFh, when the input signal V R+ ; Zero: N ADC = 0000h, when the input signal V R-. Conversion results: Binary format: V N ADC 4096 V in R V V R R Two s-complement format. 84

85 Conversion clock selection; ADC12 Similarities to ADC10 ADC12 inputs and multiplexer; Analogue port selection (P6); The ADC12 inputs are multiplexed with the port P6 pins. Voltage reference generator: For proper operation requires storage capacitors across V REF+ and AV SS. Conversion modes; Integrated temperature sensor. 85

86 ADC12 (1/3) Sample and conversion timing An A/D conversion is initiated on the rising edge of SHI. The source for SHI (SHSx bits selection) can be: ADC12SC bit; Timer_A Output Unit 1; Timer_B Output Unit 0, or ; Output Unit 1. ADC12 timer trigger for reference settling: 86

87 ADC12 (2/3) Sample and conversion timing Sample-timing methods: SHP = 0: Extended sample mode: SHI signal directly controls SAMPCON; Defines the length of the sample period tsample; SAMPCON = 1 sampling is active; High-to-Low SAMPCON transition starts the conversion after synchronization with ADC12CLK. 87

88 ADC12 (3/3) Sample and conversion timing Sample-timing methods: SHP = 1: Pulse mode: SHI signal triggers the sampling timer; SHT0x and SHT1x bits (ADC12CTL0) defines the SAMPCON sample period, t sample ; The sampling timer keeps SAMPCON = 1 after synchronization with ADC12CLK. 88

89 ADC12 Conversion memory 16 ADC12MEMx conversion memory registers (configured by the associated ADC12MCTLx control register) to store conversion results. Non-sequential conversion (single- or repeat-singlechannel): CSTARTADDx define the first and single ADC12MCTLx for conversion. Sequential conversion (sequence-of- or repeat-sequenceof-channels): A sequence is started by the command found in the ADC12MCTLx register pointed to by CSTARTADDx; The pointer is incremented automatically to the next ADC12MCTLx for the next conversion; After ADC12MCTL15 the next conversion is ADC12MCTL0; The sequence runs until an EOS bit signals that this command is the last conversion of the actual sequence; The 16 ADC12MCTLx registers can contain more than one sequence. 89

90 ADC12 ADC12 interrupts The ADC12 has 18 interrupt sources: ADC12IFG0-ADC12IFG15: ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result; ADC12OV, ADC12MEMx overflow: ADC12OV is set when a conversion result is written to any ADC12MEMx before its previous conversion result was read; ADC12TOV, ADC12 conversion time overflow: ADC12TOV is set when another sample-and-conversion is requested before the current conversion is completed. The DMA is triggered after the conversion in single channel modes or after the completion of sequence of channel modes. 90

91 ADC12 ADC12 Interrupt vector generator Interrupt vector register ADC12IV used to determine which enabled ADC12 interrupt source requested an interrupt. Considerations: The highest priority enabled interrupt generates a number in the ADC12IV register (evaluated or added to the program counter to automatically call the appropriate routine); Any access, read or write, of the ADC12IV register automatically resets the ADC12OV or the ADC12TOV conditions, if either were the highest pending interrupt; ADC12IFGx bits are reset automatically by accessing their ADC12MEMx register or may be reset by software; If another interrupt is pending after servicing of an interrupt, another interrupt is generated. 91

92 ADC12 (1/6) Registers ADC12CTL0, ADC12 Control Register 0 (high byte) SHT1x SHT0x Bit Description SHT1x Sample-and-hold time (ADC12CLK cycles in the sampling period for registers ADC12MEM8 to ADC12MEM15): SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles SHT13 SHT12 SHT11 SHT10 = ADC12CLK cycles 11-8 SHT0x Sample-and-hold time (ADC12CLK cycles in the sampling period for registers ADC12MEM0 to ADC12MEM7). These bits are configured as the previous ones (SHT1x). 92

93 ADC12 (2/6) Registers ADC12CTL0, ADC12 Control Register 0 (low byte) MSC REF2_5V REFON ADC12ON ADC12OVIE ADC12TOVIE ENC ADC12SC The bold bits have the same function as the ADC10. Refer to the ADC10 to see their description. Bit Description 3 ADC12OVIE ADC12MEMx overflow-interrupt enable (The GIE bit must also be set to enable the interrupt): ADC12OVIE = 0 Overflow interrupt disabled ADC12OVIE = 1 Overflow interrupt enabled 2 ADC12TOVIE ADC12 conversion-time-overflow interrupt enable (The GIE bit must also be set to enable the interrupt): ADC12TOVIE = 0 Conversion time overflow interrupt disabled ADC12TOVIE = 1 Conversion time overflow interrupt enabled 93

94 ADC12 (3/6) Registers ADC12CTL1, ADC12 Control Register CSTARTADDx SHSx SHP ISSH ADC12DIVx ADC12SSELx CONSEQx ADC12BUSY The bold bits have the same funciton as the ADC10. Refer to the ADC10 to see their description. Bit Description CSTARTADDx Conversion start address. These bits select which ADC12MEMx is used for a single conversion or for the first conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh, corresponding to ADC12MEM0 to ADC12MEM15. 9 SHP Sample-and-hold mode select: SHP = 0 SAMPCON signal is sourced from the sample-input signal SHP = 1 SAMPCON signal is sourced from the sampling timer 94

95 ADC12 (4/6) Registers ADC12MEMx, Conversion-Memory Register Loaded with the conversion results. Bits are always 0. The results are stored in the least significant 12 bits. ADC12MCTLx, ADC12 Conversion Memory Control Registers EOS SREFx INCHx Bit Description 7 EOS Indicates the last conversion in a sequence: EOS = 0 Not end of sequence EOS = 1 End of sequence 6-4 SREFx Select voltage reference: V R+ V R SREF2 SREF1 SREF0 = 000 AV CC AV SS SREF2 SREF1 SREF0 = 001 V REF+ AV SS SREF2 SREF1 SREF0 = 010 Ve REF+ AV SS SREF2 SREF1 SREF0 = 011 Ve REF+ AV SS SREF2 SREF1 SREF0 = 100 AV CC V REF /Ve REF SREF2 SREF1 SREF0 = 101 V REF+ V REF /Ve REF SREF2 SREF1 SREF0 = 110 Ve REF+ V REF /Ve REF SREF2 SREF1 SREF0 = 111 Ve REF+ V REF /Ve REF 95

96 ADC12 (5/6) Registers ADC12MCTLx, ADC12 Conversion Memory Control Registers (INCHx depends on the device) EOS SREFx INCHx Bit 7 EOS Indicates the last conversion in a sequence: EOS = 0 Not end of sequence EOS = 1 End of sequence Description 6-4 SREFx Select voltage reference: SREF2 SREF1 SREF0 = 000 V R+ AV CC V R AV SS SREF2 SREF1 SREF0 = 001 V REF+ AV SS SREF2 SREF1 SREF0 = 010 Ve REF+ AV SS SREF2 SREF1 SREF0 = 011 Ve REF+ AV SS SREF2 SREF1 SREF0 = 100 AV CC V REF /Ve REF SREF2 SREF1 SREF0 = 101 V REF+ V REF /Ve REF SREF2 SREF1 SREF0 = 110 Ve REF+ V REF /Ve REF SREF2 SREF1 SREF0 = 111 Ve REF+ V REF /Ve REF 3-0 INCHx Input channel select: INCH3 INCH2 INCH1 INCH0 = 0000 A0 INCH3 INCH2 INCH1 INCH0 = 0001 A1 INCH3 INCH2 INCH1 INCH0 = 0010 A2 INCH3 INCH2 INCH1 INCH0 = 0011 A3 INCH3 INCH2 INCH1 INCH0 = 0100 A4 INCH3 INCH2 INCH1 INCH0 = 0101 A5 INCH3 INCH2 INCH1 INCH0 = 0110 A6 INCH3 INCH2 INCH1 INCH0 = 0111 A7 INCH3 INCH2 INCH1 INCH0 = 1000 Ve REF+ INCH3 INCH2 INCH1 INCH0 = 1001 V REF /Ve REF INCH3 INCH2 INCH1 INCH0 = 1010 Temperature sensor INCH3 INCH2 INCH1 INCH0 = 1011 (AV CC AV SS )/2 INCH3 INCH2 INCH1 INCH0 = 1100 A12 INCH3 INCH2 INCH1 INCH0 = 1101 A13 INCH3 INCH2 INCH1 INCH0 = 1110 A14 INCH3 INCH2 INCH1 INCH0 = 1111 A15 96

97 ADC12 (6/6) Registers ADC12IE, ADC12 Interrupt Enable Register This 16-bit register enables (ADC12IEx = 1) or disables (ADC12IEx = 0), the interrupt request for the ADC12IFGx bits. ADC12IFG, ADC12 Interrupt Flag Register Each bit of this 16-bit register is set when the corresponding ADC12MEMx is loaded with a conversion result and reset if the corresponding ADC12MEMx is accessed by software. 97

98 Sigma-Delta ADC Introduction (1/11) Sigma-Delta (SD) converter determines the digital word: By oversampling the input signal using sigma-delta modulation; Applying digital filtering; Reducing data rate by collecting modulator output bits (decimation). 98

99 Sigma-Delta ADC Introduction (2/11) Delta modulator: Quantizes the difference between the current analogue input signal and the average of the previous samples. Example: 1st order modulator (simplest form): Quantization (comparator): Output={1,0} if Input={+,-} Demodulator (integrator - 1 bit DAC): Output={, } if Input={1,0}. 99

100 Sigma-Delta ADC Introduction (3/11) Delta modulator: Density of 1 s" at the modulator OUT is proportional to IN signal: Increasing IN, the comparator generates a greater number of 1 s"; Decreasing IN, the comparator generates a lesser number of 1 s". By summing the error voltage, the integrator acts as a: Lowpass filter for the input signal; Highpass filter for the quantization noise. 100

101 Sigma-Delta ADC Introduction (4/11) Delta modulator: Most quantization noise is pushed into higher frequencies; Oversampling changes noise distribution (but not total noise); Quantization noise limits the dynamic range of the ADC; Noise is the round-off error of analogue signal quantization. 101

102 Sigma-Delta ADC Introduction (5/11) Delta modulator: As the OSR (Over-Sampling Ratio) increases, the noise decreases (SNR increases); As the order of the modulator increases, the noise decreases. 102

103 Sigma-Delta ADC Introduction (6/11) Digital Filter: Averages the 1-bit data stream; Improves the analogue to digital conversion resolution; Removes quantization noise outside the band of interest; Determines signal bandwidth, settling time and stopband rejection. 103

104 Sigma-Delta ADC Introduction (7/11) Digital Filter: There are several types of digital filters: Finite Impulse Response (FIR) filter: output is dependent only on past and present values of the input; Sinc filter: Removes all frequency components above a given bandwidth, leaving the the low frequency components. It has linear phase; Infinite Impulse Response (IIR) filter: the output is dependent on past and present values of both the input and the output; Averaging, Moving average filter. 104

105 Sigma-Delta ADC Introduction (8/11) Digital Filter: SD converters: widely used lowpass filter: Sinc³ or Sinc 5 types. 105

106 Sigma-Delta ADC Introduction (9/11) Digital Filter: Main advantage of Sinc filter: notch response. The notch position is directly related to the output data rate, allowing high frequency noise reduction and 60 Hz mains. 106

107 Sigma-Delta ADC Introduction (10/11) Digital Filter: The output of the digital filter will be a data stream: 107

108 Sigma-Delta ADC Introduction (11/11) Decimation Digital Filter: Decimation: Reduces the sampling rate down from the oversampling rate without losing information (eliminates redundant data); Using the Nyquist theorem (f sample >2 f input ) and the oversampling at the delta modulator, the input signal can be reliably reconstructed without distortion. 108

109 SD16(A) UBI MSP430 SD16(A) Sigma-Delta ADC: Introduction SD16_A features SD ADC core Analogue input range and PGA Voltage reference generator Analogue input pair selection Analogue input characteristics and setup Digital filter Output data format Conversion modes Integrated temperature sensor SD16_A interrupts Interrupt vector generator (SD16IV) SD16 registers 109

110 SD16(A) (1/2) Introduction Applications MSP430 devices with up to 7 SD ADCs: Portable medical (F42xx and FG42xx); Energy metering (FE42x(A), F47xx, F471xx); Generic applications (F42x and F20x3). SD16_A: ez430-f2013 hardware development tool; SD16_A supports: 16-bit SD core; Reference generator; External analogue inputs; Internal V CC sense; Integrated temperature sensor. 110

111 SD16_A block diagram: SD16(A) (2/2) Introduction 111

112 SD16(A) SD16_A Features 16-bit sigma-delta architecture; Up to eight multiplexed differential analogue inputs per channel; Software selectable on-chip reference voltage generation (1.2 V); Software selectable internal or external reference; Built-in temperature sensor; Up to 1.1 MHz modulator input frequency; Selectable low-power conversion mode. 112

113 SD16(A) 16 bit SD ADC core The analogue-to-digital conversion is performed by a 1-bit second-order oversampling sigma-delta modulator; A single-bit comparator within the modulator quantizes the input signal with the modulator frequency, f M ; The resulting 1-bit data stream is averaged by the digital decimation filter (comb type filter with selectable oversampling) for the conversion result; The decimation filter has ratios of up to Additional filtering can be done in software. 113

114 SD16(A) Analogue Input Range and PGA The full-scale (FS) input voltage range for each analogue input pair is dependent on the gain setting of the PGA (= 1, 2, 4, 8, 16 & 32x); The maximum FS range is ±V FS : Vref VFS 2 GAIN PGA 114

115 SD16(A) Voltage Reference Generator Voltage reference options: Internal reference (1.2 V): SD16REFON=1, SD16VMIDON=0; External reference: SD16REFON=0, SD16VMIDON=0; Internal refeference, with reference with buffered output: SD16REFON=1, SD16VMIDON=1; To reduce noise it is recommended to connect an external 100-nF capacitor from V REF to AV SS. 115

116 SD16(A) Analogue Input Pair Selection The SD16_A can convert up to 8 differential input pairs multiplexed into the PGA; The available analogue input pairs are: A0-A4: External to the device; A5: Resistive divider to measure the supply voltage (AV CC /11); A6: Internal temperature sensor; A7: Offset shunt (used for calibration of SD16_A input PGA offset measurement). 116

117 SD16(A) Analogue Input Characteristics and Setup Analogue input equivalent circuit for the ez430-f2013: Max. sampling frequency, f S : t f Settling S V Ax ( R 1 2 t S Settling max 1 k ) AV 2 CC C V S S, GAIN ln V AV 2 CC 17 2 REF V S V Ax PGA gain C S pf pf pf 8 5 pf pf pf 117

118 SD16(A) Analogue Input Step Response Sinc 3 comb digital filter needs 3 data-word periods to settle; SD16INTDLY = 00h, conversion interrupt requests do not begin until the 4th conversion after a start condition. 118

119 SD16(A) Digital Filter Processes the 1-bit data stream from the modulator using a Sinc 3 comb digital filter; Take into consideration that: Oversampling rate is given by: OSR = f M /f S ; The first filter notch is at: f S = f M /OSR; Modify the notch frequency adjustment with: SD16SSELx and SD16DIVx: Change f M ; SD16OSRx and SD16XOSR bits: Change OSR. Number of output bits depends on the OSR, DR and number format, ranging from 15 to 30 bits. 119

120 SD16(A) Output Data Format Selected with SD16DF and SD16UNI bits: Two s complement; Offset binary; Unipolar. SD16UNI = 0 SD16UNI = 0 SD16UNI = 1 SD16DF = 0 SD16DF = 1 SD16DF = 0 120

121 SD16(A) (1/2) Conversion modes Single conversion: The channel is converted once (SD16SNGL = 1); After conversion completion: SD16SC = 0; Clearing SD16SC before the conversion is completed: Immediately stops conversion of the channel; Powers down the channel; Turns off the corresponding digital filter; The value in SD16MEM0 can change. 121