Tiny 12-Bit ADC Delivers 2.2Msps Through 3-Wire Serial Interface by Joe Sousa Introduction

Transcription

1 DESIGN FETURES Tiny -Bit DC Delivers.Msps Through -Wire Serial Interface by Joe Sousa Introduction LTC Serial interfaces occupy little routing space, but usually limit the speed of an DC. The LTC has a full conversion speed of.msps and a very compact -wire interface for connecting to DSPs and microprocessors without glue logic. It comes in a -pin narrow SSOP package. This minuscule package (mil mil footprint) and compact serial interface are easy to fit close to sensors to best preserve analog signal integrity. Other serial -bit DCs have sample rates limited to hundreds of kilosamples-per-second, which limits their utility in high speed data acquisition systems. This slow sample rate, combined with poor distortion characteristics, makes them unsuitable for tracking high frequency signals. The LTC will capture, in less than ns, the fast steps from an external analog input multiplexer for high speed data acquisition and it will digitize high frequency signals very accurately, with a db S/(ND) (signal-to-noise plus distortion ratio) at.mhz, for communications or signal processing systems. -Wire Serial Interface for DSPs, Cables and Optocouplers Figure a shows an example of interfacing the LTC to the TMSCx DSP. No glue logic is needed to interface the LTC to V -WIRE SERIL INTERFCE LINK TMSCX Figure a. DSP serial interface to the TMSCX DSPs. The buffered serial port of the TMSCx talks directly to a dedicated kb segment of internal buffer memory. The DC s serial data is collected in the k buffer, in two alternating kb segments, in real time, at the full.msps conversion rate of the LTC. Consult the LTC data sheet for the TMSCx assembly code for this application. V V LTC µf SIGNL D Ω Ω Ω Ω Ω TMSCX.Msps.MHz LTC QUD DRIVER PIN = EN PIN = ENB CTEGORY FIVE SHIELDED CBLE UP TO FEET LTC QUD RECEIVER Figure b. The LTC -wire serial port sends data over feet of category twisted pair with the LTC/LTC quad driver/receiver pairs Linear Technology Magazine February

2 DESIGN FETURES V V SIGNL IN LTC D µf N Ω Ω N HCPL- TMSCX N HCPL- Msps Ω MHz Figure c. The LTC is easily isolated with high speed optocouplers The minuscule -pin narrow SSOP package of the LTC saves space in compact systems or systems that require a large number of DCs. It can be located near the signal conditioning circuitry and send serial output data over a PC board trace of up to one foot in length to the DSP, as shown in Figure a. Figure b shows the LTC/ LTC quad cable driver/receiver interfacing the LTC to the DSP port to send the serial data over longer distances. The category- quad twisted pair shielded cable can extend up to feet without data corruption. Because the, and signals originate at the LTC, they arrive at the serial port with similar delays and remain synchronized. When the data is received at the serial port of a DSP or other processor, the port must be programmed to respond to the appropriate and edges. It is also necessary to check where the -bit output DT sits in the -bit data frame. The TMSCx serial port RED instructions can shift the -bit data to the preferred position within the -bit data frame. The serial interface lends itself to galvanic isolation with external optocouplers. Figure c shows how to isolate the LTC with the HPCL- dual optocoupler. The ns propagation delays through the dual optocouplers cancel to maintain a good timing match between the, and signals. The LTC, running at a Msps conversion rate, sends -bit data frames through the HPCL- optocouplers at MB/s. µf GIN SMPLE- ND-HOLD.V µf k LTC k µf LTC V OR V. D -BIT DC TIMING LOGIC V SS D V or V Serial Interface without Spurious Noise Figure shows the block diagram of the LTC. The internal architecture has been optimized to send out data serially during conversion, without degradation of conversion accuracy due to digital noise. The MHz clock input at the pin () and the external.msps conversion start input at the pin () do not inject noise into the internal analog signal path of the DC. s a result, the analog accuracy of the LTC is insensitive to the phase, duty cycle or amplitude (V or V) of the external digital inputs. The pin () swings from the voltage at the pin () to the voltage at the pin () to allow direct interfacing to V or V DSPs and microprocessors. The LTC is ideal in multiple-ground systems, where the differential input is connected to one ground, the supplies and grounds of the LTC connect to a second, local ground and the output ground connects to a third, digital ground. V Figure. LTC block diagram V OR V OUTPUT BUFFER BIP/UNI Linear Technology Magazine February

3 DESIGN FETURES MPLITUDE (db) f SMPLE =.Hz f SINE =.Hz SMPLES ND TH TH RD TH.. Figure. Sine wave spectrum plot (bipolar ±V) with ±V supplies Very High SFDR in Single V Supply pplications proprietary sampling front end circuit achieves exceptional dynamic performance at the.mhz Nyquist frequency: db THD with ±V supplies and db THD with a single V supply. Figures and show the spectra from a.mhz Nyquist frequency sine wave with ±V supplies and a single V supply, respectively. With this very clean spectrum, the LTC minimizes crosstalk and interference in communications applications where the spectrum is divided into many frequency slots. The LTC maintains db S/(ND) with a.mhz input sine wave, with either a single V or ±V supplies. Positive signals can be applied with single or dual supplies and bipolar signals are easily accommodated with dual-supply operation. The full power bandwidth of the LTC is MHz; the full linear bandwidths (SIND > db) of MHz with ±V supplies and.mhz with a single V supply round out the exceptional dynamic performance of the LTC. The wideband signal conversion purity shown in Figures a and b makes the LTC well suited for digitizing sine wave signals well above the.mhz Nyquist frequency. Figures and show that transfer function purity, represented by the differential and integral linearity plots, is maintained at the full.msps conversion rate. MPLITUDE (db) f SMPLE =.Hz f SINE =.Hz SMPLES ND TH TH RD TH.. Figure. Sine wave spectrum plot (unipolar VV) with single V supply True Differential Inputs Cancel Wideband Common Mode Noise The front-end sampling circuit acquires the input signal differentially from the and analog inputs. Except for the sign inversion, these two inputs are identical. The wide common mode rejection bandwidth of the LTC (db at MHz input) affords excellent ground noise rejection in complex, noisy systems. Figure a shows the CMRR performance vs input frequency. The differential inputs are very easy to interface to a wide range of signal sources. Grounding the input near the signal source reduces common mode ground noise. Setting the BIP/UNI pin () to a logic high selects the bipolar ±.V range; setting it to a logic low selects the unipolar V to.v range. The V to.v unipolar range is ideal for single V supply applications where the input is grounded and the signal is applied to the input. The ±.V bipolar range centered around midsupply can also be used in single V supply applications, with the input tied to a.vdc source. lternately, the full ±.V bipolar range can be driven with a pair of complementary ±.V signals into and. This limits the swing of external single V supply amplifiers to their most linear region, from.v to.v. Figure b shows half of the LT dual op amp driving the LTC in this fully differential configuration with a single V supply. EFFECTIVE NUMBER OF BITS DNL (LSB) INL (LSB) f SMPLE =.MHz INPUT FREQUENCY (Hz) Figure a. ENOBs and SIND vs input frequency (bipolar ±V) with ±V supplies f SMPLE =.MHz INPUT FREQUENCY (Hz) Figure b. ENOBs and SIND vs input frequency (unipolar VV) with single V supply EFFECTIVE NUMBER OF BITS f SMPLE =.MHz CODE Figure. Differential nonlinearity vs output code (unipolar VV) f SMPLE =.MHz CODE Figure. Integral nonlinearity vs output code (unipolar VV) SIGNL-TO-NOISE DISTORTION (db) SIGNL-TO-NOISE DISTORTION (db) Linear Technology Magazine February

4 DESIGN FETURES COMMON MODE REJECTION RTIO (db). Figure a. CMRR vs input frequency Internal or External Reference The internal.v reference (multiplied by at the output) sets the bipolar and unipolar ranges to ±.V and V to.v, respectively. Tying the Gain pin () to the pin () cuts the reference voltage at the pin and analog input spans in half, to.v. The internal reference can also be disabled by tying the Gain pin to V CC and tying an external reference with an output between V and V directly to. The single-ended unipolar input range of Figure a s circuit depends on the DC s output voltage, which acts as an infinite sample-and-hold for signals such as a CCD sensor dark V IN = V CM ±V current or similar applications, as determined by software procedures. The LTC -bit serial DC applies a voltage to the GIN and pins of the DC, in this case subtracting the voltage from the voltage, thus maintaining a positive full scale of.v while varying zero scale over the range of V to V. This adjustment of the low end of the scale preserves the full -bit dynamic range of the DC to digitize the input video signal between the dark-current value and.v. The dark-current value must be a slow-moving DC value V V µf µf D Ω V P-P IN pf pf BIP/UNI k k pf LTC V.µF IN µf R GIN Ω / LT V SS V P-P C f IN (MIN) πrc Figure b. True differential inputs accept V P-P bipolar differential signal with V P-P swings on each input and an effective gain of from the LT inputs. SIND =.db with a MHz input. so that the DC and the reference buffer amplifier can drive their respective µf capacitors. The LTC DC is stable with a µf load; care must be taken when substituting capacitors. Figure b shows alternative connections to emulate the functional range of a flash converter in an image scanner application. The top and bottom of the conversion ranges are set independently by the LTC DC, just like the top and bottom voltages of the internal resistor ladder in a flash converter. The bottom of the V SCNNER VIDEO LT µf IN LTC SCNNER VIDEO / LTC LT µf IN LTC DISBLED IN HIGH IMPEDNCE WITH PIN HIGH k k / LTC / LTC GIN k.v BNDGP V GIN k.v BNDGP µf µf Figure a. The use of a DC allows software adjustment of the lower end of the DC range for applications such as dark-current cancellation. Figure b. dual DC allows software adjustment of both the fullscale and zero-scale voltages of the DC, emulating the behavior of a flash converter. Linear Technology Magazine February

5 DESIGN FETURES SUPPLY CURRENT (m). DUL ±V SINGLE V NP MODE SLEEP MODE (WITH EXTERNL ). V SS CURRENT DUL ±V V SS CURRENT. SINGLE V.. SMPLE RTE (MHz) Figure. Current consumption vs sample rates for various operating modes and supply configurations conversion range starts at the darkcurrent value and the top of the range is set externally to match the maximum possible output from the image scanner. The voltage at (pin ) may vary from V to V; that at VREF (pin ) may vary from V to V. The LT input buffer amplifiers may not be necessary if the image sensor has a low input impedance (<Ω). Reducing Power at Low Sample Rates The LTC consumes mw in normal operation, on either single V or ±V supplies. NP and SLEEP modes cut back power drain to mw and mw, respectively. NP mode leaves the reference on and takes only ns to wake up, making it ideal for saving power between conversions in lower-sample-rate applications. SLEEP mode also shuts down the reference and takes ms to wake up. The REFREDY bit in the output data stream indicates when the reference has settled to full accuracy. NP and SLEEP modes are easily set with two or four pulses at the pin () input, respectively. One or more pulses at the pin () input wakes up the LTC for conversion. Figure shows the reduced power consumption while the sample rate is reduced and the NP or SLEEP modes is used between conversions. For example, an undersampling application with NP mode between conversions at a ksps sample rate draws only mw. Conclusion The LTC has all the speed and C and DC performance of fast -bit DCs with parallel data interfaces, but it offers a much smaller, glueless serial interface that saves space in the -pin narrow SSOP package. The tiny LTC can be placed right at the sensor for optimum analog signal capture and the compact - wire serial interface can be routed through a system board, through a cable or through an isolation barrier, to serial ports on DSPs and other processors.