Power Distribution Networks with On-Chip Decoupling Capacitors

Transcription

1 Power Distribution Networks with On-Chip Decoupling Capacitors

2 Mikhail h Popovich Andrey V. Mezhiba Eby G. Friedman Power Distribution Networks with On-Chip Decoupling Capacitors ABC

3 Mikhail Popovich University of Rochester Rochester, NY USA Andrey V. Mezhiba Intel Corporation Hillsboro, OR USA Eby G. Friedman University of Rochester Rochester, NY USA Library of Congress Control Number: ISBN e-isbn Springer Science + Business Media, LLC All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science + Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights springer.com

4 To Oksana and Elizabeth To Elizabeth To Laurie, Joseph, and Samuel

5 Preface The purpose of this book is to provide insight and intuition into the behavior and design of power distribution systems with decoupling capacitors for application to high speed integrated circuits. The primary objectives are threefold. First, to describe the impedance characteristics of the overall power distribution system, from the voltage regulator through the printed circuit board and package onto the integrated circuit to the power terminals of the on-chip circuitry. The second objective of this book is to discuss the inductive characteristics of on-chip power distribution grids and the related circuit behavior of these structures. Finally, the third primary objective is to present design methodologies for efficiently placing on-chip decoupling capacitors in nanoscale integrated circuits. Technology scaling has been the primary driver behind the amazing performance improvement of integrated circuits over the past several decades. The speed and integration density of integrated circuits have dramatically improved. These performance gains, however, have made distributing power to the on-chip circuitry a difficult task. Highly dense circuitry operating at high clock speeds have increased the distributed current to many tens of amperes, while the noise margin of the power supply has shrunk consistent with decreasing power supply levels. These trends have elevated the problems of power distribution and allocation of the on-chip decoupling capacitors to the forefront of several challenges in developing high performance integrated circuits. This book is based on the body of research carried out by Mikhail Popovich from 2001 to 2007 and Andrey V. Mezhiba from 1998 to 2003 at the University of Rochester during their doctoral studies under the supervision of Professor Eby G. Friedman. It is apparent to

6 VIII Preface the authors that although various aspects of the power distribution problem have been addressed in numerous research publications, no text exists that provides a unified focus on power distribution systems and related design problems. Furthermore, the placement of on-chip decoupling capacitors has traditionally been treated as an algorithmic oriented problem. A more electrical perspective, both circuit models and design techniques, has been used in this book for presenting how to efficiently allocate on-chip decoupling capacitors. The fundamental objective of this book is to provide a broad and cohesive treatment of these subjects. Another consequence of higher speed and greater integration density has been the emergence of inductance as a significant factor in the behavior of on-chip global interconnect structures. Once clock frequencies exceeded several hundred megahertz, incorporating on-chip inductance into the circuit analysis process became necessary to accurately describe signal delays and waveform characteristics. Although on-chip decoupling capacitors attenuate high frequency signals in power distribution networks, the inductance of the on-chip power interconnect is expected to become a significant factor in multi-gigahertz digital circuits. An important objective of this book, therefore, is to clarify the effects of inductance on the impedance characteristics of on-chip power distribution grids and to provide an understanding of related circuit behavior. The organization of the book is consistent with these primary goals. The first eight chapters provide a general description of distributing power in integrated circuits with decoupling capacitors. The challenges of power distribution are introduced and the principles of designing power distribution systems are described. A general background to decoupling capacitors is presented followed by a discussion of the use of a hierarchy of capacitors to improve the impedance characteristics of the power network. An overview of related phenomena, such as inductance and electromigration, is also presented in a tutorial style. The following seven chapters are dedicated to the impedance characteristics of on-chip power distribution networks. The effect of the interconnect inductance on the impedance characteristics of on-chip power distribution networks is investigated. The implications of these impedance characteristics on circuit behavior are also discussed. On-chip power distribution grids are described, exploiting multiple power supply voltages and multiple grounds. Techniques and algorithms for the computer-aided design and

7 Preface IX analysis of power distribution networks are also described; however, the emphasis of the book is on developing circuit intuition and understanding the electrical principles that govern the design and operation of power distribution systems. The remaining five chapters focus on the design of a system of on-chip decoupling capacitors. Methodologies for designing power distribution grids with on-chip decoupling capacitors are also presented. These techniques provide a solution for determining the location and magnitude of the on-chip decoupling capacitance to mitigate on-chip voltage fluctuations. Acknowledgments The authors would like to thank Alex Greene and Katelyn Stanne from Springer for their support and assistance. We are particularly thankful to Bill Joyner and Dale Edwards from the Semiconductor Research Corporation, and Marie Burnham, Olin Hartin, and Radu Secareanu from Freescale Semiconductor Corporation for their continued support of the research project that culminated in this book. The authors would also like to thank Emre Salman for his corrections and suggestions on improving the quality of the book. Finally, we are grateful to Michael Sotman and Avinoam Kolodny from Technion Israel Institute of Technology for their collaboration and support. The original research work presented in this book was made possible in part by the Semiconductor Research Corporation under Contract Nos. 99 TJ 687 and 2004 TJ 1207, the DARPA/ITO under AFRL Contract F K 0182, the National Science Foundation under Contract Nos. CCR and CCF , grants from the New York State Office of Science, Technology & Academic Research to the Center for Advanced Technology in Electronic Imaging Systems, and by grants from Xerox Corporation, IBM Corporation, Lucent Technologies Corporation, Intel Corporation, Eastman Kodak Company, Intrinsix Corporation, Manhattan Routing, and Freescale Semiconductor Corporation. Rochester, New York Hillsboro, Oregon June 2007 Mikhail Popovich and Eby G. Friedman Andrey V. Mezhiba

8 Contents 1 Introduction Evolution of integrated circuit technology Evolutionofdesignobjectives The problem of power distribution Deleterious effects of power distribution noise Signal delay uncertainty On-chipclockjitter Noisemargindegradation Degradation of gate oxide reliability Bookoutline Inductive Properties of Electric Circuits Definitions of inductance Field energy definition Magnetic flux definition Partial inductance Net inductance Variation of inductance with frequency Uniform current density approximation Inductance variation mechanisms Simple circuit model Inductive behavior of circuits Inductive properties of on-chip interconnect Summary Properties of On-Chip Inductive Current Loops Introduction... 59

9 XII Contents 3.2 Dependence of inductance on line length Inductive coupling between two parallel loop segments Application to circuit analysis Summary Electromigration Physical mechanism of electromigration Electromigration-induced mechanical stress Steady state limit of electromigration damage Dependence of electromigration lifetime on the line dimensions Statistical distribution of electromigration lifetime Electromigration lifetime under AC current Electromigration in novel interconnect technologies Designing for electromigration reliability Summary High Performance Power Distribution Systems Physical structure of a power distribution system Circuit model of a power distribution system Output impedance of a power distribution system A power distribution system with a decoupling capacitor Impedance characteristics Limitations of a single-tier decoupling scheme Hierarchical placement of decoupling capacitance Resonance in power distribution networks Fullimpedancecompensation Case study Designconsiderations Inductance of the decoupling capacitors Interconnect inductance Limitations of the one-dimensional circuit model Summary Decoupling Capacitance Introductiontodecouplingcapacitance Historical retrospective Decoupling capacitor as a reservoir of charge Practicalmodelofadecouplingcapacitor

10 Contents XIII 6.2 Impedance of power distribution system with decouplingcapacitors Target impedance of a power distribution system Antiresonance Hydraulic analogy of hierarchical placement of decouplingcapacitors Intrinsic vs intentional on-chip decoupling capacitance Intrinsicdecouplingcapacitance Intentionaldecouplingcapacitance Typesofon-chipdecouplingcapacitors Polysilicon-insulator-polysilicon (PIP) capacitors MOScapacitors Metal-insulator-metal(MIM)capacitors Lateralfluxcapacitors Comparison of on-chip decoupling capacitors On-chipswitchingvoltageregulator Summary On-Chip Power Distribution Networks Styles of on-chip power distribution networks Basic structure of on-chip power distribution networks Improving the impedance characteristics of on-chip power distribution networks Evolution of power distribution networks in Alpha microprocessors Die-packageinterface Otherconsiderations Summary Computer-Aided Design and Analysis Design flow for on-chip power distribution networks Linear analysis of power distribution networks Modeling power distribution networks Characterizing the power current requirements of on-chip circuits Numerical methods for analyzing power distribution networks

11 XIV Contents 8.6 Allocationofon-chipdecouplingcapacitors Charge-basedallocationmethodology Allocation strategy based on the excessive noise amplitude Allocation strategy based on excessive charge Summary Inductive Properties of On-Chip Power Distribution Grids Power transmission circuit Simulationsetup Gridtypes Inductance versus line width Dependence of inductance on grid type Non-interdigitated versus interdigitated grids Paired versus interdigitated grids Dependence of Inductance on grid dimensions Dependence of inductance on grid width Dependence of inductance on grid length Sheet inductance of power grids Efficient computation of grid inductance Summary Variation of Grid Inductance with Frequency Analysisapproach Discussion of inductance variation Circuit models Analysis of inductance variation Summary Inductance/Area/Resistance Tradeoffs Inductance vs. resistance tradeoff under a constant grid areaconstraint Inductance vs. area tradeoff under a constant grid resistanceconstraint Summary Scaling Trends of On-Chip Power Distribution Noise Priorwork

12 Contents XV 12.2 Interconnect characteristics Global interconnect characteristics Scaling of the grid inductance Flip-chip packaging characteristics Impactofon-chipcapacitance Model of power supply noise Power supply noise scaling Analysis of constant metal thickness scenario Analysis of the scaled metal thickness scenario ITRSscalingofpowernoise Implications of noise scaling Summary Impedance Characteristics of Multi-Layer Grids Electrical properties of multi-layer grids Impedance characteristics of individual grid layers Impedance characteristics of multi-layer grids Case study of a two layer grid Simulationsetup Inductive coupling between grid layers Inductive characteristics of a two layer grid Resistive characteristics of a two layer grid Variation of impedance with frequency in a two layergrid Design implications Summary Multiple On-Chip Power Supply Systems ICs with multiple power supply voltages Multiple power supply voltage techniques Clustered voltage scaling (CVS) Extended clustered voltage scaling (ECVS) Challenges in ICs with multiple power supply voltages Diearea Powerdissipation Design complexity Placementandrouting Optimum number and magnitude of available power supply voltages

13 XVI Contents 14.4 Summary On-Chip Power Distribution Grids with Multiple Supply Voltages Background Simulationsetup Power distribution grid with dual supply and dual ground InterdigitatedgridswithDSDG TypeIinterdigitatedgridswithDSDG TypeIIinterdigitatedgridswithDSDG Paired grids with DSDG Type I paired grids with DSDG Type II paired grids with DSDG Simulationresults Interdigitated power distribution grids without decouplingcapacitors Paired power distribution grids without decouplingcapacitors Power distribution grids with decoupling capacitors Dependence of power noise on the switching frequency of the current loads Design implications Summary Decoupling Capacitors for Multi-Voltage Power Distribution Systems Impedance of a power distribution system Impedance of a power distribution system Antiresonance of parallel capacitors Dependence of impedance on power distribution systemparameters Case study of the impedance of a power distribution system Voltage transfer function of power distribution system Voltage transfer function of a power distribution system Dependence of voltage transfer function on power distribution system parameters

14 Contents XVII 16.4 Case study of the voltage response of a power distribution system Overshoot-free magnitude of a voltage transfer function Tradeoff between the magnitude and frequency range Summary On-chip Power Noise Reduction Techniques in High Performance ICs Ground noise reduction through an additional low noise on-chipground Dependence of ground bounce reduction on system parameters Physical separation between noisy and noise sensitive circuits Frequency and capacitance variations Impedanceofanadditionalgroundpath Summary Effective Radii of On-Chip Decoupling Capacitors Background Effective radius of on-chip decoupling capacitor based onatargetimpedance Estimation of required on-chip decoupling capacitance Dominantresistivenoise Dominant inductive noise Criticallinelength Effectiveradiusasdeterminedbychargetime Design methodology for placing on-chip decoupling capacitors Model of on-chip power distribution network Case study Design implications Summary Efficient Placement of Distributed On-Chip Decoupling Capacitors Technologyconstraints Placing on-chip decoupling capacitors in nanoscale ICs 437

15 XVIII Contents 19.3 Design of a distributed on-chip decoupling capacitor network Design tradeoffs in a distributed on-chip decoupling capacitornetwork Dependence of system parameters on R Minimum C Minimum total budgeted on-chip decoupling capacitance Design methodology for a system of distributed on-chip decouplingcapacitors Case study Summary Impedance/Noise Issues in On-Chip Power Distribution Networks Scalingeffectsinchip-packageresonance Propagation of power distribution noise Local inductive behavior Summary Conclusions Appendices A B C D Mutual Loop Inductance in Fully Interdigitated Power Distribution Grids with DSDG Mutual Loop Inductance in Pseudo-Interdigitated Power Distribution Grids with DSDG Mutual Loop Inductance in Fully Paired Power Distribution Grids with DSDG Mutual Loop Inductance in Pseudo-Paired Power Distribution Grids with DSDG References Index

16 List of Figures 1.1 Microphotographs of the first integrated circuit (IC) and first monolithic IC along with a high performance, high complexity IC Evolution of transistor count of microprocessors and memoryics Evolution of microprocessor clock frequency Evolution of design criteria in CMOS integrated circuits Microphotograph of the Evolution of microprocessor power consumption Basic power delivery system Evolution of the average current in high performance microprocessors Increase in power current of microprocessors with technologyscaling ScalingoftheCMOSnoisemargins Projections of the target impedance of a power distribution system A grid structured power distribution network Cycle-to-cycle jitter of a clock signal Peak-to-peakjitterofaclocksignal Two complete current loops A circuit with branch points Two segmented current loops A straight round wire

17 XX List of Figures 2.5 Self and mutual partial inductance of a straight segment of wire Loop magnetic flux in terms of partial fluxes The signal and return current paths Internal magnetic flux of a round conductor Proximityeffectintwocloselyspacedlines Current loop with two alternative current return paths A cross-sectional view of two parallel current paths sharing the same current return path A circuit model of two current paths with different inductive properties Impedance characteristics of two current paths with dissimilar impedance characteristics A RL ladder circuit A line length region where signal transmission exhibits inductive behavior The line inductance design space with significant inductive behavior A signal line in an integrated circuit environment Two representations of a straight line inductance A complete current loop formed by two straight parallel lines Inductance per length versus line length Inductance per length versus line length in terms of the per cent difference A current loop formed by two parallel lines Two loop segments connected in parallel Electromigration induced circuit faults Electromigration in an interconnect line Electromigration lifetime versus line width Grain structure of interconnect lines Log-normal distribution of electromigration failures A train of current pulses Via void formation in dual-damascene interconnect A cross-sectional view of a power distribution system. 88

18 List of Figures XXI 5.2 A one-dimensional circuit model of the power supply system A reduced circuit model of a power supply system An output impedance model of a power distribution system A power distribution system without decoupling capacitors Impedance of the power distribution system with no decouplingcapacitors A power distribution network with a decoupling capacitor Impedance of the power distribution system with a decouplingcapacitor The path of current flow in a power distribution systemwithadecouplingcapacitor A circuit model of a power distribution system with a boarddecouplingcapacitance Impedance of a power distribution system with a boarddecouplingcapacitance A circuit model of a power distribution system with boardandpackagedecouplingcapacitances Impedance of the power distribution system with boardandpackagedecouplingcapacitances A model of output impedance of a power distribution system with board, package, and on-chip decoupling capacitances Impedance of a power distribution system with board, package,andon-chipdecouplingcapacitances Variation of the power current loop with frequency A parallel resonant circuit Asymptotic impedance characteristics of a tank circuit Design space of resistance in a tank circuit Decoupling capacitance requirements Impedance characteristics of a fully compensated tank circuit Impedance of a fully compensated power distribution system Case study impedance characteristics Placement of area array connections for low inductance

19 XXII List of Figures 6.1 Leyden jar originally developed by Ewald Georg von Kleist in 1745 and independently invented by Pieter van Musschenbroek in Capacitance of two metal lines placed over a substrate Hydraulic model of a decoupling capacitor as a reservoirofcharge Practicalmodelofadecouplingcapacitor Physical structure of an on-chip MOS decoupling capacitor A circuit network representing the impedance of a power distribution system with decoupling capacitors as seen from the terminals of the current load A circuit network representing the impedance of a power distribution system without decoupling capacitors Impedance of a power distribution system without decouplingcapacitors Antiresonance of the output impedance of a power distribution network Impedance of a power distribution system with n identical decoupling capacitors connected in parallel Antiresonance of parallel capacitors, C 1 >C 2, L 1 = L 2,andR 1 = R Antiresonance of parallel capacitors Hydraulic analogy of the hierarchical placement of decouplingcapacitors Impedance of a power distribution system with board, package,andon-chipdecouplingcapacitances Intrinsic decoupling capacitance of the interconnect lines Intrinsic decoupling capacitance of a non-switching circuit N-well junction intrinsic decoupling capacitance Banksofon-chipdecouplingcapacitors ThinoxideMOSdecouplingcapacitor Equivalent RC model of a MOS decoupling capacitor Layout (a) and cross section (b) of a PIP oxide-nitride-oxide(ono)capacitor Thestructureofann-typeMOScapacitor

20 List of Figures XXIII 6.23 Capacitance versus gate voltage (CV) diagram of an n-typemoscapacitor Charge distribution in an NMOS capacitor operating in accumulation (V gb <V fb ) Accumulation charge density as a function of the applied gate voltage Charge distribution in an NMOS capacitor operating in depletion (V fb <V gb <V t ) Charge distribution of an NMOS capacitor operating in inversion (V t <V gb ) Layout (a) and cross section (b) of a deep-n + MOS capacitorconstructedinabicmosprocess CrosssectionofaMIMcapacitor A simplified structure of an interdigitated lateral flux capacitor (top view) Verticalfluxversuslateralflux Reduction of the bottom plate parasitic capacitance throughfluxstealing Wovencapacitor Switchingdecouplingcapacitors Routed power and ground distribution networks A mesh structured power distribution network A multi-layer power distribution grid On-chippowerandgroundplanes A power distribution network structured as a cascaded ring Narrowpowerlinesversuswidepowerlines Global power distribution network in Alpha microprocessor Closelyattachedcapacitor Flow of power current in an IC with peripheral I/O Flow of power current in an IC with flip-chip I/O Flip-chippingridarraypackage Interaction of the substrate and power distribution network Design flow for on-chip power distribution networks An RLC model of an on-chip power distribution network

21 XXIV List of Figures 8.3 Substitution of a nonlinear load with a time-dependent current source Characterization of the intrinsic decoupling capacitance Exploiting the symmetry of the power and ground distribution networks to reduce the model complexity Separation of the analysis of the RLC and RC-only parts of a power distribution system A hierarchical model of a power distribution network Flow chart for allocating on-chip decoupling capacitors Variation of ground supply voltage with time A simple power transmission circuit Two parallel coupled inductors Three types of power distribution grids Loop grid inductance versus number of lines Inductance of grids with 1 µm 1 µm cross section lines Inductance of grids with 1 µm 3 µm cross section lines Grid inductance versus grid length Threetypesofgridstructures A cross-sectional view of two parallel current paths sharing the same current return path A circuit model of two current paths with different inductive properties Impedance characteristics of two paths with dissimilar impedance characteristics Inductance of non-interdigitated grids versus frequency Loop inductance of paired grids versus frequency Loop inductance of interdigitated grids versus frequency Inductance versus resistance tradeoff scenario Grid inductance versus line width under a constant gridareaconstraint The sheet inductance L A versus line width under a constantgridareaconstraint

22 List of Figures XXV 11.4 Normalized sheet inductance and sheet resistance under a constant grid area constraint Inductance versus area tradeoff scenario The grid inductance versus line width under a constant gridresistanceconstraint The sheet inductance L R versus line width under a constantgridresistanceconstraint Normalized sheet inductance L R and grid area ratio A R under a constant grid resistance constraint An area array of on-chip power/ground I/O pads Decrease in flip-chip pad pitch with technology scaling A simplified circuit model of the on-chip power distribution network A model of the power distribution cell Scaling of a power distribution grid according to the constantmetalthicknessscenario Scaling of a power distribution grid according to the scaledmetalthicknessscenario Increase in power current demands of microprocessors withtechnologyscaling A power distribution grid model Scaling trends of resistive and inductive power supply noise under the constant metal thickness scenario Scaling trends of resistive and inductive power supply noise under the scaled metal thickness scenario A multi-layer power distribution grid Two stacks of layers comprising a multi-layer grid Impedance of the individual grid layers in a multi-layer grid Equivalent circuit of a stack of N gridlayers Variation of the inductance and resistance of a multi-layer stack with frequency General view of a two layer grid An equivalent circuit diagram of a two layer grid Alignment of two parallel grid layers with the same linepitch Inductance of a two layer grid versus the physical offset between the two layers

23 XXVI List of Figures Thecrosssectionofatwolayergrid Inductance of a two layer grid versus signal frequency Resistance of a two layer grid versus signal frequency Impedance magnitude of a two layer grid versus frequency An example single supply voltage circuit An example dual supply voltage circuit Static current as a result of a direct connection between the Vdd L gate and the V H dd gate Level converter circuit A dual power supply voltage circuit with the clustered voltagescaling(cvs)technique A dual power supply voltage circuit with the extended clustered voltage scaling (ECVS) technique Layout of an area-by-area architecture with a dual power supply voltage Layout of a row-by-row architecture with a dual power supply voltage In-row dual power supply voltage scheme Trend in power reduction with multi-voltage scheme as a function of the number of available supply voltages A lambda-shaped normalized path delay distribution function Dependence of the total power of a dual power supply system on a lower power supply voltage Vdd L A multi-layer on-chip power distribution grid Interdigitated power distribution grids under investigation Circuit diagram of the mutual inductive coupling of the DSDG power distribution grid Physical structure of an interdigitated power distribution grid with DSDG Physical structure of a fully interdigitated power distribution grid with DSDG Physical structure of a pseudo-interdigitated power distribution grid with DSDG

24 List of Figures XXVII 15.7 Total mutual inductance of interdigitated power distribution grids with DSDG as a function of line separation Physical structure of a fully paired power distribution gridwithdsdg Physical structure of a pseudo-paired power distribution grid with DSDG Total mutual inductance of paired power distribution grids with DSDG as a function of the ratio of the distance between the pairs to the line separation inside each pair (n) Maximum voltage drop for the four interdigitated power distribution grids under investigation Maximum voltage drop for the three paired power distribution grids under investigation Maximum voltage drop for interdigitated and paired power distribution grids under investigation Maximum voltage drop for seven types of power distribution grids with a decoupling capacitance Maximum voltage drop for the power distribution grid with SSSG as a function of frequency and line width for different values of decoupling capacitance Impedance of power distribution system with two supply voltages seen from the load of the power supply V dd Impedance of power distribution system with two supply voltages and the decoupling capacitors represented as series RLC networks Frequency dependence of the impedance of a power distribution system with dual supply voltages, R 1 = R 12 = R 2 =10mΩ,C 1 = C 12 = C 2 = 1 nf, and L 1 = L 12 = L 2 =1nH Antiresonance of the two capacitors connected in parallel, C 2 = C Antiresonance of a power distribution system with dual power supply voltages, R 1 = R 12 = R 2 =10mΩ, C 1 = C 2 = 1 nf, and L 1 = L 12 = L 2 =1nH Impedance of the power distribution system as a function of frequency

25 XXVIII List of Figures 16.7 Dependence of a dual V dd power distribution system impedance on frequency for different ESL of the decouplingcapacitors The impedance of a power distribution system with dual power supply voltages as a function of frequency, R 1 = R 12 = R 2 = 100 mω, C 1 = C 2 =10nF, C 12 = 1 nf, and L 1 = L 12 = L 2 =1nH Hierarchical model of a power distribution system with dual supply voltages and a single ground Voltage transfer function of a power distribution network with two supply voltages and the decoupling capacitors represented as series RLC networks Dependence of the magnitude of the voltage transfer function on frequency of a dual V dd power distribution system for different values of ESR of the decoupling capacitors, R 12 =10mΩ,C 12 = C 2 = 1 nf, and L 12 = L 2 =1nH Frequency dependence of the voltage transfer function of a dual V dd power distribution system for different values of ESL of the decoupling capacitors, R 12 = R 2 = 100 mω, C 12 = C 2 = 100 nf, and L 12 =10pH Frequency dependence of the voltage transfer function of a dual V dd power distribution system Dependence of the magnitude of the voltage transfer function of a dual V dd power distribution system on frequency for different values of the ESR and ESL of the decoupling capacitors, R 12 = R 2 =0.1Ω, C 12 =20nF,C 2 =40nF,andL 12 = L 2 =1nH Magnitude of the voltage transfer function of an example dual V dd power distribution system as a function of frequency An equivalent circuit for analyzing ground bounce in ansoc Groundbouncereductiontechnique Simplified circuit of the ground bounce reduction technique Ground bounce reduction as a function of noise frequency

26 List of Figures XXIX 17.5 Reduction in ground bounce as a function of capacitancevariations Placement of an on-chip decoupling capacitor based onthemaximumeffectivedistance Projection of the maximum effective radius as determined by the target impedance d max Z for future technology generations: I max = 10 ma, V dd = 1 V, and Ripple = Linear approximation of the current demand of a power distribution network by a current source Power distribution noise during discharge of an on-chip decoupling capacitor: I max = 100 ma, V dd =1V, t r =20ps,t f =80ps,R = 100 mω, L = 15 ph, and C dec =50pF Critical line length of an interconnect between a decoupling capacitor and a current load Dependence of the critical line length d crit on the rise time of the current load: I max =0.1A, V dd =1V, r =0.007 Ω/µm, and l =0.5pH/µm Design space for determining minimum required on-chip decoupling capacitance: I max = 50 ma, V dd =1V,r =0.007 Ω/µm, l =0.5pH/µm, t r = 100 ps, and t f =300ps Circuit charging an on-chip decoupling capacitor Design space for determining the maximum tolerable parasitic resistance and inductance of a power distribution grid: I max = 100 ma, t r = 100 ps, t f = 300 ps, C dec = 100 pf, V dd =1volt,and t ch =400ps Design flow for placing on-chip decoupling capacitors basedonthemaximumeffectiveradii The effective radii of an on-chip decoupling capacitor Model of a power distribution network Effective radii of an on-chip decoupling capacitor in a power distribution system modeled as a distributed RL mesh A schematic example allocation of on-chip decoupling capacitorsacrossanic

27 XXX List of Figures 19.1 Fundamental limits of on-chip interconnections Placement of on-chip decoupling capacitors using a conventionalapproach Aconventionalon-chipdecouplingcapacitor A network of distributed on-chip decoupling capacitors A physical model of a system of distributed on-chip decouplingcapacitors A circuit model of an on-chip distributed decoupling capacitornetwork Voltage across C 1 during discharge as a function of C 1 and R 2 : I max =0.01 ma, V dd =1volt,and t r =100ps The total budgeted on-chip decoupling capacitance as a function of the parasitic resistance of the metal lines, R 1 and R 2 : I max = 10 ma, V dd =1volt, V load =0.9 volt, and t r =100ps The total budgeted on-chip decoupling capacitance as a function of the parasitic resistance of the metal lines, R 1 and R 2 : I max = 10 ma, V dd =1volt, V load =0.9 volt, and t r =100ps Design flow for determining the parameters of a system of distributed on-chip decoupling capacitors Evolution of the impedance of a power distribution system in microprocessors Cross section of interconnect connecting the load and decouplingcapacitance The effect of circuit scaling on the on-chip capacitance allocation

28 List of Tables 5.1 Parameters of a case study power distribution system Four common types of on-chip decoupling capacitors in a90nmcmostechnology Inductive characteristics of power/ground grids Ideal scaling of CMOS circuits Scaling analyses of power distribution noise Impedance characteristics of power distribution grids with SSSG Impedance characteristics of interdigitated power distribution grids with DSSG Impedance characteristics of interdigitated power distribution grids with DSDG Impedance characteristics of Type I paired power distribution grids with DSDG Impedance characteristics of Type II paired power distribution grids with DSDG Case study of the impedance of a power distribution system Tradeoff between the magnitude and frequency range ofthevoltageresponse Ground bounce reduction as a function of the separation between the noisy and noise sensitive circuits

29 XXXII List of Tables 17.2 Ground bounce reduction for different values of parasitic resistance of the on-chip low noise ground Maximum effective radii of an on-chip decoupling capacitor for a single line connecting a decoupling capacitor to a current load Maximum effective radii of an on-chip decoupling capacitor for an on-chip power distribution grid modeled as a distributed RL mesh Dependence of the parameters of a distributed on-chip decoupling capacitor network on R Distributed on-chip decoupling capacitor network as a function of R 1 under the constraint of a minimum C The magnitude of the on-chip decoupling capacitors as a function of the parasitic resistance of the power/ground lines connecting the capacitors to the current load The magnitude of the on-chip decoupling capacitors as a function of the parasitic resistance of the power/ground lines connecting the capacitors to the current load for a limit on C