100 MHz to 4000 MHz RF/IF Digitally Controlled VGA ADL5243

Transcription

1 FEATURES Operating frequency from MHz to 4 MHz Digitally controlled VGA with serial and parallel interfaces 6-bit,. db digital step attenuator 3. db gain control range with ±.2 db step accuracy Gain Block Amplifier Gain: 9.2 db at 24 MHz OIP3: 4.2 dbm at 24 MHz PdB: 9.8 dbm at 24 MHz Noise figure: 2.9 db at 24 MHz ¼ W Driver Amplifier 2 Gain: 4.2 db at 24 MHz OIP3: 4. dbm at 24 MHz PdB: 26. dbm at 24 MHz Noise figure: 3.7 db at 24 MHz Gain block, DSA, or ¼ W driver amplifier can be first Low quiescent current of 7 ma The companion ADL24 integrates a gain block with DSA APPLICATIONS Wireless infrastructure Automated test equipment RF/IF gain control MHz to 4 MHz RF/IF Digitally Controlled VGA GENERAL DESCRIPTION The is a high performance, digitally controlled variable gain amplifier operating from MHz to 4 MHz. The VGA integrates two high performance amplifiers and a digital step attenuator (DSA). Amplifier (AMP) is an internally matched gain block amplifier with db gain, and Amplifier 2 (AMP2) is a broadband ¼ W driver amplifier that requires very few external tuning components. The DSA is 6-bit with a 3. db gain control range,. db steps, and ±.2 db step accuracy. The attenuation of the DSA can be controlled using a serial or parallel interface. The gain block and DSA are internally matched to Ω at their inputs and outputs, and all three internal devices are separately biased. The separate bias allows all or part of the to be used, which allows for easy reuse throughout a design. The pinout of the also enables the gain block, DSA, or ¼ W driver amplifier to be first, giving the VGA maximum flexibility in a signal chain. The consumes 7 ma and operates off a single supply ranging from 4.7 V to.2 V. The VGA is packaged in a thermally efficient, mm mm, 32-lead LFCSP and is fully specified for operation from 4 C to +8 C. A fully populated evaluation board is available. FUTIONAL BLOCK DIAGRAM AMP AMPIN AMP2/VCC2 VBIAS SEL D/CLK D/DATA D2/LE D3 D4 D D VDD SERIAL/PARALLEL INTERFACE 24 VDD DSAIN 4 2 DSA.dB db 2dB 4dB 8dB 6dB AMP/VCC AMP Figure. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 62-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 * PRODUCT PAGE QUICK LINKS Last Content Update: 2/23/7 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS Evaluation Board DOCUMENTATION : MHz to 4 MHz RF/IF Digitally Controlled VGA SOFTWARE AND SYSTEMS REQUIREMENTS ADL24 and Evaluation Board Software TOOLS AND SIMULATIONS ADIsimPLL ADIsimRF S-Parameters DESIGN RESOURCES Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. REFEREE MATERIALS Press Analog Devices Introduces High-Performance RF ICs for Multi-band Base Stations and Microwave Point-to-Point Radios Product Selection Guide RF Source Booklet This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Revision History... 2 Specifications... 3 Absolute Maximum Ratings... ESD Caution... Pin Configuration and Function Descriptions... Typical Performance Characteristics... 2 Applications Information Basic Layout Connections SPI Timing Amplifier 2 Matching... 2 Loop Performance... 3 Proper Driving Level for the Optimum ACLR Thermal Considerations Soldering Information and Recommended PCB Land Pattern Evaluation Board Outline Dimensions Ordering Guide REVISION HISTORY 8/2 Rev. A to Rev. B Changes to General Description Section... Changes to Table... 3 Changes to Table 3... Changes to Figure Changes to Figure Added Figure 47 and Figure 49, Renumbered Sequentially... 9 Change to Figure Changes to Amplifier 2 Matching Section, Table 8, and Table Added Figure 6 and Figure Changes to Figure 63 and Figure Added Figure 6; Changes to Figure Added Figure 67; Changes to Figure Added Figure Changes to Loop Performance Section; Added Figure 7, Figure 72, and Table, Renumbered Sequentially... 3 Added Proper Driving Level for the Optimum ACLR Section and Figure Changes to Evaluation Board Section and Table Changes to Figure Added Figure Changes to Figure 77 and Figure Added Figure / Rev. to Rev. A Changes to Features Section... 7/ Revision : Initial Version Rev. B Page 2 of 4

4 SPECIFICATIONS VDD = V, VCC = V, VCC2 = V, TA = 2 C. Table. Parameter Conditions Min Typ Max Unit OVERALL FUTION Frequency Range 4 MHz AMPLIFIER FREQUEY = MHz Using the AMPIN and AMP pins Gain 8.2 db vs. Frequency ± MHz ±.97 db vs. Temperature 4 C TA +8 C ±.7 db vs. Supply 4.7 V to.2 V ±.3 db Input Return Loss S.4 db Output Return Loss S db Output db Compression Point 8.4 dbm Output Third-Order Intercept f = MHz, P = 3 dbm/tone 29. dbm Noise Figure 2.8 db AMPLIFIER FREQUEY = 4 MHz Using the AMPIN and AMP pins Gain.6 db vs. Frequency ± MHz ±. db vs. Temperature 4 C TA +8 C ±.36 db vs. Supply 4.7 V to.2 V ±. db Input Return Loss S 7.8 db Output Return Loss S22 6. db Output db Compression Point 9. dbm Output Third-Order Intercept f = MHz, P = 3 dbm/tone 38.4 dbm Noise Figure 2.8 db AMPLIFIER FREQUEY = 748 MHz Using the AMPIN and AMP pins Gain.8 db vs. Frequency ± MHz ±.2 db vs. Temperature 4 C TA +8 C ±.32 db vs. Supply 4.7 V to.2 V ±. db Input Return Loss S 22. db Output Return Loss S db Output db Compression Point 9.6 dbm Output Third-Order Intercept f = MHz, P = 3 dbm/tone 39.6 dbm Noise Figure 2.7 db AMPLIFIER FREQUEY = 943 MHz Using the AMPIN and AMP pins Gain db vs. Frequency ±8 MHz ±. db vs. Temperature 4 C TA +8 C ±.28 db vs. Supply 4.7 V to.2 V ±.2 db Input Return Loss S 24. db Output Return Loss S22 2. db Output db Compression Point dbm Output Third-Order Intercept f = MHz, P = 3 dbm/tone 4.4 dbm Noise Figure 2.7 db Rev. B Page 3 of 4

5 Parameter Conditions Min Typ Max Unit AMPLIFIER FREQUEY = 96 MHz Using the AMPIN and AMP pins Gain 9. db vs. Frequency ±3 MHz ±.2 db vs. Temperature 4 C TA +8 C ±.26 db vs. Supply 4.7 V to.2 V ±.4 db Input Return Loss S 3. db Output Return Loss S db Output db Compression Point 9.6 dbm Output Third-Order Intercept f = MHz, P = 3 dbm/tone 4.4 dbm Noise Figure 2.9 db AMPLIFIER FREQUEY = 24 MHz Using the AMPIN and AMP pins Gain db vs. Frequency ±3 MHz ±.2 db vs. Temperature 4 C TA +8 C ±.26 db vs. Supply 4.7 V to.2 V ±. db Input Return Loss S 3.3 db Output Return Loss S db Output db Compression Point dbm Output Third-Order Intercept f = MHz, P = 3 dbm/tone 4.2 dbm Noise Figure 2.9 db AMPLIFIER FREQUEY = 263 MHz Using the AMPIN and AMP pins Gain db vs. Frequency ±6 MHz ±.3 db vs. Temperature 4 C TA +8 C ±.22 db vs. Supply 4.7 V to.2 V ±. db Input Return Loss S 7.3 db Output Return Loss S db Output db Compression Point dbm Output Third-Order Intercept f = MHz, P = 3 dbm/tone 39. dbm Noise Figure 2.9 db AMPLIFIER FREQUEY = 36 MHz Using the AMPIN and AMP pins Gain 8. db vs. Frequency ± MHz ±. db vs. Temperature 4 C TA +8 C ±. db vs. Supply 4.7 V to.2 V ±.2 db Input Return Loss S 3.7 db Output Return Loss S22 9. db Output db Compression Point 8. dbm Output Third-Order Intercept f = MHz, P = 3 dbm/tone 34.6 dbm Noise Figure 3.3 db AMPLIFIER 2 FREQUEY = MHz Using the and AMP2 pins Gain.8 db vs. Frequency ± MHz ±. db vs. Temperature 4 C TA +8 C ±.3 db vs. Supply 4.7 V to.2 V ±.3 db Input Return Loss S. db Output Return Loss S22 6. db Output db Compression Point 22.8 dbm Output Third-Order Intercept f = MHz, P = dbm/tone 4.6 dbm Noise Figure 6.3 db Rev. B Page 4 of 4

6 Parameter Conditions Min Typ Max Unit AMPLIFIER 2 FREQUEY = 4 MHz Using the and AMP2 pins Gain 6.4 db vs. Frequency ± MHz ±. db vs. Temperature 4 C TA +8 C ±.3 db vs. Supply 4.7 V to.2 V ±.7 db Input Return Loss S 9. db Output Return Loss S22 8. db Output db Compression Point 23.2 dbm Output Third-Order Intercept f = MHz, P = dbm/tone 38. dbm Noise Figure 6.2 db AMPLIFIER 2 FREQUEY = 748 MHz Using the and AMP2 pins Gain 7. db vs. Frequency ± MHz ±.4 db Input Return Loss S 4 db Output Return Loss S db Output db Compression Point 24.7 dbm Output Third-Order Intercept f = MHz, P = dbm/tone 4. dbm Noise Figure.6 db AMPLIFIER 2 FREQUEY = 943 MHz Using the and AMP2 pins Gain 6. db vs. Frequency ±8 MHz ±. db vs. Temperature 4 C TA +8 C ±.39 db vs. Supply 4.7 V to.2 V ±. db Input Return Loss S.2 db Output Return Loss S22 8. db Output db Compression Point 2. dbm Output Third-Order Intercept f = MHz, P = dbm/tone 43.3 dbm Noise Figure.3 db AMPLIFIER 2 FREQUEY = 96 MHz Using the and AMP2 pins Gain 4.9 db vs. Frequency ±3 MHz ±. db Input Return Loss S 4 db Output Return Loss S22 7. db Output db Compression Point 26. dbm Output Third-Order Intercept f = MHz, P = dbm/tone 39.9 dbm Noise Figure 3.73 db AMPLIFIER 2 FREQUEY = 24 MHz Using the and AMP2 pins Gain db vs. Frequency ±3 MHz ±.3 db vs. Temperature 4 C TA +8 C ±. db vs. Supply 4.7 V to.2 V ±.9 db Input Return Loss S.7 db Output Return Loss S22 8. db Output db Compression Point 26. dbm Output Third-Order Intercept f = MHz, P = dbm/tone 4. dbm Noise Figure 3.7 db Rev. B Page of 4

7 Parameter Conditions Min Typ Max Unit AMPLIFIER 2 FREQUEY = 263 MHz Using the and AMP2 pins Gain 3. db vs. Frequency ±6 MHz ±.3 db vs. Temperature 4 C TA +8 C ±.6 db vs. Supply 4.7 V to.2 V ±.9 db Input Return Loss S 9.4 db Output Return Loss S db Output db Compression Point 24. dbm Output Third-Order Intercept f = MHz, P = dbm/tone 4.4 dbm Noise Figure 4. db AMPLIFIER 2 FREQUEY = 36 MHz Using the and AMP2 pins Gain 2.3 db vs. Frequency ± MHz ±.23 db vs. Temperature 4 C TA +8 C ±. db vs. Supply 4.7 V to.2 V ±.7 db Input Return Loss S. db Output Return Loss S22. db Output db Compression Point 26.2 dbm Output Third-Order Intercept f = MHz, P = dbm/tone 36.2 dbm Noise Figure. db DSA FREQUEY = MHz Using the DSAIN and DSA pins, minimum attenuation Insertion Loss. db vs. Frequency ± MHz ±.2 db vs. Temperature 4 C TA +8 C ±. db Attenuation Range Between maximum and minimum attenuation states 28.8 db Attenuation Step Error All attenuation states ±.8 db Attenuation Absolute Error All attenuation states ±.3 db Input Return Loss 3. db Output Return Loss 3.3 db Input Third-Order Intercept f = MHz, P = dbm/tone 48.2 dbm DSA FREQUEY = 4 MHz Using the DSAIN and DSA pins, minimum attenuation Insertion Loss.4 db vs. Frequency ± MHz ±.2 db vs. Temperature 4 C TA +8 C ±.2 db Attenuation Range Between maximum and minimum attenuation states 3.7 db Attenuation Step Error All attenuation states ±.4 db Attenuation Absolute Error All attenuation states ±.39 db Input Return Loss 7.7 db Output Return Loss 7.4 db Input Third-Order Intercept f = MHz, P = dbm/tone 44. dbm DSA FREQUEY = 748 MHz Using the DSAIN and DSA pins, minimum attenuation Insertion Loss. db vs. Frequency ± MHz ±.2 db vs. Temperature 4 C TA +8 C ±.2 db Attenuation Range Between maximum and minimum attenuation states 3.9 db Attenuation Step Error All attenuation states ±. db Attenuation Absolute Error All attenuation states ±.3 db Input Return Loss 7. db Output Return Loss 7. db Input Third-Order Intercept f = MHz, P = dbm/tone 44. dbm Rev. B Page 6 of 4

8 Parameter Conditions Min Typ Max Unit DSA FREQUEY = 943 MHz Using the DSAIN and DSA pins, minimum attenuation Insertion Loss.6 db vs. Frequency ±8 MHz ±. db vs. Temperature 4 C TA +8 C ±.3 db Attenuation Range Between maximum and minimum attenuation states 3.9 db Attenuation Step Error All attenuation states ±. db Attenuation Absolute Error All attenuation states ±.28 db Input Return Loss 6. db Output Return Loss.9 db Input db Compression Point 3. dbm Input Third-Order Intercept f = MHz, P = dbm/tone.7 dbm DSA FREQUEY = 96 MHz Using the DSAIN and DSA pins, minimum attenuation Insertion Loss 2. db vs. Frequency ±3 MHz ±.4 db vs. Temperature 4 C TA +8 C ±.8 db Attenuation Range Between maximum and minimum attenuation states 3.8 db Attenuation Step Error All attenuation states ±. db Attenuation Absolute Error All attenuation states ±.3 db Input Return Loss.3 db Output Return Loss 9.6 db Input db Compression Point 3. dbm Input Third-Order Intercept f = MHz, P = dbm/tone 49.6 dbm DSA FREQUEY = 24 MHz Using the DSAIN and DSA pins, minimum attenuation Insertion Loss 2.6 db vs. Frequency ±3 MHz ±.2 db vs. Temperature 4 C TA +8 C ±.9 db Attenuation Range Between maximum and minimum attenuation states 3.9 db Attenuation Step Error All attenuation states ±.3 db Attenuation Absolute Error All attenuation states ±.32 db Input Return Loss 9.8 db Output Return Loss 9.3 db Input db Compression Point 3. dbm Input Third-Order Intercept f = MHz, P = dbm/tone 49.6 dbm DSA FREQUEY = 263 MHz Using the DSAIN and DSA pins, minimum attenuation Insertion Loss 2.8 db vs. Frequency ±6 MHz ±.2 db vs. Temperature 4 C TA +8 C ±.2 db Attenuation Range Between maximum and minimum attenuation states 3.2 db Attenuation Step Error All attenuation states ±.8 db Attenuation Absolute Error All attenuation states ±.24 db Input Return Loss. db Output Return Loss 9.6 db Input db Compression Point 3. dbm Input Third-Order Intercept f = MHz, P = dbm/tone 48.3 dbm Rev. B Page 7 of 4

9 Parameter Conditions Min Typ Max Unit DSA FREQUEY = 36 MHz Using the DSAIN and DSA pins, minimum attenuation Insertion Loss 3. db vs. Frequency ± MHz ±.2 db vs. Temperature 4 C TA +8 C ±.23 db Attenuation Range Between maximum and minimum attenuation states 3.7 db Attenuation Step Error All attenuation states ±.38 db Attenuation Absolute Error All attenuation states ±.3 db Input Return Loss 2.3 db Output Return Loss.7 db Input db Compression Point 3. dbm Input Third-Order Intercept f = MHz, P = dbm/tone 46.2 dbm DSA Gain Settling Using the DSAIN and DSA pins Minimum Attenuation to Maximum 36 ns Attenuation Maximum Attenuation to Minimum 36 ns Attenuation LOOP FREQUEY = MHz AMP DSA AMP2, DSA at minimum attenuation Gain 37.4 db vs. Frequency ± MHz ±. db Gain Range Between maximum and minimum attenuation states 28. db Input Return Loss S. db Output Return Loss S22 7. db Output db Compression Point 22. dbm Output Third-Order Intercept f = MHz, P = dbm/tone 38. dbm Noise Figure 3. db LOOP FREQUEY = 4 MHz AMP DSA AMP2, DSA at minimum attenuation Gain 3.8 db vs. Frequency ± MHz ±.43 db Gain Range Between maximum and minimum attenuation states 3. db Input Return Loss S 2. db Output Return Loss S db Output db Compression Point 23. dbm Output Third-Order Intercept f = MHz, P = dbm/tone 37.6 dbm Noise Figure 3. db LOOP FREQUEY = 943 MHz AMP DSA AMP2, DSA at minimum attenuation Gain 34. db vs. Frequency ±8 MHz ±. db Gain Range Between maximum and minimum attenuation states 29.3 db Input Return Loss S 4.2 db Output Return Loss S22. db Output db Compression Point 2. dbm Output Third-Order Intercept f = MHz, P = dbm/tone 42.8 dbm Noise Figure 2.9 db LOOP FREQUEY = 24 MHz AMP DSA AMP2, DSA at minimum attenuation Gain 3.3 db vs. Frequency ±3 MHz ±.3 db Gain Range Between maximum and minimum attenuation states 32. db Input Return Loss S 9.3 db Output Return Loss S22.4 db Output db Compression Point 2.3 dbm Output Third-Order Intercept f = MHz, P = dbm/tone 4. dbm Noise Figure 3. db Rev. B Page 8 of 4

10 Parameter Conditions Min Typ Max Unit LOOP FREQUEY = 263 MHz AMP DSA AMP2, DSA at minimum attenuation Gain 29. db vs. Frequency ±6 MHz ±.6 db Gain Range Between maximum and minimum attenuation states 3. db Input Return Loss S 2.6 db Output Return Loss S22.8 db Output db Compression Point 24.6 dbm Output Third-Order Intercept f = MHz, P = dbm/tone 39.3 dbm Noise Figure 3. db LOOP FREQUEY = 36 MHz AMP DSA AMP2, DSA at minimum attenuation Gain 26. db vs. Frequency ± MHz ±.3 db Gain Range Between maximum and minimum attenuation states 33. db Input Return Loss S 8. db Output Return Loss S22 8. db Output db Compression Point 24.7 dbm Output Third-Order Intercept f = MHz, P = dbm/tone 36. dbm Noise Figure 3.7 db LOGIC INPUTS CLK, DATA, LE, SEL, D~D6 Input High Voltage, VINH 2. V Input Low Voltage, VINL.8 V Input Current, IINH/IINL. µa Input Capacitance, CIN. pf POWER SUPPLIES Voltage V Supply Current AMP 89 ma AMP2 86 ma DSA. ma Rev. B Page 9 of 4

11 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage (VDD, VCC, VCC2) 6. V Input Power AMPIN 6 dbm ( Ω Impedance) dbm DSAIN 3 dbm Internal Power Dissipation. W θja (Exposed Paddle Soldered Down) 34.8 C/W θjc (Exposed Paddle) 6.2 C/W Maximum Junction Temperature C Lead Temperature (Soldering, 6 sec) 24 C Operating Temperature Range 4 C to +8 C Storage Temperature Range 6 C to + C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B Page of 4

12 AMPIN AMP2/VCC2 VBIAS PIN CONFIGURATION AND FUTION DESCRIPTIONS 32 SEL 28 D3 27 D4 26 D 3 D/CLK 3 D/DATA 29 D2/LE 2 D6 VDD 2 3 DSAIN 4 AMP/VCC PIN INDICATOR TOP VIEW (Not to Scale) 24 VDD DSA NOTES. = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description, 24 VDD Supply Voltage for DSA. Connect this pin to a V supply. 2, 3,, 7, 8, 9,, 2, 3, 4, No Connect. Do not connect to this pin. 7, 8,, 22, 23 4 DSAIN RF Input to DSA. 6 AMP/VCC RF Output from Amplifier /Supply Voltage for Amplifier. Bias to Gain Block Amplifier is provided through a choke to this pin when connected to VCC. AMPIN RF Input to Gain Block Amplifier. AMP2/VCC2 RF Output from Amplifier 2/Supply Voltage for Amplifier 2. Bias to Driver Amplifier 2 is provided through a choke to this pin when connected to VCC2. 6 VBIAS Bias for Driver Amplifier 2. 9 RF Input to Amplifier 2. 2 DSA RF Output from DSA. 2 D6 Data Bit in Parallel Mode (LSB). Connect to supply in serial mode. 26 D Data Bit in Parallel Mode. Connect to ground in serial mode. 27 D4 Data Bit in Parallel Mode. Connect to ground in serial mode. 28 D3 Data Bit in Parallel Mode. Connect to ground in serial mode. 29 D2/LE Data Bit in Parallel Mode/Latch Enable in Serial Mode. 3 D/DATA Data Bit in Parallel Mode (MSB)/Data in Serial Mode. 3 D/CLK Connect this pin to ground in parallel mode. This pin functions as a clock in serial mode. 32 SEL Select Pin. For parallel mode operation, connect this pin to the supply. For serial mode operation, connect this pin to ground. EPAD Exposed Paddle. The exposed paddle must be connected to ground. Rev. B Page of 4

13 TYPICAL PERFORMAE CHARACTERISTICS NOISE FIGURE, GAIN, PdB, OIP3 (db, dbm) GAIN PdB OIP3 NOISE FIGURE FREQUEY (GHz) Figure 3. AMP: Gain, PdB, OIP3 at P = 3 dbm/tone and Noise Figure vs. Frequency PdB (dbm) C +2 C 4 C FREQUEY (GHz) Figure 6. AMP: OIP3 at P = 3 dbm/tone and PdB vs. Frequency and Temperature OIP3 (dbm) MHz 4MHz GAIN (db) C 4 C +8 C OIP3 (dbm) MHz 36MHz MHz 24MHz 263MHz 748MHz FREQUEY (GHz) P PER TONE (dbm) Figure 4. AMP: Gain vs. Frequency and Temperature Figure 7. AMP: OIP3 vs. P and Frequency. S22 4. S-PARAMETERS (db) S2 S NOISE FIGURE (db) C +2 C 4 C FREQUEY (GHz) Figure. AMP: Input Return Loss (S), Output Return Loss (S22), and Reverse Isolation (S2) vs. Frequency FREQUEY (GHz) Figure 8. AMP: Noise Figure vs. Frequency and Temperature Rev. B Page 2 of 4

14 NOISE FIGURE, GAIN, PdB, OIP3 (db, dbm) OIP3 PdB GAIN FREQUEY (GHz) Figure 9. AMP2 943 MHz: Gain, PdB, OIP3 at P = dbm/tone and Noise Figure vs. Frequency 8. NF PdB (dbm) C +2 C 4 C FREQUEY (GHz) Figure 2. AMP2 943 MHz: OIP3 at P = dbm/tone and PdB vs. Frequency and Temperature OIP3 (dbm) MHz GAIN (db) C +2 C +8 C OIP3 (dbm) MHz 943MHz FREQUEY (GHz) Figure. AMP2 943 MHz: Gain vs. Frequency and Temperature P PER TONE (dbm) 7. Figure 3. AMP2 943 MHz: OIP3 vs. P and Frequency S-PARAMETERS (db) 2 S22 S S2 NOISE FIGURE (db) C +2 C 4 C FREQUEY (GHz) Figure. AMP2 943 MHz: Input Return Loss (S), Output Return Loss (S22), and Reverse Isolation (S2) vs. Frequency FREQUEY (GHz) Figure 4. AMP2 943 MHz: Noise Figure vs. Frequency and Temperature Rev. B Page 3 of 4

15 NOISE FIGURE, GAIN, PdB, OIP3 (db, dbm) OIP3 PdB GAIN NF FREQUEY (GHz) Figure. AMP2 24 MHz: Gain, PdB, OIP3 at P = dbm/tone and Noise Figure vs. Frequency 943- PdB (dbm) C +2 C 4 C FREQUEY (GHz) Figure 8. AMP2 24 MHz: OIP3 at P = dbm/tone and PdB vs. Frequency and Temperature OIP3 (dbm) GHz 2.7GHz GAIN (db) C +2 C +8 C OIP3 (dbm) GHz FREQUEY (GHz) Figure 6. AMP2 24 MHz: Gain vs. Frequency and Temperature P PER TONE (dbm). Figure 9. AMP2 24 MHz: OIP3 vs. P and Frequency S-PARAMETERS (db) S S22 S2 NOISE FIGURE (db) C +2 C 4 C FREQUEY (GHz) Figure 7. AMP2 24 MHz: Input Return Loss (S), Output Return Loss (S22), and Reverse Isolation (S2) vs. Frequency FREQUEY (GHz) Figure. AMP2 24 MHz: Noise Figure vs. Frequency and Temperature 943- Rev. B Page 4 of 4

16 NOISE FIGURE, GAIN, PdB, OIP3 (db, dbm) OIP3 PdB GAIN NF FREQUEY (GHz) Figure 2. AMP2 263 MHz: Gain, PdB, OIP3 at P = dbm/tone and Noise Figure vs. Frequency PdB (dbm) C C C FREQUEY (GHz) Figure 24. AMP2 263 MHz: OIP3 at P = dbm/tone and PdB vs. Frequency and Temperature OIP3 (dbm) GAIN (db) C C C FREQUEY (GHz) Figure 22. AMP2 263 MHz: Gain vs. Frequency and Temperature OIP3 (dbm) GHz 2.63GHz GHz P PER TONE (dbm) 6. Figure 2. AMP2 263 MHz: OIP3 vs. P and Frequency S-PARAMETERS (db) S S22 S2 NOISE FIGURE (db) C +2 C 4 C FREQUEY (GHz) Figure 23. AMP2 263 MHz: Input Return Loss (S), Output Return Loss (S22), and Reverse Isolation (S2) vs. Frequency FREQUEY (GHz) Figure 26. AMP2 263 MHz: Noise Figure vs. Frequency and Temperature Rev. B Page of 4

17 ATTENUATION (db) 2 3 db ABSOLUTE ERROR (db) MHz 748MHz 943MHz 96MHz 24MHz 263MHz 36MHz 3 3.dB FREQUEY (GHz) ATTENUATION (db) Figure 27. DSA: Attenuation vs. Frequency Figure 3. DSA: Absolute Error vs. Attenuation db ATTENUATION (db) dB 6dB 4dB +8 C +2 C 4 C INPUT RETURN LOSS (db) db 3.dB dB FREQUEY (GHz) FREQUEY (GHz) Figure 28. DSA: Attenuation vs. Frequency and Temperature Figure 3. DSA: Input Return Loss vs. Frequency, All States STEP ERROR (db) MHz 748MHz 943MHz 96MHz 24MHz 263MHz 36MHz PUT RETURN LOSS (db) 2 db 3.dB ATTENUATION (db) FREQUEY (GHz) Figure 29. DSA: Step Error vs. Attenuation Figure 32. DSA: Output Return Loss vs. Frequency, All States Rev. B Page 6 of 4

18 36 96MHz 3 IIP3 24MHz IPdB (dbm) IPdB IIP3 (dbm) PHASE (Degrees) 263MHz MHz FREQUEY (GHz) Figure 33. DSA: Input PdB and Input IP3 vs. Frequency, Minimum Attenuation State ATTENUATION (db) Figure 36. DSA: Phase vs. Attenuation NOISE FIGURE, GAIN, PdB, OIP3 (db, dbm) OIP3 GAIN PdB NF CH3 2.V CH4 mv Mns GS/s IT.ps/pt A CH3.24V Figure 34. DSA: Gain Settling Time, db to 3. db FREQUEY (MHz) Figure 37. Loop 943 MHz: Gain, PdB, OIP3 at P = dbm/tone and Noise Figure vs. Frequency, Minimum Attenuation State S S-PARAMETERS (db) S S2 8 CH3 2.V CH4 mv Mns GS/s IT.ps/pt A CH3.24V Figure 3. DSA: Gain Settling Time, 3. db to db FREQUEY (GHz) Figure 38. Loop 943 MHz: Input Return Loss (S), Output Return Loss (S22), and Reverse Isolation (S2) vs. Frequency, Minimum Attenuation State Rev. B Page 7 of 4

19 MHz GHz 2.GHz OIP3 (dbm) MHz 943MHz OIP3 (dbm) GHz P PER TONE (dbm) Figure 39. Loop 943 MHz: OIP3 vs. P and Frequency, Minimum Attenuation State P PER TONE (dbm) Figure 42. Loop 24 MHz: OIP3 vs. P and Frequency, Minimum Attenuation State NOISE FIGURE, GAIN, PdB, OIP3 (db, dbm) OIP3 GAIN PdB NF NOISE FIGURE, GAIN, PdB, OIP3 (db, dbm) OIP3 GAIN PdB NF FREQUEY (GHz) Figure 4. Loop 24 MHz: Gain, PdB, OIP3 at P = dbm/tone and Noise Figure vs. Frequency, Minimum Attenuation State FREQUEY (GHz) Figure 43. Loop 263 MHz: Gain, PdB, OIP3 at P = dbm/tone and Noise Figure vs. Frequency, Minimum Attenuation State S22 S22 S-PARAMETERS (db) S S2 S-PARAMETERS (db) S S FREQUEY (GHz) Figure 4. Loop 24 MHz: Input Return Loss (S), Output Return Loss (S22), and Reverse Isolation (S2) vs. Frequency, Minimum Attenuation State FREQUEY (GHz) Figure 44. Loop 263 MHz: Input Return Loss (S), Output Return Loss (S22), and Reverse Isolation (S2) vs. Frequency, Minimum Attenuation State Rev. B Page 8 of 4

20 GHz OIP3 (dbm) GHz 2.7GHz SUPPLY CURRENT (ma) V.V 4.7V P PER TONE (dbm) TEMPERATURE ( C) SUPPLY CURRENT (ma) Figure 4. Loop 263 MHz: OIP3 vs. P and Frequency, Minimum Attenuation State TEMPERATURE ( C).2V.V 4.7V Figure 46. AMP: Supply Current vs. Voltage and Temperature SUPPLY CURRENT (ma) Figure 48. AMP2: Supply Current vs. Voltage and Temperature C 9 +8 C C P PER TONE (dbm) Figure 49. AMP2: Supply Current vs. P and Temperature SUPPLY CURRENT (ma) C +2 C +8 C P PER TONE (dbm) Figure 47. AMP: Supply Current vs. P and Temperature Rev. B Page 9 of 4

21 PERCENTAGE (%) 3 2 PERCENTAGE (%) GAIN (db) Figure. AMP: Gain Distribution at 24 MHz NOISE FIGURE (db) Figure 3. AMP: Noise Figure Distribution at 24 MHz PERCENTAGE (%) PERCENTAGE (%) PdB (dbm) GAIN (db) Figure. AMP: PdB Distribution at 24 MHz Figure 4. AMP2: Gain Distribution at 24 MHz PERCENTAGE (%) 2 PERCENTAGE (%) OIP3 (dbm) Figure 2. AMP: OIP3 Distribution at 24 MHz PdB (dbm) Figure. AMP2: PdB Distribution at 24 MHz Rev. B Page of 4

22 7 6 6 PERCENTAGE (%) 4 3 PERCENTAGE (%) OIP3 (dbm) Figure 6. AMP2: OIP3 Distribution at 24 MHz NOISE FIGURE (db) Figure 7. AMP2: Noise Figure Distribution at 24 MHz 943- Rev. B Page 2 of 4

23 APPLICATIONS INFORMATION BASIC LAY CONNECTIONS The basic connections for operating the are shown in Figure 8. The schematic of AMP2 is configured for 24 MHz operation. VDD SERIAL PARALLEL INTERFACE VDD.µF C DSAIN AMP C pf C4.µF L 47nH C 68pF VDD DSAIN AMP/VCC SEL AMPIN D/CLK D/DATA D2/LE D3 D4 AMP2/VCC2 D VBIAS D6 VDD DSA C pf C27 2.2pF C28.8pF DSA C8 pf C4.2nF VCC2 C3 µf VCC AMPIN C2.µF L2 9.nH C22 pf C3 pf C2 nf C µf C23 pf AMP2 Figure 8. Basic Connections Rev. B Page 22 of 4

24 Amplifier Power Supply AMP in the is a broadband gain block. The dc bias is supplied through Inductor L and is connected to the AMP pin. Three decoupling capacitors (C3, C4, and C2) are used to prevent RF signals from propagating on the dc lines. The dc supply ranges from 4.7 V to.2 V and should be connected to the VCC test pin. Amplifier RF Input Interface Pin is the RF input for AMP of the. The amplifier is internally matched to Ω at the input; therefore, no external components are required. Only a dc blocking capacitor (C2) is required. Amplifier RF Output Interface Pin 6 is the RF output for AMP of the. The amplifier is internally matched to Ω at the output as well; therefore, no external components are required. Only a dc blocking capacitor (C4) is required. The bias is provided through this pin via a choke inductor, L. Amplifier 2 Power Supply The collector bias for AMP2 is supplied through Inductor L2 and is connected to the AMP2 pin, whereas the base bias is provided through Pin 6. The base bias is connected to the same supply pin as the collector bias. Three decoupling capacitors (C3, C, and C2) are used to prevent RF signals from propagating on the dc lines. The dc supply ranges from 4.7 V to.2 V and should be connected to the VCC2 test pin. Amplifier 2 RF Input Interface Pin 9 is the RF input for AMP2 of the. The input of the amplifier is easily matched to Ω with a combination of series and shunt capacitors and a microstrip line serving as an inductor. Figure 8 shows the input matching components and is configured for 24 MHz. Amplifier 2 RF Output Interface Pin is the RF input for AMP2 of the. The output of the amplifier is easily matched to Ω with a combination of series and shunt capacitors and a microstrip line serving as an inductor. Additionally, bias is provided through this pin. Figure 8 shows the output matching components and is configured for 24 MHz. DSA RF Input Interface Pin 4 is the RF input for the DSA of the. The input impedance of the DSA is close to Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C) is required. DSA RF Output Interface Pin 2 is the RF output for the DSA of the. The output impedance of the DSA is close to Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C) is required. DSA SPI Interface The DSA of the can operate in either serial or parallel mode. Pin 32 (SEL) controls the mode of operation. For serial mode operation, connect SEL to ground, and for parallel mode operation, connect SEL to VDD. In parallel mode, Pin 2 to Pin 3 (D6 to D) are the data bits, with D6 being the LSB. Connect Pin 3 (D) to ground during parallel mode of operation. In serial mode, Pin 29 is the latch enable (LE), Pin 3 is the data (DATA), and Pin 3 is the clock (CLK). Pin 26, Pin 27, and Pin 28 are not used in the serial mode and should be connected to ground. Pin 2 (D6) should be connected to VDD during the serial mode of operation. To prevent noise from coupling onto the digital signals, an RC filter can be used on each data line. SPI TIMING SPI Timing Sequence Figure 6 shows the timing sequence for the SPI function using a 6-bit operation. The clock can be as fast as MHz. In serial mode operation, Register B (MSB) is first, and Register B (LSB) is last. Table 4. Mode Selection Table Pin 32 (SEL) Functionality Connect to Ground Serial mode Connect to Supply Parallel mode Table. SPI Timing Specifications Parameter Limit Unit Test Conditions/Comments FCLK MHz Data clock frequency t 3 ns min Clock high time t2 3 ns min Clock low time t3 ns min Data to clock setup time t4 ns min Clock to data hold time t ns min Clock low to LE setup time t6 3 ns min LE pulse width Rev. B Page 23 of 4

25 t t CLK t 2 t 3 t 4 DATA MSB B B4 B3 B2 B LSB B t 6 LE Figure 9. SPI Timing Diagram (Data Loaded MSB First) D/CLK D/DATA MSB B B4 B3 B2 B LSB B D2/LE D Figure 6. SPI Timing Sequence Table 6. DSA Attenuation Truth Table Serial Mode Attenuation State B (MSB) B4 B3 B2 B B (LSB) db (Reference). db. db 2. db 4. db 8. db 6. db 3. db Table 7. DSA Attenuation Truth Table Parallel Mode Attenuation State D (MSB) D2 D3 D4 D D6 (LSB) db (Reference). db. db 2. db 4. db 8. db 6. db 3. db Rev. B Page 24 of 4

26 AMPLIFIER 2 MATCHING The AMP2 input and output of the can be matched to Ω with two or three external components and the microstrip line used as an inductor. Table 8 lists the required matching components values. All capacitors are Murata GRM series (42 size), and Inductor L2 is a Coilcraft 63CS series (63 size). For all frequency bands, the placement of Capacitors C22, C26, and C28 is critical. the spacing is 3 mils and 2 mils respectively. The component spacing is referenced from the center of the component to the edge of the package. Figure 6 to Figure 69 show the graphical representation of the matching network. It is recommended to configure a RC feedback network and bias the AMP2 input through external R for optimal performance at frequency bands less than MHz as shown at Figure 6 and Figure 62. In this case, VBIAS pin must be left open. Table 9 lists the recommended component spacing of C22, C26, and C28 for the various frequencies. The placement of R2 and C27 is fixed for the matching network on evaluation board and Table 8. Component Values on Evaluation Board Frequency C27 C26 C28 C8 C22 C23 L2 R R R2 R6 R C R3 R3 MHz 2.7n H. pf N/A pf. pf 47 pf 39 nh 2 Ω N/A 22 nh 3.6 kω 7 Ω nf Ω N/A 4 MHz Ω N/A.pF pf. pf pf nh 2 Ω.6 Ω 3.9 nh 3.6 kω 7 Ω nf Ω N/A 748 MHz Ω N/A. pf 2 pf.3 pf 8 pf 6 nh 8 Ω.6 Ω 3.9 nh N/A N/A N/A N/A Ω 943 MHz Ω 3.9 pf N/A 6 pf.3 pf pf 6 nh 8 Ω N/A 3.3 nh N/A N/A N/A N/A Ω 96 MHz 2.7 pf N/A. pf pf. pf pf 9. nh Ω N/A Ω N/A N/A N/A N/A Ω 24 MHz 2.2 pf N/A.8 pf pf. pf pf 9. nh Ω N/A Ω N/A N/A N/A N/A Ω 23 MHz 3.3 pf.6 pf. KΩ pf. pf pf 9. nh Ω N/A Ω N/A N/A N/A N/A Ω 263 MHz 2.7 pf. pf. KΩ pf.3 pf pf 9. nh Ω N/A Ω N/A N/A N/A N/A Ω 36 MHz. pf. KΩ.2 pf pf.2 pf pf 9. nh Ω N/A. nh N/A N/A N/A N/A Ω R is not reserved on the evaluation board. Table 9. Component Spacing on Evaluation Board Frequency C26 : λ(mils) C28 : λ2(mils) C22 : λ3(mils) MHz 23 N/A 48 4 MHz N/A MHz N/A MHz 236 N/A MHz N/A MHz N/A MHz MHz MHz Rev. B Page 2 of 4

27 AMP2//VCC VBIAS λ C27 2.7nH R3 R 7 C26.pF R6 3.6kΩ R 2Ω C8 pf λ3 R2 22nH L2 39nH C nf VCC C23 47pF C22.pF AMP2 Figure 6. AMP2: Matching Circuit at MHz AMP2//VCC VBIAS R3 R 7 λ2 C27 R6 3.6kΩ C28.pF R.6Ω R 2Ω C8 pf C nf λ3 L2 nh R2 3.9nH VCC C23 pf C22.pF AMP Figure 62. AMP2: Matching Circuit at 4 MHz Rev. B Page 26 of 4

28 λ2 AMP2/VCC2 VBIAS C27 C28.pF R.6Ω R 8Ω C8 2pF λ3 L2 6nH R2 3.9nH C22.3pF C23 8pF AMP2 Figure 63. AMP2: Matching Circuit at 748 MHz AMP2//VCC2 VBIAS C27 λ C26 3.9pF R 8Ω C8 6pF λ3 L2 6nH R2 3.3nH C22.3pF C23 pf AMP2 Figure 64. AMP2: Matching Circuit at 943 MHz Rev. B Page 27 of 4

29 AMP2//VCC2 VBIAS C27 2.7pF λ2 C28.pF R C8 pf λ3 R2 L2 9.nH C22.pF C23 pf AMP2 Figure 6. AMP2: Matching Circuit at 96 MHz AMP2/VCC2 VBIAS C27 2.2pF λ2 C28.8pF R C8 pf λ3 L2 9.nH R2 C22 pf C23 pf AMP2 Figure 66. AMP2: Matching Circuit at 24 MHz Rev. B Page 28 of 4

30 AMP2//VCC2 VBIAS λ C27 3.3pF λ2 C26.6pF C28.kΩ R C8 pf λ3 L2 9.nH R2 C22.pF C23 pf AMP2 Figure 67. AMP2: Matching Circuit at 23 MHz AMP2//VCC2 VBIAS λ C27 2.7pF λ2 C26.pF C28.kΩ R C8 pf λ3 L2 9.nH R2 C22.3pF C23 pf AMP2 Figure 68. AMP2: Matching Circuit at 263 MHz Rev. B Page 29 of 4

31 AMP2//VCC2 VBIAS λ C27.pF λ2 C26.kΩ C28.2pF R C8 pf λ3 L2 9.nH R2 R2 nh C23 pf C22.2pF AMP2 Figure 69. AMP2: Matching Circuit at 36 MHz Rev. B Page 3 of 4

32 LOOP PERFORMAE λ4 The typical configuration of the is to connect in AMP-DSA-AMP2 mode, as shown in Figure 7. Because AMP and DSA are broadband in nature and internally matched, only an ac coupling capacitor is required between them. The AMP2 is externally matched for each frequency band of operation, and these matching elements should be placed between the DSA and AMP2 and at the output of AMP2. Matching circuits for AMP2 are shown in Figure 6 through Figure 69. This works well in a loop in each case but matching circuits between the DSA and AMP2 requires slight retuning, such as adding a shunt capacitor at the DSA output or changing the location of a shunt capacitor for optimum performance in a loop at certain frequency bands. Figure 7 and Figure 72 show the retuned matching circuits from Figure 66 and Figure 69 at 24 MHz and 36 MHz, respectively. Figure 37 to Figure 4 show the performance of the when connected in a loop for the three primary frequency bands of operation, namely 943 MHz, 24 MHz, and 263 MHz λ3 AMP2/VCC2 VBIAS L2 9.nH R2 DSA C27 2.2pF λ2 C.3pF C28.8pF R33 C6 pf Table. Component Spacing in a Loop on Evaluation Board Frequency C26: λ (mils) C28: λ2 (mils) C22: λ3 (mils) C: λ4 (mils) 24 MHz N/A MHz N/A VCC VDD/SPI VCC2 C23 pf C22 pf AMP2 Figure 7. Matching Circuit at 24 MHz in a Loop DSA 2 RFIN AMP DSA IMN AMP2 OMN RF Figure 7. Loop Block Diagram AMP2/VCC2 VBIAS λ C27.pF λ2 C26.2pF C28.kΩ R33 C6 pf λ3 L2 9.nH C22 pf R2.2nH C23 pf AMP2 Figure 72. Matching Circuit at 36 MHz in a Loop Rev. B Page 3 of 4

33 PROPER DRIVING LEVEL FOR THE OPTIMUM ACLR It is usually required to drive the amplifier as high as possible in order to maximize output power. However, properly driving AMP and AMP2 at the is required to achieve optimum ACLR performance. Once output power approaches PdB and OIP3, there is ACLR degradation. The driving level of amplifier with a modulated signal should be backed off properly from PdB by at least the amount of a signal crest factor for optimum ACLR. So assuming a gain and PdB of AMP at 24 MHz are 9 db and 9 dbm respectively, the output power, which is backed off by db crest factor at the modulated signal case, is 8 dbm. Therefore, the proper input driving level should be under dbm. ACLR (dbc) AMP, ADJ AMP, ALT AMP2, ADJ AMP2, ALT P IN (dbm) Figure 73. Single Carrier WCDMA Adjacent Chanel Power Ratio vs. Input Power at AMP and AMP2, 24 MHz THERMAL CONSIDERATIONS The is packaged in a thermally efficient, mm mm, 32-lead LFCSP. The thermal resistance from junction to air (θja) is 34.8 C/W. The thermal resistance for the product was extracted assuming a standard 4-layer JEDEC board with 2 copper platter thermal vias. The thermal vias are filled with conductive copper paste, AE33, with a thermal conductivity of 7.8 W/mk and thermal expansion as follows: α of 4 / C and α2 of 8.6 / C. The thermal resistance from junction to case (θjc) is 6.2 C/W, where case is the exposed pad of the lead frame package For the best thermal performance, it is recommended to add as many thermal vias as possible under the exposed pad of the LFCSP. The above thermal resistance numbers assume a minimum of 2 thermal vias arranged in a array with a via diameter of 3 mils, via pad of 2 mils, and pitch of 2 mils. The vias are plated with copper, and the drill hole is filled with a conductive copper paste. For optimal performance, it is recommended to fill the thermal vias with a conductive paste of equivalent thermal conductivity, as mentioned above, or use an external heat sink to dissipate the heat quickly without affecting the die junction temperature. It is also recommended to extend the ground pattern as shown in Figure 74 to improve thermal efficiency. SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN Figure 74 shows the recommended land pattern for the. To minimize thermal impedance, the exposed paddle on the mm mm LFCSP package is soldered down to a ground plane. To improve thermal dissipation, 2 thermal vias are arranged in a array under the exposed paddle. If multiple ground layers exist, they should be tied together using vias. For more information on land pattern design and layout, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). DSAIN 2 MIL VIA PAD WITH 3 MIL VIA 8 Figure 74. Recommended Land Pattern 24 DSA Rev. B Page 32 of 4

34 EVALUATION BOARD The schematic of the evaluation board is shown in Figure 7. All RF traces on the evaluation board have a characteristic impedance of Ω and are fabricated from Rogers33 material. The traces are CPWG with a width of 2 mils, spacing of mils, and dielectric thickness of mils. The input and output to the DSA and amplifier should be ac-coupled with capacitors of an appropriate value to ensure broadband performance. The bias to AMP is provided through a choke connected to the AMP pin and, similarly, bias to AMP2 is provided through a choke connected to the AMP2 pin. Bypassing capacitors are recommended on all supply lines to minimize RF coupling. The DSA and the amplifiers can be individually biased or connected to the VDD plane through Resistors R, R2, and R. The schematic of AMP2 on evaluation board is configured for 24 MHz operation. When configuring the evaluation board in the AMP-DSA-AMP2 loop, remove Capacitors C, C4, C, and C8 and remove Resistor R. Place pf in place of C24 and C6, and Ω in place of R32 and R33. If needed, placing a shunt capacitor (.3 pf) at the output of the DSA improves the output return loss of this loop as described at the Loop Performance section. On the digital signal traces, provisions for an RC filter are made to clean any potential coupled noise. In normal operation, series resistors are Ω and shunt resistors and capacitors are open. The evaluation board is designed to control DSA in either parallel or serial mode by connecting the SEL pin to the supply or ground by a switch. For adjusting attenuation at DSA, the can be programmed in two ways: through the on-board USB interface from a PC USB port, or through an SDP board, which will become the Analog Devices common control board in the future. The on-board USB interface circuitry of the evaluation board is powered directly by the PC. USB based programming software is available to download from the product page at Figure 7 shows the window of the programming software where the user selects serial or parallel mode for the attenuation adjustment at DSA. The selection of the mode in the window should match the mode of the evaluation board switch. It is highly recommended to refer the evaluation board layout for the optimal and stable performance of each block as well as for the improvement of thermal efficiency. Table. Evaluation Board Configurations Options Component Function Default Value C, C AC coupling caps for DSA. C, C = pf C4, C2 AC coupling capacitors for AMP. C4, C2 = pf C3, C4, C Power supply bypassing capacitors for AMP. Capacitor C should be closest to the device. C3 = μf C4 = nf C = pf L The bias for AMP comes through L when connected to a V supply. L should be high L = 33 nh impedance for the frequency of operation, while providing low resistance for the dc current. C8 AMP2 input ac coupling capacitor. C8 = pf C23 AMP2 output ac coupling capacitor. C23 = pf C22 AMP2 shunt output tuning capacitor. C22 =. pf at 244 mils from edge of package C26 ANP2 shunt input tuning capacitor. DNP C27 AMP2 series input tuning capacitor. C27 = 2.2 pf C28 AMP2 shunt input tuning capacitor. C28 =.8 pf at 366 mils from edge of package C3, C2, C Power supply bypassing capacitors for AMP2. Capacitor C3 should be closest to the device. C3 = pf C2 = nf C = μf L2 The bias for AMP2 comes through L2 when connected to a V supply. L2 should be high L2 = 9. nh impedance for the frequency of operation, while providing low resistance for the dc current. C7 Power supply bypassing capacitor for DSA. C7 =. μf R, R2 Placeholder for the series component for the other frequency band. R, R2 = Ω C6, C24, R32, R33 Replace with capacitors and resistors to connect the device in a loop. C6, C24, R32, R33 = open R, R2, R Resistors to connect the supply for the amplifier and the DSA to the same VDD plane. R, R2 = open S Switch to change between serial and parallel mode operation; connect to a supply for parallel mode and to ground for serial mode operation. 3-pin rocker Rev. B Page 33 of 4

35 DSAIN C 4 AMP C4 4 R VCC RED C3 µf S 3 2 AGND VDD R2 C7.µF R32 C24 L 33nH C4.µF C pf D6 VDD RED U C.µF R3 L2 R2 9.nH C22 pf C23 pf R3 R 7 R6 3.6kΩ C DSA C27 2.2pF C.3pF pf PAD AGND AGND VDD AGND 2 pf pf AGND AMPIN C2 pf 3 4 AGND pf AGND CLK_D DATA_D LE_D2 D3 D4 D AGND ACPZ AGND AGND AGND AGND C26.pF C6 pf R33 C28.8pF R C8 pf AGND AGND VCC2 RED R VDD C3 C2 C pf pf µf AGND AMP AGND EPAD SEL D/CLK D/DATA D2/LE D3 D4 D D6 VDD DSA AMPIN AMP2/VCC2 VBIAS VDD DSAIN AMP/VCC AGND R AGND Figure 7. Evaluation Board Rev. B Page 34 of 4

36 Rev. B Page 3 of 4 DECOUPLING FOR U PLACEHOLDER R29 C9 R28 C8 R27 C6 C2 R26 R2 R23 R R9 R46 A C CR2 R8 R R24 R4 R3 C3 R3 C R4 C P PAD U4 C3 C36 C38 C39 C4 C46 C48 R4 A C D R4 C37 6 PAD U3 R3 C44 R9 C U2 R C49 C34 R47 R7 C3 C G4 G3 G2 G P C Y C2 C33 C9 33pF.kΩ JEDEC_TYPE=QFN6_8X8_PAD_2X4_ 33pF 33pF 33pF 33pF.kΩ SML-2MTT86 33pF 33pF kω kω CY7C683A-6LTXC PA PA6 PA4 PB PA PA3 PA2 LE_D2 DATA_D CLK_D PA7 PB3 CTL2_FLAGC 24LC64-I-SN LE_D2 CLK_D TSW--8-G-D DATA_D CTL_FLAGB CTL_FLAGA DM V_USB PD D4 D3 D6 D6 D D D4 D3.kΩ.kΩ.kΩ PA DP 2kΩ PD PD2 CLK RESETN PD7 PD4 PD6 PD3 PD PB7 PB PB6 PB2 PB4 PB IFCLK 2kΩ ADP3334ACPZ 3V3_USB XTALIN 22pF.kΩ.kΩ.µF pf.µf 2kΩ.µF.µF.µF.µF.µF.µF SML-2MTT86 2kΩ 78.7kΩ pf 4kΩ FB E38 pf.µf 22pF XTAL.µF SDA WAKEUP SCL µf µf 24.MHZ 3V3_USB V_USB.µF PINS GND CASE AGND PAD CLK PD7_FD PD6_FD4 PD_FD3 PD4_FD2 PD3_FD PD2_FD PD_FD9 PD_FD8 WAKEUP RESET_N PA7_FLAGD_SLCS_N PA6_PKTEND PA_FIFOADR PA4_FIFOADR PA3_WU2 PA2_SLOE PA_INT_N PA_INT_N VCC CTL2_FLAGC CTL_FLAGB CTL_FLAGA GND PB7_FD7 PB6_FD6 PB_FD PB4_FD4 PB3_FD3 PB2_FD2 PB_FD PB_FD SDA SCL RESERVED IFCLK DMINUS DPLUS AGND XTALIN XTAL AVCC RDY_SLWR RDY_SLRD IN IO IN IN2 2 PAD FB GND SD_N GND SCL SDA WC_N A2 A A VCC IN IN IN (FROM MAIN BOARD; ma MINIMUM) V_SDP R2 R22 R7 R42 R6 R8 R43 R U P P2 LE_D2 CLK_D TBD63 kω kω 24LC32A-I/MS JEDEC_TYPE=MSOP8 E46 FX8-S-SV(2) DATA_D D D4 D3 RED V_SDP FX8-S-SV(2) D6 BLK VSS VCC WP A2 A A SCL SDA Figure 76. USB/SDP Interface Circuitry on the Customer Evaluation Board

37 Figure 78. Evaluation Board Layout Bottom Figure 77. Evaluation Board Layout Top Rev. B Page 36 of 4

38 Figure 79. Evaluation Board Control Software Rev. B Page 37 of 4

39 LINE DIMENSIONS PIN INDICATOR. BSC SQ 4.7 BSC SQ.6 MAX. BSC MAX EXPOSED PAD 32 PIN INDICATOR SQ SEATING PLANE TOP VIEW 2 MAX.8 MAX.6 TYP MAX.2 NOM COPLANARITY.8. REF 6 9 BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO-2-VHHD REF Figure Lead Lead Frame Chip Scale Package [LFCSP_VQ] mm mm Body, Very Thin Quad (CP-32-3) Dimensions shown in millimeters 8.2 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUTION DESCRIPTIONS SECTION OF THIS DATA SHEET A ORDERING GUIDE Model Temperature Range Package Description Package Option ACPZ-R7 4 C to +8 C 32-Lead Lead Frame Chip Scale Package LFCSP_VQ CP EVALZ Evaluation Board Z = RoHS Compliant Part. Rev. B Page 38 of 4

40 NOTES Rev. B Page 39 of 4

41 NOTES 2 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D943--8/2(B) Rev. B Page 4 of 4