100 MHz to 4000 MHz RF/IF Digitally Controlled VGA ADL5240

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1 FEATURES Operating frequency from MHz to MHz Digitally controlled VGA with serial and parallel interfaces 6-bit,. db digital step attenuator. db gain control range with ±. db step accuracy Gain block amplifier specifications Gain: 9.7 db at. GHz OIP:. dbm at. GHz PdB: 9. dbm at. GHz Noise figure:.9 db at. GHz Gain block or digital step attenuator can be first Single supply operation from.7 V to. V Low quiescent current of 9 ma Thermally efficient, mm mm, -lead LFCSP The companion ADL integrates a ¼ W driver amplifier to the output of the gain block and DSA APPLICATIONS Wireless infrastructure Automated test equipment RF/IF gain control FUTIONAL BLOCK DIAGRAM MHz to MHz RF/IF Digitally Controlled VGA ADL GENERAL DESCRIPTION The ADL is a high performance, digitally controlled variable gain amplifier (VGA) operating from MHz to MHz. The VGA integrates a high performance, db gain, internally matched amplifier (AMP) with a 6-bit digital step attenuator (DSA) that has a gain control range of. db in. db steps with ±. db step accuracy. The attenuation of the DSA can be controlled using a serial or parallel interface. Both the gain block and DSA are internally matched to Ω at their inputs and outputs and are separately biased. The separate bias allows all or part of the ADL to be used, which facilitates easy reuse throughout a design. The pinout of the ADL also enables either the gain block or DSA to be first, giving the VGA maximum flexibility in a signal chain. The ADL consumes just 9 ma and operates from a single supply ranging from.7 V to. V. The VGA is packaged in a thermally efficient, mm mm, -lead LFCSP and is fully specified for operation from C to +8 C. A fully populated evaluation board is available. SEL D/CLK D/DATA D/LE D D D D SERIAL/PARALLEL INTERFACE DSAIN DSA.dB db db db 8dB 6dB 6 ADL 9 7 AMP AMP/VCC Figure. AMPIN 9- Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 ADL TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Revision History... Specifications... Absolute Maximum Ratings... 8 ESD Caution... 8 Pin Configuration and Function Descriptions... 9 Typical Performance Characteristics... Applications Information... 6 Basic Layout Connections... 6 SPI Timing... 8 Loop Performance... Amplifier Drive Level for Optimum ACLR... Thermal Considerations... Evaluation Board... Outline Dimensions... 8 Ordering Guide... 8 REVISION HISTORY 6/ Rev. to Rev. A Changes to Table... Changes to Table... 9 Changes to Figure... Changes to Figure 6... Added Figure 9, Renumbered Sequentially... Changes to Table, Figure, and Figure Added Amplifier Drive Level for Optimum ACLR Section and Figure 9... Changes to Evaluation Board Section... Changes to Figure and Table 8... Added Figure... Changes to Figure and Figure... 6 Added Figure / Revision : Initial Version Rev. A Page of 8

3 ADL SPECIFICATIONS = V, VCC = V, T A = o C Table. Parameter Test Conditions/Comments Min Typ Max Unit OVERALL FUTION Frequency Range MHz AMPLIFIER FREQUEY = MHz Using the AMPIN and AMP pins Gain 7.6 db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±. db vs. Supply.7 V to. V ±. db Input Return Loss S. db Output Return Loss S 7.7 db Output db Compression Point 8. dbm Output Third-Order Intercept f = MHz, P = dbm/tone. dbm Noise Figure.8 db AMPLIFIER FREQUEY = MHz Using the AMPIN and AMP pins Gain. db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±.6 db vs. Supply.7 V to. V ±. db Input Return Loss S 8. db Output Return Loss S.7 db Output db Compression Point. dbm Output Third-Order Intercept f = MHz, P = dbm/tone 9. dbm Noise Figure.9 db AMPLIFIER FREQUEY = 78 MHz Using the AMPIN and AMP pins Gain.6 db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±. db vs. Supply.7 V to. V ±. db Input Return Loss S.7 db Output Return Loss S.7 db Output db Compression Point. dbm Output Third-Order Intercept f = MHz, P = dbm/tone. dbm Noise Figure.7 db AMPLIFIER FREQUEY = 9 MHz Using the AMPIN and AMP pins Gain 9... db vs. Frequency ±8 MHz ±. db vs. Temperature C T A +8 C ±.7 db vs. Supply.7 V to. V ±. db Input Return Loss S. db Output Return Loss S.8 db Output db Compression Point 8.. dbm Output Third-Order Intercept f = MHz, P = dbm/tone. dbm Noise Figure.7 db Rev. A Page of 8

4 ADL Parameter Test Conditions/Comments Min Typ Max Unit AMPLIFIER FREQUEY = 96 MHz Using the AMPIN and AMP pins Gain 9.8 db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±.6 db vs. Supply.7 V to. V ±. db Input Return Loss S.9 db Output Return Loss S.6 db Output db Compression Point 9.8 dbm Output Third-Order Intercept f = MHz, P = dbm/tone. dbm Noise Figure.9 db AMPLIFIER FREQUEY = MHz Using the AMPIN and AMP pins Gain db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±. db vs. Supply.7 V to. V ±. db Input Return Loss S. db Output Return Loss S. db Output db Compression Point dbm Output Third-Order Intercept f = MHz, P = dbm/tone. dbm Noise Figure.9 db AMPLIFIER FREQUEY = 6 MHz Using the AMPIN and AMP pins Gain db vs. Frequency ±6 MHz ±. db vs. Temperature C T A +8 C ±. db vs. Supply.7 V to. V ±. db Input Return Loss S. db Output Return Loss S. db Output db Compression Point dbm Output Third-Order Intercept f = MHz, P = dbm/tone. dbm Noise Figure.9 db AMPLIFIER FREQUEY = 6 MHz Using the AMPIN and AMP pins Gain 9.6 db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±. db vs. Supply.7 V to. V ±. db Input Return Loss S. db Output Return Loss S. db Output db Compression Point 8.8 dbm Output Third-Order Intercept f = MHz, P = dbm/tone 7. dbm Noise Figure. db DSA FREQUEY = MHz Using the DSAIN and DSA pins Insertion Loss Minimum attenuation. db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±.9 db Attenuation Range 8.8 db Attenuation Step Error All attenuation states ±.8 db Attenuation Absolute Error All attenuation states ±. db Input Return Loss Minimum attenuation. db Output Return Loss Minimum attenuation. db Input Third-Order Intercept f = MHz, P = dbm/tone, minimum attenuation 7.9 dbm Rev. A Page of 8

5 ADL Parameter Test Conditions/Comments Min Typ Max Unit DSA FREQUEY = MHz Using the DSAIN and DSA pins Insertion Loss Minimum attenuation. db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±. db Attenuation Range.7 db Attenuation Step Error All attenuation states ±. db Attenuation Absolute Error All attenuation states ±. db Input Return Loss Minimum attenuation 7.6 db Output Return Loss Minimum attenuation 7.6 db Input Third-Order Intercept f = MHz, P = dbm/tone, minimum attenuation. dbm DSA FREQUEY = 78 MHz Using the DSAIN and DSA pins Insertion Loss Minimum attenuation.6 db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±. db Attenuation Range.9 db Attenuation Step Error All attenuation states ±. db Attenuation Absolute Error All attenuation states ±. db Input Return Loss Minimum attenuation 7. db Output Return Loss Minimum attenuation 7. db Input Third-Order Intercept f = MHz, P = dbm/tone, minimum attenuation. dbm DSA FREQUEY = 9 MHz Using the DSAIN and DSA pins Insertion Loss Minimum attenuation.6 db vs. Frequency ±8 MHz ±. db vs. Temperature C T A +8 C ±. db Attenuation Range.9 db Attenuation Step Error All attenuation states ±. db Attenuation Absolute Error All attenuation states ±. db Input Return Loss Minimum attenuation 6.6 db Output Return Loss Minimum attenuation 6. db Input db Compression Point Minimum attenuation. dbm Input Third-Order Intercept f = MHz, P = dbm/tone, minimum attenuation.9 dbm DSA FREQUEY = 96 MHz Using the DSAIN and DSA pins Insertion Loss Minimum attenuation. db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±.6 db Attenuation Range. db Attenuation Step Error All attenuation states ±. db Attenuation Absolute Error All attenuation states ±.9 db Input Return Loss Minimum attenuation. db Output Return Loss Minimum attenuation. db Input db Compression Point Minimum attenuation. dbm Input Third-Order Intercept f = MHz, P = dbm/tone, minimum attenuation 9. dbm DSA FREQUEY = MHz Using the DSAIN and DSA pins Insertion Loss Minimum attenuation. db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±.7 db Attenuation Range. db Attenuation Step Error All attenuation states ±. db Attenuation Absolute Error All attenuation states ±.6 db Input Return Loss Minimum attenuation.9 db Output Return Loss Minimum attenuation. db Input db Compression Point Minimum attenuation. dbm Input Third-Order Intercept f = MHz, P = dbm/tone, minimum attenuation 9. dbm Rev. A Page of 8

6 ADL Parameter Test Conditions/Comments Min Typ Max Unit DSA FREQUEY = 6 MHz Using the DSAIN and DSA pins Insertion Loss Minimum attenuation.6 db vs. Frequency ±6 MHz ±. db vs. Temperature C T A +8 C ±.9 db Attenuation Range. db Attenuation Step Error All attenuation states ±.6 db Attenuation Absolute Error All attenuation states ±.9 db Input Return Loss Minimum attenuation. db Output Return Loss Minimum attenuation. db Input db Compression Point Minimum attenuation. dbm Input Third-Order Intercept f = MHz, P = dbm/tone, minimum attenuation 7.6 dbm DSA FREQUEY = 6 MHz Using the DSAIN and DSA pins Insertion Loss Minimum attenuation.8 db vs. Frequency ± MHz ±. db vs. Temperature C T A +8 C ±. db Attenuation Range. db Attenuation Step Error All attenuation states ±.7 db Attenuation Absolute Error All attenuation states ±. db Input Return Loss Minimum attenuation. db Output Return Loss Minimum attenuation 8. db Input db Compression Point Minimum attenuation. dbm Input Third-Order Intercept f = MHz, P = dbm/tone, minimum attenuation 8. dbm DIGITAL STEP ATTENUATOR GAIN SETTLING Minimum Attenuation to Maximum Attenuation 6 ns Maximum Attenuation to Minimum Attenuation 6 ns AMP-DSA LOOP FREQUEY = 9 MHz Using the AMPIN and DSA pins, DSA at minimum attenuation Gain 8.9 db vs. Frequency ±8 MHz ±. db Gain Range Between maximum and minimum attenuation states.8 db Input Return Loss S. db Output Return Loss S 9.7 db Output db Compression Point 8.6 dbm Output Third-Order Intercept f = MHz, P = dbm/tone 6. dbm Noise Figure.7 db AMP-DSA LOOP FREQUEY = MHz Using the AMPIN and DSA pins, DSA at minimum attenuation Gain 8. db vs. Frequency ± MHz ±. db Gain Range Between maximum and minimum attenuation states. db Input Return Loss S.9 db Output Return Loss S 6. db Output db Compression Point 7.9 dbm Output Third-Order Intercept f = MHz, P = dbm/tone 7. dbm Noise Figure. db Rev. A Page 6 of 8

7 ADL Parameter Test Conditions/Comments Min Typ Max Unit AMP-DSA LOOP FREQUEY = 6 MHz Using the AMPIN and DSA pins, DSA at minimum attenuation Gain 7.7 db vs. Frequency ±6 MHz ±. db Gain Range. db Input Return Loss S. db Output Return Loss S 9.6 db Output db Compression Point 6.9 dbm Output Third-Order Intercept f = MHz, P = dbm/tone.7 dbm Noise Figure. db DSA-AMP LOOP FREQUEY = 9 MHz Using the DSAIN and AMP pins, DSA at minimum attenuation Gain 8.9 db vs. Frequency ±8 MHz ±. db Gain Range Between maximum and minimum attenuation states.8 db Input Return Loss S 7. db Output Return Loss S.7 db Output db Compression Point. dbm Output Third-Order Intercept f = MHz, P = dbm/tone. dbm Noise Figure. db DSA-AMP LOOP Frequency = MHz Using the DSAIN and AMP pins, DSA at minimum attenuation Gain 8. db vs. Frequency ± MHz ±. db Gain Range Between maximum and minimum attenuation states. db Input Return Loss S.7 db Output Return Loss S. db Output db Compression Point 9.7 dbm Output Third-Order Intercept f = MHz, P = dbm/tone 7. dbm Noise Figure.9 db DSA-AMP LOOP Frequency = 6 MHz Using the DSAIN and AMP pins, DSA at minimum attenuation Gain 8. db vs. Frequency ±6 MHz ±. db Gain Range Between maximum and minimum attenuation states.7 db Input Return Loss S.7 db Output Return Loss S 6.9 db Output db Compression Point 9.8 dbm Output Third-Order Intercept f = MHz, P = dbm/tone.8 dbm Noise Figure. db LOGIC INPUTS CLK, DATA, LE, SEL, D~D6 Input High Voltage, VINH. V Input Low Voltage, VINL.8 V Input Current, IINH/IINL. µa Input Capacitance, CIN. pf POWER SUPPLIES Using the and VCC pins Voltage.7.. V Supply Current Amplifier 9 ma Digital Step Attenuator. ma Rev. A Page 7 of 8

8 ADL ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage (, VCC) 6. V Input Power AMPIN 6 dbm DSAIN dbm Internal Power Dissipation. W θ JA (Exposed Pad Soldered Down) 6.8 C/W θ JC (Exposed Pad is the Contact) 6.9 C/W Maximum Junction Temperature C Lead Temperature (Soldering, 6 sec) C Operating Temperature Range C to +8 C Storage Temperature Range 6 C to + C ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A Page 8 of 8

9 AMP/VCC AMPIN 9 6 SEL D/CLK D/DATA 9 D/LE ADL PIN CONFIGURATION AND FUTION DESCRIPTIONS 8 D 7 D 6 D D6 DSAIN PIN INDICATOR ADL TOP VIEW (Not to Scale) DSA NOTES. = NO CONNECT. DO NOT CONNECT TO THIS PIN.. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure. Pin Configuration 9- Table. Pin Function Descriptions Pin No. Mnemonic Description, Supply Voltage for DSA. Connect this pin to a V supply.,,, 6, 7, 8, 9,,, No Connect. Do not connect to this pin.,, 6, 7, 8, 9,,, DSAIN RF Input to DSA. AMP/VCC RF Output from Amplifier/Supply Voltage for Amplifier. A bias to the amplifier is provided through a choke inductor connected to this pin. AMPIN RF Input to Amplifier. DSA RF Output from DSA. D6 Data Bit in Parallel Mode (LSB). Connect this pin to the supply in serial mode. 6 D Data Bit in Parallel Mode. Connect this pin to ground or leave open in serial mode. 7 D Data Bit in Parallel Mode. Connect this pin to ground or leave open in serial mode. 8 D Data Bit in Parallel Mode. Connect this pin to ground or leave open in serial mode. 9 D/LE Data Bit in Parallel Mode/Latch Enable in Serial Mode. D/DATA Data Bit in Parallel Mode (MSB)/Data in Serial Mode. D/CLK Connect this pin to ground in parallel mode. This pin functions as a clock in serial mode. SEL Select Pin. Connect this pin to the supply to select parallel mode operation; connect this pin to ground to select serial mode operation. EPAD Exposed Pad. The exposed pad must be connected to ground. Rev. A Page 9 of 8

10 ADL TYPICAL PERFORMAE CHARACTERISTICS NOISE FIGURE, GAIN, PdB, OIP (db, dbm) OIP NOISE FIGURE GAIN PdB FREQUEY (GHz) Figure. AMP: Gain, PdB, OIP at P = dbm/tone and Noise Figure vs. Frequency 9- PdB (dbm) C + C C FREQUEY (GHz) Figure 6. AMP: OIP at P = dbm/tone and PdB vs. Frequency and Temperature OIP (dbm) C MHz 96MHz MHz 9MHz GAIN (db) C +8 C OIP (dbm) MHz 6MHz MHz 6MHz FREQUEY (GHz) P PER TONE (dbm) 9-7 Figure. AMP: Gain vs. Frequency and Temperature Figure 7. AMP: OIP vs. P and Frequency.. S-PARAMETERS (db) S S NOISE FIGURE (db) C + C C S FREQUEY (GHz) Figure. AMP: Input Return Loss (S), Output Return Loss (S), and Reverse Isolation (S) vs. Frequency FREQUEY (GHz) Figure 8. AMP: Noise Figure vs. Frequency and Temperature 9-8 Rev. A Page of 8

11 ADL db. ATTENUATION (db) STEP ERROR (db) dB.dB.dB db.db FREQUEY (GHz) FREQUEY (GHz) 9-6 Figure 9. DSA: Attenuation vs. Frequency Figure. DSA: Step Error vs. Frequency, All Attenuation States 6 db db..8.6 MHz 96MHz 78MHz ATTENUATION (db) 6 6 8dB 6dB.dB FREQUEY (GHz) +8 C + C C Figure. DSA: Attenuation vs. Frequency and Temperature 9- ABSOLUTE ERROR (db).. MHz 6MHz 9MHz...6 6MHz ATTENUATION (db) Figure. DSA: Absolute Error vs. Attenuation 9- STEP ERROR (db) MHz 78MHz 9MHz 96MHz MHz 6MHz 6MHz INPUT RETURN LOSS (db) db.db ATTENUATION (db) Figure. DSA: Step Error vs. Attenuation FREQUEY (GHz) Figure. DSA: Input Return Loss vs. Frequency, All States 9- Rev. A Page of 8

12 ADL PUT RETURN LOSS (db) db.db FREQUEY (GHz) Figure. DSA: Output Return Loss vs. Frequency, All States 9- CH.V CH mv Mns GS/s IT.ps/pt A CH.V Figure 8. DSA: Gain Settling Time, db to. db IIP IPdB (dbm) IIP (dbm) IPdB FREQUEY (GHz) Figure 6. DSA: Input PdB and Input IP vs. Frequency, Minimum Attenuation State 9- CH.V CH mv Mns GS/s IT.ps/pt A CH.V Figure 9. DSA: Gain Settling Time,. db to db 9-9 PHASE (Degrees) 96MHz MHz 6MHz 9MHz GAIN AND NOISE FIGURE (db) GAIN NOISE FIGURE ATTENUATION (db) FREQUEY (GHz) 9- Figure 7. DSA: Phase vs. Attenuation Figure. AMP-DSA Loop: Gain and Noise Figure vs. Frequency, Minimum Attenuation State Rev. A Page of 8

13 ADL S-PARAMETERS (db) S S S GAIN AND NOISE FIGURE (db) GAIN NOISE FIGURE FREQUEY (GHz) Figure. AMP-DSA Loop: Input Return Loss (S), Output Return Loss (S), and Reverse Isolation (S) vs. Frequency, Minimum Attenuation State FREQUEY (GHz) Figure. DSA-AMP Loop: Gain and Noise Figure vs. Frequency, Minimum Attenuation State 9- OIP (dbm) MHz 6MHz 9MHz P (dbm) 9- S-PARAMETERS (db) S S FREQUEY (GHz) S 9- Figure. AMP-DSA Loop: OIP vs. P and Frequency, Minimum Attenuation State Figure. DSA-AMP Loop: Input Return Loss (S), Output Return Loss (S), and Reverse Isolation (S) vs. Frequency, Minimum Attenuation State. 9. GAIN (db) MHz MHz 6MHz OIP (dbm) 8 6 9MHz MHz MHz P (dbm) P (dbm) 9-6 Figure. AMP-DSA Loop: Gain vs. P and Frequency, Minimum Attenuation State Figure 6. DSA-AMP Loop: OIP vs. P and Frequency, Minimum Attenuation State Rev. A Page of 8

14 ADL MHz GAIN (db) MHz 6MHz PERCENTAGE (%) P (dbm) Figure 7. DSA-AMP Loop: Gain vs. P and Frequency, Minimum Attenuation State GAIN (db) Figure. AMP: Gain Distribution at MHz 9-9 SUPPLY CURRENT (ma) V.V.7V PERCENTAGE (%) TEMPERATURE ( C) Figure 8. AMP: Supply Current vs. Voltage and Temperature PdB (dbm) Figure. AMP: PdB Distribution at MHz 9- SUPPLY CURRENT (ma) 9 9 C + C +8 C PERCENTAGE (%) P PER TONE (dbm) OIP (dbm) Figure. AMP: OIP Distribution at MHz 9- Figure 9. AMP: Supply Current vs. P and Temperature Rev. A Page of 8

15 ADL 7 6 PERCENTAGE (%) NOISE FIGURE (db) 9- Figure. AMP: Noise Figure Distribution at MHz Rev. A Page of 8

16 ADL APPLICATIONS INFORMATION BASIC LAY CONNECTIONS The basic connections for operating the ADL are shown in Figure. SERIAL PARALLEL INTERFACE.µF C DSAIN pf C DSAIN SEL AMP/VCC D/CLK D/DATA D/LE D D AMPIN D D6 ADL DSA pf C7 DSA 9 6 AMP.µF.µF AMPIN C L 7nH C C 68pF C VCC.nF C µf Figure. Basic Connections 9- Rev. A Page 6 of 8

17 ADL Amplifier Bias The dc bias for the amplifier in ADL is supplied through Inductor L and is connected to the AMP pin. Three decoupling capacitors (C, C, and C) are used to prevent RF signals from propagating onto the dc lines. The dc supply ranges from.7 V to. V and should be connected to the VCC test point on the evaluation board. Digital Step Attenuator Bias The bias for the DSA is provided through the pin. At least one decoupling capacitor (C8) is recommended on the trace. The voltage ranges from.7 V to. V and should be connected to the test point on the evaluation board. The DSA is shown to work for dc voltages as low as. V. Amplifier RF Input Interface Pin is the RF input for the amplifier of ADL. The amplifier is internally matched to Ω at the input; therefore, no external components are required. Only a dc blocking capacitor (C) is required. Amplifier RF Output Interface Pin is the RF output for the amplifier of ADL. The amplifier is internally matched to Ω at the output; therefore, no external components are required. Only a dc blocking capacitor (C) is required. The bias is provided through this pin via a choke inductor. DSA RF Input Interface Pin is the RF input for the DSA of ADL. The input impedance of the DSA is close to Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C6) is required. DSA RF Output Interface Pin is the RF output for the DSA of ADL. The output impedance of the DSA is close to Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C7) is required. DSA SPI Interface The DSA of the ADL can operate in either serial or parallel mode. Pin (SEL) controls the mode of operation. To select serial mode, connect SEL to ground; to select parallel mode, connect SEL to. In parallel mode, Pin to Pin (D6 to D) are the data bits, with D6 being the LSB. Connect Pin (D) to ground during the parallel mode of operation. In serial mode, Pin 9 is the latch enable (LE), Pin is the data (DATA), and Pin is the clock (CLK). Pin 6, Pin 7, and Pin 8 are not used in serial mode and should be connected to ground. Pin (D6) should be connected to during the serial mode of operation. To prevent noise from coupling onto the digital signals, an RC filter can be used on each data line. Rev. A Page 7 of 8

18 ADL SPI TIMING Table provides details about the timing characteristics for the SPI signals namely, the clock (CLK), latch enable (LE), and data (DATA) signals and Figure shows the corresponding SPI timing diagram. SPI Timing Sequence Figure 6 is the timing sequence for the SPI function using a 6-bit operation. The clock can be as fast as MHz. In serial mode, Register B (MSB) is first and Register B (LSB) is last. Table. Mode Selection Table Pin (SEL) Functionality Connect to Ground Serial mode Connect to Supply Parallel mode Table. SPI Timing Setup Parameter Limit Unit Test Conditions/Comments f CLK MHz Data clock frequency t ns min Clock high time t ns min Clock low time t ns min Data to clock setup time t ns min Clock to data hold time t ns min Clock low to LE setup time t 6 ns min LE pulse width CLK t t t t t DON'T CARE DON'T CARE DATA LE MSB DON'T CARE B B B B B LSB B DON'T CARE t 6 Figure. SPI Timing Diagram (Data Is Loaded MSB First), Serial Mode 9- D/CLK DON'T CARE DON'T CARE D/DATA MSB DON'T CARE B B B B B LSB B DON'T CARE D/LE D6 Figure 6. SPI Timing Sequence, Serial Mode 9- Rev. A Page 8 of 8

19 ADL Table 6. DSA Attenuation Truth Table Serial Mode Attenuation State (db) B (MSB) B B B B B (LSB) (Reference) Table 7. DSA Attenuation Truth Table Parallel Mode Attenuation State (db) D (MSB) D D D D D6 (LSB) (Reference) Rev. A Page 9 of 8

20 ADL LOOP PERFORMAE The ADL can be configured so that either the DSA precedes the amplifier (see Figure 7) or the amplifier precedes the DSA (see Figure 8). The performance of the loop configurations is presented in Figure to Figure 7. To improve the overall return loss, a shunt capacitor can be placed between the amplifier and DSA. This helps to align the phases of the two blocks. SERIAL PARALLEL INTERFACE.µF C RFIN pf C DSAIN SEL AMP/VCC D/CLK D/DATA D/LE D ADL D D AMPIN D6 DSA RF.µF pf C L 7nH C C 68pF C.nF VCC C µf Figure 7. DSA-AMP Loop Configuration 9-6 Rev. A Page of 8

21 ADL SERIAL PARALLEL INTERFACE.µF C C pf DSAIN SEL AMP/VCC D/CLK D/DATA D/LE D ADL D D AMPIN D6 DSA pf C6 RF 9 6.µF RFIN L 7nH C C 68pF C VCC.nF C µf Figure 8. AMP-DSA Loop Configuration 9-7 Rev. A Page of 8

22 ADL AMPLIFIER DRIVE LEVEL FOR OPTIMUM ACLR It is usually required to drive the amplifier as high as possible in order to maximize output power. However, properly driving Amplifier at the ADL is required to achieve optimum ACLR performance. Once output power approaches PdB and OIP, there is ACLR degradation. The driving level of amplifier with a modulated signal should be backed off properly from PdB by at least the amount of a signal crest factor for optimum ACLR. So assuming a gain and output PdB of Amplifier at MHz are 9 db and 9 dbm respectively, the output power, which is backed off by db crest factor at the modulated signal case, is 8 dbm. Therefore, the proper input driving level should be under dbm. AMP_ADJ THERMAL CONSIDERATIONS The ADL is packaged in a thermally efficient, mm mm, -lead LFCSP. The thermal resistance from junction to air (θ JA) is 6.8 o C/W. The thermal resistance for the product was extracted assuming a standard -layer JEDEC board with conductive, epoxy filled thermal vias. The thermal resistance from junction to case (θ JC) is 6.9 o C/W, where case is the exposed pad of the lead frame package. The ADL consumes approximately 9 ma with a V supply voltage. Even though the part dissipates less than. W, for the best thermal performance, it is recommended to add as many thermal vias as possible under the exposed pad of the LFC SP. The thermal resistance values given in this section assume a minimum of thermal vias arranged in a array with a diameter of mils and a pitch of mils. Figure shows a close-up of the thermal via distribution under the exposed pad. ACPR (dbc) AMP_ALT 9 P IN (dbm) Figure 9. Single Carrier WCDMA Adjacent Chanel Power Ratio vs. Input Power at Amplifier, MHz 9- Figure. Exposed Pad with Thermal Via Distribution 9-8 Rev. A Page of 8

23 EVALUATION BOARD The schematic of the ADL evaluation board is shown in Figure, the evaluation board configuration options are detailed in Table 8, and the layout of the ADL evaluation board is shown in Figure and Figure. Each RF trace on the evaluation board has a characteristic impedance of Ω and is fabricated on Rogers material. In addition, each trace is a coplanar waveguide (CPWG) with a width of mils, a spacing of mils, and a dielectric thickness of mils. The input to and output from the DSA and amplifier should be ac-coupled with capacitors of appropriate values to ensure the broadband performance. The bias to the amplifier is provided by connecting a choke to the AMP pin. Bypassing capacitors are recommended on all supply lines to minimize the RF coupling. The DSA and the amplifier can be individually biased or connected to the plane using Resistors R and R. The ADL can be operated in two ways: the amplifier can precede the DSA (AMP-DSA loop configuration) or the DSA can precede the amplifier (DSA-AMP loop configuration). The evaluation board can be configured to handle either option. In normal operation, R and R are open, and R and R are Ω and are used to terminate any RF coupling onto the bypass trace. To configure the ADL in AMP-DSA loop configuration, R should be replaced with a capacitor, R should be replaced with a Ω resistor, and R and R should be left open. Similarly, to configure the ADL in the DSA-AMP loop configuration, R6 should be replaced with a capacitor, R7 should be replaced with a Ω resistor, and R and R should be left open. ADL The digital signal traces incorporate a footprint for an RC filter to prevent potential noise from coupling onto the signal. In normal operation, series resistors are Ω and shunt resistors and capacitors are open. The evaluation board is designed to control DSA in either parallel or serial mode by connecting the SEL pin to the supply or ground by a switch. For adjusting attenuation at DSA, the ADL can be programmed in two ways: through the on-board USB interface from a PC USB port, or through an SDP board, which will become the Analog Devices common control board in the future. The on-board USB interface circuitry of the evaluation board is powered directly by the PC. USB based programming software is available to download from the ADL product page at Figure shows the window of the programming software where the user selects serial or parallel mode for the attenuation adjustment at DSA. The selection of the mode in the window should match the mode of the evaluation board switch. It is highly recommended to refer the evaluation board layout for the optimal and stable performance of each block as well as for the improvement of thermal efficiency. Rev. A Page of 8

24 ADL AGND R S RED CLK_D DATA_D LE_D D D D D6.µF C7 PAD U AGND DSAIN AMP AGND C pf AGND C R R R R DSAIN AGND EPAD SEL D/CLK D/DATA D/LE D D D D6 ADLACPZ AMP/VCC AMPIN 9 6 DSA AGND AGND R6 R7 R R C pf C8.µF DSA AGND AMPIN AGND.µF AGND R C µf VCC RED C pf L 7nH C 68pF AGND Figure. ADL Evaluation Board 9-9 Table 8. Evaluation Board Configuration Options Component Function/Notes Default Value C, C Input/output dc blocking capacitors for DSA. C, C = pf C, C Input/output dc blocking capacitors for AMP. C, C =. µf C, C6, C7 Power supply decoupling for amplifier. The bias associated with the AMP pin is the most sensitive to noise because the bias is connected directly to the output. The smallest capacitor (C7) should be the closest to the AMP pin. C = µf C6 =. nf C7 = 68 pf C8 Power supply decoupling for the DSA. C8 =. µf L The bias for the amplifier comes through L when VCC is connected to a V supply. L = 7 nh L should be high impedance for the frequency of operation while providing low resistance for the dc current. R, R Resistors to connect the supply for the amplifier and the DSA to the same plane. R, R = open R, R, R, R These resistors are used to terminate RF coupling onto the traces and to close the loop. R, R, R, R = Ω R, R, R6, R7 R and R6 are replaced with capacitors, and R and R7 are replaced with Ω to close the loop. R, R, R6, R7 = open S Switch to change between the serial mode and parallel mode of operation. Connect to supply for parallel mode and to ground for serial mode operation. S connected to ground Rev. A Page of 8

25 ADL Rev. A Page of 8 DECOUPLING FOR U PLACEHOLDER R9 C9 R8 C8 R7 C6 C R6 R R R R9 R6 A C CR R8 R R R R C R C R C P PAD U C C6 C8 C9 C C6 C8 R A C D R C7 6 PAD 8 7 U R C R9 C U R C9 C R7 R7 C C G G G G P C Y C C C9 pf.kω Ω JEDEC_TYPE=QFN6_8X8_PAD_X_ pf pf pf pf.kω SML-MTT86 pf pf kω kω CY7C68A-6LTXC PA PA6 PA PB PA PA PA LE_D DATA_D CLK_D PA7 PB CTL_FLAGC LC6-I-SN LE_D CLK_D TSW--8-G-D DATA_D CTL_FLAGB CTL_FLAGA DM V_USB PD D D D6 D6 D D D D.kΩ.kΩ.kΩ Ω PA Ω Ω Ω Ω Ω DP kω PD PD CLK RESETN PD7 PD PD6 PD PD PB7 PB PB6 PB PB PB IFCLK kω ADPACPZ V_USB XTALIN pf.kω.kω.µf pf.µf kω.µf.µf.µf.µf.µf.µf SML-MTT86 kω 78.7kΩ pf kω FB E8 pf.µf pf XTAL.µF SDA WAKEUP SCL µf µf.mhz V_USB Ω V_USB.µF PINS GND CASE AGND PAD CLK PD7_FD PD6_FD PD_FD PD_FD PD_FD PD_FD PD_FD9 PD_FD8 WAKEUP RESET_N PA7_FLAGD_SLCS_N PA6_PKTEND PA_FIFOADR PA_FIFOADR PA_WU PA_SLOE PA_INT_N PA_INT_N VCC CTL_FLAGC CTL_FLAGB CTL_FLAGA GND PB7_FD7 PB6_FD6 PB_FD PB_FD PB_FD PB_FD PB_FD PB_FD SDA SCL RESERVED IFCLK DMINUS DPLUS AGND XTALIN XTAL AVCC RDY_SLWR RDY_SLRD IN IO IN IN PAD FB GND SD_N GND SCL SDA WC_N A A A VCC IN IN IN (FROM MAIN BOARD; ma MINIMUM) V_SDP R R R7 R R6 R8 R R U P P LE_D CLK_D TBD6 kω kω LCA-I/MS JEDEC_TYPE=MSOP8 E6 Ω FX8-S-SV() Ω DATA_D Ω Ω Ω D D D RED V_SDP FX8-S-SV() D6 BLK VSS VCC WP A A A SCL SDA 9- Figure. USB/SDP Interface Circuitry on the Customer Evaluation Board

26 ADL Figure. Evaluation Board Layout Top 9- Figure. Evaluation Board Layout Bottom 9- Rev. A Page 6 of 8

27 ADL Figure. Evaluation Board Control Software 9- Rev. A Page 7 of 8

28 ADL LINE DIMENSIONS PIN INDICATOR. BSC SQ.7 BSC SQ.6 MAX. BSC.6 MAX EXPOSED PAD PIN INDICATOR.. SQ SEATING PLANE TOP VIEW MAX.8 MAX.6 TYP MAX. NOM COPLANARITY.8. REF 6 9 BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO--VHHD- 7. REF Figure 6. -Lead Lead Frame Chip Scale Package [LFCSP_VQ] mm mm Body, Very Thin Quad (CP--) Dimensions shown in millimeters 8. MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ---A ORDERING GUIDE Model Temperature Range Package Description Package Option ADLACPZ-R7 C to +8 C Lead LFCSP_VQ, 7" Tape and Reel CP-- ADL-EVALZ Evaluation Board Z = RoHS Compliant Part. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D9--6/(A) Rev. A Page 8 of 8

100 MHz to 4000 MHz RF/IF Digitally Controlled VGA ADL5240

100 MHz to 4000 MHz RF/IF Digitally Controlled VGA ADL5240 1 MHz to 4 MHz RF/IF Digitally Controlled VGA ADL524 FEATURES Operating frequency from 1 MHz to 4 MHz Digitally controlled VGA with serial and parallel interfaces 6-bit,.5 db digital step attenuator 31.5