FOD3150 High Noise Immunity, 1.0A Output Current, Gate Drive Optocoupler

Transcription

1 FOD0 High Noise Immunity,.0A Output Current, Gate Drive Optocoupler Features High noise immunity characterized by 0kV/µs minimum common mode rejection Use of P-channel MOSFETs at output stage enables output voltage swing close to the supply rail Wide supply voltage range from V to 0V Fast switching speed 00ns max. propagation delay 00ns max. pulse width distortion Under Voltage LockOut (UVLO) with hysteresis Extended industrial temperate range, -0 C to 00 C temperature range Safety and regulatory pending approvals UL77, 000 V RMS for min. IEC077-- (approval pending) >.0mm clearance and creepage distance (option T ) Applications Industrial inverter Uninterruptible power supply Induction heating Isolated IGBT/Power MOSFET gate drive Description October 00 The FOD0 is a.0a Output Current Gate Drive Optocoupler, capable of driving most 00V/0A IGBT/MOSFET. It is ideally suited for fast switching driving of power IGBT and MOSFETs used in motor control inverter applications, and high performance power system. It utilizes Fairchild s patented coplanar packaging technology, Optoplanar, and optimized IC design to achieve high noise immunity, characterized by high common mode rejection. It consists of a gallium aluminum arsenide (AlGaAs) light emitting diode optically coupled to an integrated circuit with a high-speed driver for push-pull MOSFET output stage. Related Resources FOD0,.A Output Current, Gate Drive Optocoupler Datasheet Functional Block Diagram Package Outlines NC V CC ANODE 7 CATHODE NC V EE Note: A 0.µF bypass capacitor must be connected between pins and. 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

2 Truth Table Pin Definitions V CC V EE Positive Going (Turn-on) V CC V EE Negative Going (Turn-off) LED Off 0V to 0V 0V to 0V Low On 0V to V 0V to 9.V Low On V to.v 9.V to V Transition On.V to 0V V to 0V High Pin # Name Description NC Not Connected Anode LED Anode Cathode LED Cathode NC Not Connected V EE Negative Supply Voltage Output Voltage (internally connected to ) 7 Output Voltage V CC Positive Supply Voltage 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

3 Safety and Insulation Ratings As per IEC This optocoupler is suitable for safe electrical insulation only within the safety limit data. Compliance with the safety ratings shall be ensured by means of protective circuits. Symbol Parameter Min. Typ. Max. Unit Installation Classifications per DIN VDE 00/.9 Table For Rated Main Voltage < 0Vrms IIV For Rated Main Voltage < 00Vrms IIV For Rated Main Voltage < 0Vrms IIII For Rated Main Voltage < 00Vrms IIII Climatic Classification /00/ Pollution Degree (DIN VDE 00/.9) CTI Comparative Tracking Index 7 V PR Input to Output Test Voltage, Method b, 9 V IORM x.7 = V PR, 00% Production Test with tm = sec., Partial Discharge < pc Input to Output Test Voltage, Method a, V IORM x. = V PR, Type and Sample Test with tm = 0 sec.,partial Discharge < pc V IORM Max Working Insulation Voltage 90 V peak V IOTM Highest Allowable Over Voltage 000 V peak External Creepage mm External Clearance 7. mm External Clearance (for Option T-0. Lead Spacing) 0. mm Insulation Thickness 0. mm Safety Limit Values Maximum Values Allowed in the Event of a Failure T Case Case Temperature 0 C I S,INPUT Input Current ma P S,OUTPUT Output Power (Duty Factor.7%) 0 mw R IO Insulation Resistance at T S, V IO = 00V 0 9 Ω 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

4 Absolute Maximum Ratings (T A = ºC unless otherwise specified) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Value Units T STG Storage Temperature - to ºC T OPR Operating Temperature -0 to 00 ºC T J Junction Temperature -0 to ºC T SOL Lead Wave Solder Temperature 0 for 0sec ºC (refer to page 9 for reflow solder profile) I F(AVG) Average Input Current ma V R Reverse Input Voltage V I O(PEAK) Peak Output Current (). A V CC V EE Supply Voltage 0 to V (PEAK) Peak Output Voltage 0 to V CC V t R(IN), t F(IN) Input Signal Rise and Fall Time 00 ns PD I Input Power Dissipation ()() mw PD O Output Power Dissipation ()() 0 mw Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Value Units T A Ambient Operating Temperature -0 to 00 C V CC V EE Power Supply to 0 V I F(ON) Input Current (ON) 7 to ma V F(OFF) Input Voltage (OFF) 0 to 0. V Isolation Characteristics Apply over all recommended conditions, typical value is measured at T A = ºC Symbol Parameter Conditions Min. Typ. Max. Units V ISO Input-Output Isolation Voltage T A = ºC, R.H.< 0%, t =.0min, 000 V RMS I I-O 0µA, 0Hz ()() R ISO Isolation Resistance V I-O = 00V () 0 Ω C ISO Isolation Capacitance V I-O = 0V, Freq =.0MHz () pf 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

5 Electrical Characteristics Apply over all recommended conditions, typical value is measured at V CC = 0V, V EE = Ground, T A = C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units V F Input Forward Voltage I F = 0mA... V (V F / T A ) Temperature Coefficient of Forward Voltage -. mv/ºc BV R Input Reverse Breakdown Voltage I R = 0µA V C IN Input Capacitance f = MHz, VF = 0V 0 pf I OH High Level Output Current () = V CC 0.7V 0. A = V CC V.0 I OL Low Level Output Current () = V EE 0.7V 0. A = V EE V.0 H High Level Output Voltage I F = 0mA, I O = -A V CC V V CC V V I F = 0mA, I O = -00mA V CC 0.V V CC 0.V L Low Level Output Voltage I F = 0mA, I O = A V EE V V EE V V I F = 0mA, I O = 00mA V EE 0.V V EE 0.V I CCH High Level Supply Current = Open, I F = 7 to ma. ma I CCL Low Level Supply Current = Open, V F = 0 to 0.V. ma I FLH Threshold Input Current Low to High I O = 0mA, > V..0 ma V FHL Threshold Input Voltage I O = 0mA, < V 0. V High to Low V UVLO Under Voltage Lockout I F = 0mA, > V.7. V V UVLO Threshold I F = 0mA, < V V UVLO HYS Under Voltage Lockout Threshold Hysteresis. V 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

6 Switching Characteristics Apply over all recommended conditions, typical value is measured at V CC = 0V, V EE = Ground, T A = C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units t PHL Propagation Delay Time to Logic I F = 7mA to ma, ns t PLH Low Output Propagation Delay Time to Logic Rg = 0Ω, Cg =0nF, f = 0kHz, Duty Cycle = 0% ns High Output PWD Pulse Width Distortion, 0 00 ns t PHL t PLH PDD Propagation Delay Difference -0 0 ns (Skew) Between Any Two Parts or Channels, (t PHL t PLH ) (7) t r Output Rise Time (0% 90%) 0 ns t f Output Fall Time (90% 0%) 0 ns t UVLO ON UVLO Turn On Delay I F = 0mA, > V. µs t UVLO OFF UVLO Turn Off Delay I F = 0mA, < V 0. µs CM H Common Mode Transient Immunity at Output High CM L Common Mode Transient Immunity at Output Low T A = C, V CC = 0V, I F = 7 to ma, V CM = 000V () 0 0 kv/µs T A = C, V CC = 0V, V F = 0V, 0 0 kv/µs V CM = 000V (9) Notes:. Maximum pulse width = 0µs, maximum duty cycle = 0.%. Derate linearly above 7 C, free air temperature at a rate of 0.77mW/ C. No derating required across temperature range.. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside these ratings.. Device is considered a two terminal device: Pins and are shorted together and Pins,, 7 and are shorted together..,000 V RMS for minute duration is equivalent to,000 VAC RMS for second duration. 7. The difference between t PHL and t PLH between any two FOD0 parts under same test conditions.. Common mode transient immunity at output high is the maximum tolerable negative dvcm/dt on the trailing edge of the common mode impulse signal, Vcm, to assure that the output will remain high (i.e. >.0V). 9. Common mode transient immunity at output low is the maximum tolerable positive dvcm/dt on the leading edge of the common pulse signal, Vcm, to assure that the output will remain low (i.e. <.0V). 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

7 Typical Performance Curves L -OUTPUTLOWVOLTAGE (V) (H -V CC )-OUTPUTHIGHVOLTAGE DROP (V) I CC -SUPPLY CURRENT (ma) Fig. Output High Voltage Drop vs. Output High Current Fig. Output Low Voltage vs. Output Low Current Frequency = 0Hz Duty Cycle = 99.9% V F(OFF) =-.0V to 0.V V CC = V to 0V V EE =0V Fig. Supply Current vs. Ambient Temperature V CC = 0V V EE =0V I F =0mA(forI CC L ) I F = 0mA (for I CCH ) I CCH I CC L T A = C I OH -OUTPUT HIGH CURRENT (A) T A = C I OL -OUTPUTLOWCURRENT (A) Frequency = 0Hz Duty Cycle = 0.% I F =7tomA V CC =to0v V EE =0V T A =-0 C T A =00 C T A = 00 C T A =-0 C (H -V CC )-HIGHOUTPUT VOLTAGE DROP (V) L -OUTPUTLOWVOLTAGE(V) I CC -SUPPLY CURRENT (ma) Fig. Output High Voltage Drop vs. Ambient Temperature V CC =Vto 0V V EE =0V I F =7mAto ma I O =-00mA T A -AMBIENTTEMPERATURE ( C) Fig. Output Low Voltage vs. Ambient Temperature V CC =Vto 0V V EE =0V V F(OFF) =-Vto 0.V I O = 00mA T A -AMBIENTTEMPERATURE ( C) Fig. Supply Current vs. Supply Voltage I F = 0mA (for I CCH ) I F =0mA(forI CC L ) V EE =0,T A = C I CC H I CC L T A -AMBIENTTEMPEATURE ( C) V CC -SUPPLY VOLTAGE (V) 00 Fairchild Semiconductor Corporation FOD0 Rev..0. 7

8 Typical Performance Curves (Continued) t P PROPAGATION DELAY (ns) I FLH -LOWTOHIGH CURRENT THRESHOLD (ma) t P PROPAGATION DELAY (ns) Fig. 7 Low to High Input Current Threshold vs. Ambient Temperature Fig. 9 Propagation Delay vs. LED Forward Current V CC =Vto0V V EE =0V Output =Open V CC =0V,V EE =0V Rg = 0Ω, Cg=0nF T A = C DUTY CYCLE = 0% f=0khz I F FORWARDLEDCURRENT (ma) Fig. Propagation Delay vs. Series Load Resistance I F = 0mA V CC = 0V, V EE =0V Cg = 0nF T A = C DUTY CYCLE = 0% f=0khz T A -AMBIENTTEMPERATURE ( C) t PHL t PLH t PHL t PLH t P PROPAGATION DELAY (ns) t P PROPAGATION DELAY(ns) t P PROPAGATION DELAY(ns) Fig. Propagation Delay vs. Supply Voltage I F = 0mA T A = C Rg = 0Ω, Cg=0nF DUTY CYCLE = 0% f=0khz t PHL t PLH V CC SUPPLY VOLTAGE (V) Fig. 0 Propagation Delay vs. Ambient Temperature I F = 0mA V CC = 0V, V EE =0V Rg = 0Ω, Cg=0nF DUTY CYCLE = 0% f=0khz t PHL t PLH T A AMBIENT TEMPERATURE ( C) Fig. Propagation Delay vs. Load Capacitance I F = 0mA V CC = 0V, V EE =0V Rg = 0Ω T A = C DUTY CYCLE = 0% f=0khz t PHL t PLH R g - SERIES LOAD RESISTANCE (Ω) C g -LOAD CAPACITANCE (nf) 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

9 Typical Performance Curves (Continued) OUTPUTVOLTAGE (V) Fig. Transfer Characteristics T A = C V CC =0V I FORWARD LED CURRENT (ma) F OUTPUTVOLTAGE (V) I F -FORWARD CURRENT (ma) Fig. Under Voltage Lockout (.7,.0) (.,.0) 0 (.0,0.00) (.70, 0.00) (V CC -V EE )SUPPLY VOLT AGE (V) Fig. Input Forward Current vs. Forward Voltage 00 0 T A = 00 C T A =-0 C 0. T A = C V F -FORWARDVOLTAGE (V) 00 Fairchild Semiconductor Corporation FOD0 Rev..0. 9

10 Test Circuit Pulse Generator PW =.99ms Period = ms R OUT = 0Ω Test Conditions: Frequency = 00Hz Duty Cycle = 99.% V CC = V to 0V V EE = 0V V F(OFF) = -.0V to 0.V Pulse Generator PW = 0µs Period = ms R OUT = 0Ω Pulse-In LED-IFmon Pulse-In LED-IFmon R 00Ω R 00Ω R 00Ω R 00Ω Figure 0. I OL Test Circuit 7 7 L H Ioh C 0.µF Iol D C 0.µF D Current Probe C 7µF C 0.µF To Scope C 7µF C 0.µF To Scope C 7µF C 7µF Power Supply V CC = V to 0V Power Supply V = V Power Supply V CC = V to 0V Power Supply V = V Test Conditions: Frequency = 00Hz Duty Cycle = 0.% V CC = V to 0V V EE = 0V I F = 7mA to ma Figure. I OH Test Circuit 00 Fairchild Semiconductor Corporation FOD0 Rev..0. 0

11 Test Circuit (Continued) I F = 7 to ma 7 0.µF 00mA Figure. H Test Circuit 7 0.µF Figure. L Test Circuit 00mA V CC = to 0V V CC = to 0V 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

12 Test Circuit (Continued) I F = 7 to ma V F = 0 to 0.V 7 0.µF Figure. I CCH Test Circuit 7 0.µF Figure. I CCL Test Circuit V CC = 0V V CC = 0V 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

13 Test Circuit (Continued) IF V F = 0 to 0.V I F = 0mA 7 0.µF > V Figure. I FLH Test Circuit 7 0.µF Figure 7. V FHL Test Circuit 7 0.µF = V V CC = to 0V V CC = to 0V V or 0V V CC Ramp Figure. UVLO Test Circuit 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

14 Test Circuit (Continued) F = 0kHz DC = 0% V Probe I F UT Figure 9. t PHL, t PLH, t R and t F Test Circuit and Waveforms I F 0Ω A B t PLH t r 7 7 t PHL 0.µF t f 0.µF Rg = 0Ω Cg = 0nF 90% 0% 0% V CC = to 0V V CC = 0V V CM =,000V V CM 0V t H Switch at A: I F = 0mA L Switch at B: I F = 0mA Figure 0. CMR Test Circuit and Waveforms 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

15 Package Dimensions Through Hole SEATING PLANE 0.00 (.0) 0.0 (.) 0.0 (0.) 0.0 (0.) Surface Mount (9.9) 0.70 (9.0) 0.90 (9.9) 0.70 (9.0) (.) TYP 0.00 (.) TYP Lead Coplanarity : 0.00 (0.0) MAX PIN ID (.) 0.0 (.) (.7) 0.0 (.) 0. (.90) 0.0 (.0) 0.70 (.) 0.0 (.) 0.0 (0.) 0.0 (0.) PIN ID (.7) 0.0 (.) 0.00 (0.) MIN 0.00 (0.) MIN 0.0 (0.0) 0.00 (0.0) 0.00 (7.) TYP 0.0 [.] 0. (.00) MIN 0.0 (0.0) MAX. MAX 0.00 (7.) TYP 0.0 (0.) 0.00 (0.0) 0." Lead Spacing SEATING PLANE 0.00 (.0) 0.0 (.) 0.0 (0.) 0.0 (0.) -Pin DIP Land Pattern 0. (0.) (9.9) 0.70 (9.0) 0.00 (.) TYP 0.9 (7.9) PIN ID (.) 0.0 (.) (.7) 0.0 (.) 0. (.90) 0.0 (.0) 0.00 (0.0) MIN 0.0 (0.0) 0.00 (0.0) 0.00 (.) (.7) 0 to 0.00 (0.) TYP 0.00 (.) 0.00 (0.7) Note: All dimensions are in inches (millimeters) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

16 Ordering Information Part Number Package Packing Method FOD0 DIP -Pin Tube (0 units per tube) FOD0S SMT -Pin (Lead Bend) Tube (0 units per tube) FOD0SD SMT -Pin (Lead Bend) Tape and Reel (,000 units per reel) FOD0V DIP -Pin, IEC077-- option (Pending approval) Tube (0 units per tube) FOD0SV SMT -Pin (Lead Bend), IEC077-- option Tube (0 units per tube) (Pending approval) FOD0SDV SMT -Pin (Lead Bend), IEC077-- option Tape and Reel (,000 units per reel) (Pending approval) FOD0T DIP -Pin, 0. Lead Spacing Tube (0 units per tube) FOD0TV DIP -Pin, 0. Lead Spacing, IEC077-- option (Pending approval) Tube (0 units per tube) Marking Information Definitions V X 0 YY Fairchild logo Device number IEC077-- Option (only appears on component ordered with this option) (Pending approval) One digit year code, e.g., Two digit work week ranging from 0 to Assembly package code B 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

17 Carrier Tape Specifications D 0 P 0 P t K E 0 F A 0 W W B 0 d User Direction of Feed P D Symbol Description Dimension in mm W Tape Width.0 ± 0. t Tape Thickness 0.0 ± 0.0 P 0 Sprocket Hole Pitch.0 ± 0. D 0 Sprocket Hole Diameter. ± 0.0 E Sprocket Hole Location.7 ± 0.0 F Pocket Location 7. ± 0. P.0 ± 0. P Pocket Pitch.0 ± 0. A 0 Pocket Dimensions 0.0 ±0.0 B ±0.0 K 0.90 ±0.0 W Cover Tape Width. ± 0. d Cover Tape Thickness 0. max Max. Component Rotation or Tilt 0 R Min. Bending Radius 0 00 Fairchild Semiconductor Corporation FOD0 Rev..0. 7

18 Reflow Profile Temperature ( C) C peak Time (Minute) C, 00 s Time above C, <0 sec Ramp up = 0C/sec Peak reflow temperature: 0C (package surface temperature) Time of temperature higher than C for 0 seconds or less One time soldering reflow is recommended 00 Fairchild Semiconductor Corporation FOD0 Rev..0.

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