Sensors & Transducers Published by IFSA Publishing, S. L.,

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1 Sensors & Transducers Published by IFSA Publishing, S. L., Modeling Nanoscale FinFET Performance by a Neural Network Method 1 Jin He*, 1 Guoqing Hu, 1 Bing Xie, 1 Guangjin Ma, 2 Ping He, 3 Lei Song, 1 Chunlai Li, 1 Daye Lin, 1 Jingjing Liu, 1 Ying Yu, 1 Zhangyuan Chen and 1 Zhiping Zhou 1 Peking University Shenzhen SoC Key Laboratory, Shenzhen , China 2 Shenzhen Emperor Electronic Technology Co., Ltd, Nanshan District, Shenzhen518108, China 3 Shenzhen SuperD Co. Ltd, Huaqiaocheng, Nanshan District, Shenzhen , China Tel.: * frankhe@pku.edu.cn Received: 1 June 2017 /Accepted: 12 July 2017 /Published: 31 July 2017 Abstract: This paper presents a neural network method to model nanometer FinFET performance. The principle of this method is firstly introduced and its application in modeling DC and conductance characteristics of nanoscale FinFET transistor is demonstrated in detail. It is shown that this method does not need parameter extraction routine while its prediction of the transistor performance has a small relative error within 1 % compared with measured data, thus this new method is as accurate as the physics based surface potential model. Keywords: nanometer FinFET, compact modeling and simulation, network method, accuracy 1. Introduction With intensive downscaling of CMOS VLSI integrated circuits, traditional bulk device structure is approaching the practical limit imposed by gate tunneling and severe short channel effects (SCEs)[1], as channel lengths shrink to a few decananometres. In such case, the new material, new principle, and new struture semiconductor devices have been proposed to extend the CMOS industry generation to several nanometer size to support the information society life and performance. Among the proposed non-classical device structures, the double-gate MOSFET and FinFET, with very thin film body are strong contenders to replace the bulk MOSFETs due to superior short-channel-effect immunity, near-ideal sub-threshold slope, and low parasitic resistance and capacitance [2-6]. Following the ITRS prediction, the CMOS integrated circuit will soon approach 10 nm technology generation in two or three years[7], and the compact model for such nanoscale FinFET is highly required for the device optimization and circuit analysis. The traditional device models such as BSIM and PICM models use the threshold voltage method to construct the compact model framework. Such a model approach, however, is generally believed to be outdated due to the regional characteristics, too many fitting parameter which lead to complex parameter extraction routine, thus requires a paradigm shift in the core model structure. In this paper, we forsake the traditional method and develop a neural network method to model nanoscale FinFET transistor. When compared with the measured data, the accuracy of our model is satisfactory for the compact modeling application because the relative error is within 1%. We hope this new neural network 53

2 method can work well in next generation modeling of the FinFET design and circuit architecture [8]. 2. Neural Network Principle and its Back Propagation Algorithm We first describe the neural network structure to better understand what neural network is and why it has the ability to model nanoscale FinFET performance. We start the neural network from the external input-output-point-of-view, and also from the internal neuron information processing point-of-view. The most popularly used neural network structure is the multiplayer perception (MLP) as shown in Fig. 1. A typical neural network structure has two types of basic components, namely, the processing elements and interconnections between them. The processing elements are called neuron and the connections between the neurons are known as links or synapses. Every link has a corresponding weight parameter associated with it. Each neuron receives stimulus from other neurons connected to it, processes the information, and produced an output. Neurons that receive stimuli from outside network are called input neurons, while neurons whose outputs are used externally are called output neurons. Neurons that receive stimuli from other neurons and whose outputs are stimuli for other neurons in the network are known as hidden neurons. Different neural network framework can be constructed by using different type and amount of neurons and by connecting them differently. The type and amount determine the network scale and the connecting algorithm determines network efficiency and accuracy. In this paper, we used a so-called back propagation algorithm, which may be suitable for the nanoscale device modeling [9]. P. J. Werbos first depicted the back-propagation algorithm in his Ph.D. thesis [10]. It became widely used after it was rediscovered by Rumehlhart, Hinton, Williams, David Parker and Yann Le Cun [11]. Some research results prove that MLP feeding forward networks with arbitrary squashing functions can be approximated as a bore integrable function from one finite dimensional space to another finite dimensional space. Fig. 1 is a three-layer forward neural network, there are R neuron inputs, S 1, S 2 and S 3 neurons in the first, second and third layer, respectively. The output of one layer becomes the input to the following layer. the equation that describe this operation is as follows: a =f (w f (w f (w p+b )+b )+b ), (1) where f i, w i, b i denote the transfer function, the weight and bias matrix of the ith layer respectively. The working principle of the neural network shown in Fig. 1 includes two different stages: training and working. In the former stage, data is sent into the input layer of the network and transmitted to the output layer, then according to the error between network output data and the measure data, the network can update the parameters. The training process needs to be repeated until the error reaching below a defined value. The working stage use the trained network to predict the new input data, this can forward the input data to output layer and obtain the wanted result at once. The algorithm that is used to update the parameters in training stage is the steepest descent back programming algorithm [1, 7], however some disadvantages of this algorithm limits its action in practice. As an improved, the Levenberg-Marquardt algorithm is a variation of Newton s method that was designed for minimizing functions that are sums of squares of other nonlinear function, this algorithm is well suited to neural network training. The Levenberg- Marquardt algorithm [1, 5] is written as T -1 T X =X - (J (X )J(X )+μ I) J (X )V(X ), (k+1) k k k K k k (2) where X k is the weight or bias matrix of the Kth epoch of network, J(X k ) is the Jacobian matrix that contain first derivatives of the network errors with respect to the weights and biases, μ K is a variable parameter, I is the identity matrix, V(X k ) is a vector of network errors. 3. Neural Network to Model Nanoscale FinFET Here, we select a three-layer forward network, the network has 6 inputs parameters: drain-source voltage (V ds ), gate-source voltage (V gs ), bulk-source voltage (V bs ), length (L), width (W), and temperature (T). The network has 16,8,1 neurons in the first, second and third layer and the corresponding transfer function f 1, f 2, f 3 is hyperbolic tangent sigmoid, log-sigmoid and linear function, the output is the drain-source current. This network can model the transistor DC and AC characteristics of nanoscale FinFET. We firstly train the network with the measure data coming from 28 nm CMOS production process. Theoretically, we can use one data set to model transistor DC and AC characteristics if the data set has enough points in V ds and V gs range simultaneously. Unfortunately the data present does not satisfy this. Here we use two set training data show in Table 1 and Table 2 to model DC and AC characteristics, Table 1 for I ds -V ds and g ds -V ds characteristics, Table 2 for I ds -V gs and g ms -V gs characteristics. The training algorithm is the Levenberg-Marquardt algorithm. In training stage, after 300th epoch, the output of the network compared with the measure data, has only an relative error within 1 %. The corresponding result is shown in Figs. 2-5 and Figs

3 Fig. 1. Three layer forward network diagram. Table 1. Ids-Vds training data. Measure Parameters range Vds (V) 0.05:0.05:1.0 Vbs (V) -0.75, -0.5, 0 Vgs (V) 0.2:0.2:1.0 W/L(μm) 0.1/0.08,0.24/0.08,0.5/0.08,1/0.08, 0.12/0.09,0.12/0.1, 0.12/0.12, 2/0.24 T ( C) 25 Table 2. Ids-Vgs training data. Measure Parameters range Vds (V) 0.05:0.05:1.0 Vbs (V) -1, -0.5,0,0.25 Vgs (V) 0.0:0.05:1.0 W/L(μm) 0.1/0.08, 0.24/0.08, 0.5/0.08, 0.12/0.09, 0.12/0.1,0.12/0.12,2/0.24 T ( C) 25 Fig. 3. Comparison of the trained FinFET trans-conductance Fig. 2. Comparison of the trained FinFET transfer Fig. 4. Comparison of the trained FinFET transfer 55

4 Fig. 5. Comparison of the trained FinFET transfer performance with the measured data for the FinFET with 90 nm channel length. The dot is the measure data and the line is Fig. 6. Comparison of the trained FinFET transfer performance with the FinFET measured data for 50 nm Fig. 7. Comparison of the trained FinFET transfer performance with the FinFET measured data for 50 nm Fig. 8. Comparison of the trained FinFET trans-conductance performance with the FinFET measured data for 0.97 um Fig. 9. Comparison of the trained FinFET transfer performance with the measured data for the FinFET with 0.97 um 4. Conclusion In this paper we present a neural network method to model nanometer FinFET performance. The MLP neural network application in modeling nanometer FinFET is demonstrated in detail via the training and working processing. It is shown that the neural network method does not need extraction parameters while also having some other advantages: the characteristic curve can be differentiable from first order to infinite order in all transistor operation regions. 56

5 Acknowledgments This work is funded by National Natural Science Foundation of China under Grants ( ), by Fundamental Research Project of Shenzhen Sci. & Tech. Fund (JCYJ , JCYJ , JCYJ , JCYJ , JCYJ , JCYJ , JCYJ ), by Key technical project of Shenzhen Sci. & Tech. Fund (JSGG ). It is also supported by IER Funding of PKU-HKUST Shenzhen-Hong Kong Institution. References [1]. ITRS, International Technology Roadmap for Semiconductors [2]. Y. Taur, Xiaoping Liang, Wei Wang, and H. Lu, A continuous analytical drain-current model for doublegate MOSFETs, IEEE Electron Device Lett., Vol. 25, No. 2, 2004, pp [3]. A. Ortiz-Conde, F. J. G. Sánchez and J. Muci, Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs, Solid State Electronics, Vol. 49, No. 4, 2005, pp [4]. Jean-Michel Sallese, François Krummenacher, Fabien Prégaldiny, Christophe Lallement, A. Roy and C. Enz, A design oriented charge- based current model for symmetric DG MOSFET and its correlation with the EKV formalism, Solid-State Electronics, Vol. 49, No. 3, 2005, pp [5]. F. Prégaldiny, F. Krummenacher, J. M. Sallese, B. Diagne and C. Lallement, An explicit quasi-static charge-based compact model for symmetric DG MOSFET, in Proceedings of the NSTI Nanotechnology Conference and Trade Show, Vol. 3, 2006, p [6]. B. Diagne, F. Prégaldiny, C. Lallement, J. M. Sallese, F. Krummenacher, Explicit compact model for symmetric double-gate MOSFETs including solutions for small-geometry effects, Solid-State Electronics, Vol. 52, 2008, pp [7]. J. He, W. Bian, Y. Chen, B. Li, Y. Tao and Y. Wei, Carrier-based compact modeling of charge and capacitance of long channel undoped symmetric double-gate MOSFETs, Semicond. Sci. Technol., Vol. 23, No. 4, 2008, [8]. Martin Hagan, Howard B. Demuth, Mark H. Beale, Neural network design, PWS, [9]. J. He, G. Hu, B. Xie, G. Ma. A Neural Network Method to Model Nanoscale FinFET Performance, TechConnect Briefs 2017, pp19-22, ISBN [10]. P. J. Werbos, Beyond regression: new tools for prediction and analysis in the behavioral sciences, Ph. D. Dissertation, Harvard University, Cambridge, MA, [11]. D. E. Rumelhart, G. E. Hinton and R. J. Williams, learning representations by back propagating errors, Nature, Vol. 323, 1986, pp Published by International Frequency Sensor Association (IFSA) Publishing, S. L., 2017 ( 57