Strain Engineering for Future CMOS Technologies

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1 Strain Engineering for Future CMOS Technologies S. S. Mahato 1, T. K. Maiti 1, R. Arora 2, A. R. Saha 1, S. K. Sarkar 3 and C. K. Maiti 1 1 Dept. of Electronics and ECE, IIT, Kharagpur , India 2 Punjab Engineering College, Chandigarh, India 3 ETCE Department, Jadavpur University, Kolkata , India Corresponding author: satyamahato@yahoo.com Abstract- TCAD tools have been used to study the influence of both the uniaxial (process-induced) and biaxial (substrate-induced) strain on nanoscale MOSFETs down to 45 nm gate length. Processinduced stress has been introduced using SiGe, SiGeC, and SiC in the source/drain regions. Scalability of strained-si MOSFETs and SPICE parameter extraction by combining TCAD and BSIM3 model are presented for the first time. I. INTRODUCTION Strain engineering is being widely accepted as a promising technique to improve CMOS performance with significant mobility enhancement in 90 nm node and beyond. In recent years, substrate-and/or process-induced strained channels have successfully been integrated into MOSFETs in order to enhance carrier mobility [1, 2]. Until now, the substrateinduced biaxial strain has offered the best results for long channels (over 100% mobility enhancement). However, source/drain access resistances, saturation velocity, self-heating or strain relaxation has hindered the performance enhancements in nanoscale devices. The advantage of the uniaxial strain approach is that it can be engineered during the CMOS manufacturing. However, scalability and device geometry dependence are major concerns. The lateral dimensions of the transistors affect the efficiency and the strength of the induced strain. It has been shown that the introduction of a process-induced tensile stress in the Si channel can improve the mobility of both carrier types and increases the n- and p-mosfet drive current. The strain in the channel region can be obtained by the optimization of the stress introduced by the individual process steps and can as well be implemented by using strained-si substrates. The process-induced strain engineering needs to be taken into account at the transistor level and may limit the flexibility and add further complexity to transistor architectures. In this work, we investigate the effect of both the substrate- and process-induced strain in MOSFETs down to 45 nm gate lengths. A simulation study is performed to understand the strain distribution in the S/D regions of strainengineered MOSFETs by incorporating SiC, SiGe, and SiGeC films as stressors. SiC stressors are found to produce tensile strain in the channel (suitable for n-mosfets) and SiGe and SiGeC stressors produce compressive strain (suitable for p-mosfets).mobility enhancement in p- MOSFETs with SiGe source/drain is investigated as a function of Ge mole fraction. Scaling issues for strained-si MOSFETs are also discussed. II. PROCESS-INDUCED STRAIN ENGINEERING Towards strain engineering in MOSFETs, various stressors or stress inducing structures may be employed in the S/D regions in various ways. Relaxed SiGe buffer layer, as a bottom stressor in S/D, induce a compressive stress in the channel. Feasibility of introducing both the compressive and tensile strains simultaneously by using SiC and SiGe or SiGeC as stressor for the CMOS performance enhancement is shown. Finite element method (FEM) has been used in this study (via ANSYS simulator). Representative simulation results showing the stress distribution in the S/D regions are shown below. Simulated stress components for different types of stressors are shown in Table-1. Table.1 The stress components in channel for use of various type stressors in source and drain(s/d) region in MOSFET Stress in channel (Top8nm) GPa SiC SiGe SiGeC ε xx (along channel) ε yy (along channel)

Fig.1 shows the stress components (tensile) with SiC stressors which is applicable for n- MOSFETs. SiGeC stressors are found to produce more compressive stress than SiGe in the channel region.

2 Fig.1 shows the stress components (tensile) with SiC stressors which is applicable for n- MOSFETs. SiGeC stressors are found to produce more compressive stress than SiGe in the channel region. The stress distribution due to the application of SiGe and SiGeC stressors is shown in Figs. 2 and 3, respectively. The stress field in a transistor with the SiC source/drain stressors, distribution of stress components and the origin of the strain field in the transistor has been studied using ANSYS- FEM simulation. The impact of transistor design parameters, such as the carbon mole fraction x in the stressors, the spacing between stressors, the stressor depth, and the raised stressor height have been studied. Fig. 4 shows the profile of lateral strain component ε xx along a horizontal line from the source to drain at a depth 15 nm below the channel surface. The strain through out the channel is tensile and increases towards the top of the surface. Figure 1: Stress distribution using SiC stressors. Figure2: Stress distribution using SiGe stressors. Figure 4: Strain distribution from source to drain region. Therefore, for large value of ε xx near the channel surface where carrier transport takes place, producing significant change in carrier mobility and hence affect the drain current. Fig. 5 indicates that the increase in C mole fraction may increases both ε xx and ε yy for a fixed channel length. For a given mole fraction and stressor depth, with the decrease in channel length, both ε xx and ε yy are increases (Fig. 6). Figure 3: Stress distribution using SiGeC stressor. Figure 5: Increase of strain with increase of carbon mole fraction. Fig.7 shows variation of ε xx and ε yy with stressor depth. Reducing the inter-stressor spacing and increasing the C content and the recessed

$Figure 6: Increase of strain with decrease of channel length. Figure 8: Simulated stress (ε xx ) distribution in a p-mosfet with Ge mole fraction of 0.20.$

3 depth/raised height of the SiC stressors are three ways to achieve high strain levels in the Si channel region for drive current and enhanced electron mobility in n-channel MOSFETs. Figure 6: Increase of strain with decrease of channel length. Figure 8: Simulated stress (ε xx ) distribution in a p-mosfet with Ge mole fraction of Figure 7: Thick SiC stressor increases ε xx and ε yy. III. EFFECT OF Ge-CONTENT Depending on the Ge content, the shape of the SiGe source/drain is engineered to vary the compressive stress in the channel from 255 MPa to 1.8 GPa. It is shown that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Fig. 8 shows the simulated stress (ε xx ) distribution in a p-mosfet with Ge mole fraction of Fig. 9 shows the effect of enhancement in drive current (I d -V d ) due to Ge mole fraction increase. However, no saturation in the mobility enhancement is seen even at 1.8 GPa stress level. While it is expected that the valley occupancy and transverse mass improvement will saturate at high level splitting due to high Ge mole fraction, further improvements in the mobility can come from the suppression of scattering. Figure 9: Drive current (I d -V d ) enhancement in strain-engineered SiGe (S/D) p-mosfets. The strain in the channel region can be obtained by the optimization of the stress introduced by the individual process steps and can as well be implemented by using strained-si substrates. In the following, we investigate the effect of combining the substrate- and process-induced strain together in MOSFETs down to 45 nm gate lengths and show a performance enhancement of more than 62% with respect to conventional silicon MOSFETs. The influence of combining both the uniaxial (process-induced) and biaxial (substrate-induced) strain on nanoscale MOSFETs is shown in Figs.10 and 11.

4 Figure 10: Drive current (I d -V d ) enhancement in strain-engineered n-mosfets. Figure 11: Enhancement of gm in strainengineered n-mosfets. IV. SELF-HEATING EFFECT Hot carrier degradation due to self-heating of MOSFETs is an important reliability issue in deep sub-micron CMOS technology. Scaling and high performance requirements make the device channel length shrink continuously. It is known that with the operating voltage downscaling, devices will be in the stressed condition. The channel length scaling of conventional CMOS has reached its physical limit. It has been reported that short channel n-mosfets incorporating thin strained-si (on relaxed-sige) surface channels can achieve significant drive current enhancement. One of the major issues concerning strained-si transistors is the selfheating problem since thermal conductivities of the SiGe alloys are much smaller than that of bulk silicon. This is also evident from the rise in temperature in the device, obtained using ANSYS thermal simulation as shown in Fig.12. Figure 12: ANSYS simulated temperature rise in a strained-si MOSFET. BSIM3 is a physics-based analytical modeling tool and can predict MOSFET characteristics. We predict several important SPICE parameters of the substrate-induced strained-si devices including the self-heating effects and are given in Table-2. Name (Unit) Values VTH0(V) K1(V 0.5 ) K2(-) K3(-) W0(m) 2.50E-6 NLX(m) 1.74E-7 DVT2W(V -1 ) DVT0(-) DVT1(-) U0(cm 2 /Vs) KETA(V -1 ) RD(ohm/square) PRWD1(V -1 ) PRWD2(V -2 ) UD(-) VSATG(0+0.05V -1 ) Table. 2 Extracted device parameter (using SMART-SPICE) V. SCALING OF STRAINED-Si MOSFETS To cope with explosive development costs and competition in the semiconductor industry today, Technology Computer Aided Design (TCAD) methodologies are extensively being used in the development and production of advanced devices with heterostructure layers. In the following, process to device simulation of sub-90 nm strained-si MOSFETs is carried out to study the

scaling limit of strained-si MOSFETs. The ATHENA process simulation tool from SILVACO was used for the process simulation of scaled strained-si-mosfets.

ATHENA simulated device structure is shown in Fig.13. The calibrated I d -V d is shown in Fig.14 for a 90 nm device. Current gain (db) 90 70 50 30 10 W=1 µm -10 1.E+06 1 1.E+08 10 1.E+10 100 1.

5 scaling limit of strained-si MOSFETs. The ATHENA process simulation tool from SILVACO was used for the process simulation of scaled strained-si-mosfets. Typical Si- CMOS fabrication process steps, chosen from reference have been simulated. The simulated drain characteristics have been calibrated with the experimental data. ATHENA simulated device structure is shown in Fig.13. The calibrated I d -V d is shown in Fig.14 for a 90 nm device. Current gain (db) W=1 µm E E E E E+14 Frequency (GHz) FT0.5 = 41 GHz Lg=500 nm Lg=300 nm Lg= 90 nm Lg= 45 nm FT0.3 = 70.5 GHz FT0.1 = 105 GHz FT0.045 = 210 GHz Figure 15: Current gain vs. frequency plot. Figure 13: ATHENA simulated device structure. Drain current (µa) 3.E Symbols - DD simulation Leff=0.09 µm E E E-16 0 Solid lines (RED) - NEB simulation Solid lines (GREEN) - Experimental (Rim VLSI01) Drain voltage (V) Vg-Vt= V 0.6 V 0.4 V 0.2V Figure 14: Calibrated I d -V d, showing the usefulness of NEB model used in simulation. Fig.15 shows the simulated current gain vs. frequency plot with variable gate length for n- MOSFETs. For sub-45nm gate length MOSFETs, the cut-off frequency may reach 210 GHz which however, need to be experimentally verified. Towards circuit applications, for an inverter, the waveforms for inverting and non-inverting outputs are shown in Fig. 16. A comparison of circuit delay of strained-si CMOS inverters with variable gate length is also shown. Figure 16: Variation in circuit delay for the device simulated with different gate lengths. VI. CONCLUSION In conclusion, via simulation, the influence of both the uniaxial (process-induced) and biaxial (substrate-induced) strain on nanoscale MOSFETs is reported for the first time. Stress field in a transistor with SiGe, SiGeC, and SiC source/drain stressors was investigated and the origin of the strain field in the transistor channel was clarified. Strained-Si n-mosfet SPICE parameter prediction by combining TCAD and BSIM3 model is presented. Effect of Ge content and scaling issues of strained-si MOSFETs are discussed. Strained-Si n-mosfets in a standard Si-CMOS process were simulated down to 45 nm gate length to study the scalability. REFERENCES [1] C. K. Maiti and G. A. Armstrong, Applications of Silicon Germanium Heterostructure Devices, Inst. of Physics, UK, [2] S. E. Thompson et al., A logic nanotechnology featuring strained-silicon, IEEE Electron Dev. Lett., Vol. 24, (2004).

A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors

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