Chip and micro systems evolution

Transcription

1 New Emerging Technologies for Contactless Microsystems F. Vacherand - CEA-LETI soc-eusai 2005 October Grenoble New Emerging Technologies for Contactless Chips Chip and micro systems evolution Improved performances Very High Data Rates Non Volatile Memories High MIPS/low power Multi-Tag flow reading protocols New embedded functions for traceability and security Micro sensors Micro batteries Low cost process soc-eusai 2005 October Grenoble F. Vacherand 2

2 Introduction to contactless passive/active devices Basic Passive Contactless Overview No power on micro system Forward link communication: energy and data transmission Return link communication: passive load modulation Future Applications Requirements Very High Data Rates for Smart Cards Very Low Power RFID Electronic Tags Active tags for sensing and security BF POWER DATA Reader Tag/SC POWER Main applications Basic ID: Tags and Smart Cards Typical: Medical or industrial implants HF DATA soc-eusai 2005 October Grenoble F. Vacherand 3 Contactless µsystems : the low cost generation CONTACTLESS CHIP CORE Very Low Cost POWER ON RESET RECTIFICATION & SEQUENCER MEMORY ACCESS CONTROL RFID Ticketing STABILISATION CLOCK EXTRACTOR NON VOLATILE MEMORY DEMODULATOR MODULATOR DYNAMIC POWER MANAGEMENT STANDARD APPLICATION DEPENDENT BLOC soc-eusai 2005 October Grenoble F. Vacherand 4

3 Contactless µsystems : the secure generation CONTACTLESS CHIP CORE Low Cost POWER ON RESET RECTIFICATION & STABILISATION CLOCK EXTRACTOR SEQUENCER CRYPTO PROCESSOR MEMORY ACCESS CONTROL NON VOLATILE MEMORY & Secure RFID Ticketing Smart Card DEMODULATOR MODULATOR DYNAMIC POWER MANAGEMENT SECURITY MANAGEMENT DATA ACQUISITION ADC INTERNAL SENSOR STANDARD APPLICATION DEPENDENT BLOC soc-eusai 2005 October Grenoble F. Vacherand 5 Contactless µsystems : the active generation CONTACTLESS CHIP CORE High end & Secure POWER ON RESET RECTIFICATION & STABILISATION SEQUENCER MEMORY ACCESS CONTROL Traceability Med. Implant E-Purse Privacy CLOCK EXTRACTOR DATA PROCESSING NON VOLATILE MEMORY EXTERNAL OR INTERNAL DEMODULATOR CRYPTO & SECURITY MANAGEMENT MICRO-BATTERY MODULATOR DATA ACQUISITION EXTERNAL DYNAMIC POWER MANAGEMENT POWER MANAGEMENT ADC INTERNAL SENSOR MICROSENSOR OR MICROACTUATOR STANDARD APPLICATION DEPENDENT BLOC soc-eusai 2005 October Grenoble F. Vacherand 6

4 Very High Data Rate Interface Technical Goals : Break the 1Mbits/s barrier for Cless SC An ISO extension Scalable kbps: 106, 212, 424, and beyond Same antennas bandwidth for all data rates Low cost upgrade One bit to multi bit per symbol Multi-level modulations Reader Card : Multi level ASK modulation Card Reader : Multi phase PSK modulation on sub-carrier First step : Validation of reader and smart card chip air interface at 1.7Mb ps Technical proposal to standardisation committee soc-eusai 2005 October Grenoble F. Vacherand 7 Very High Data Rate Interface From PCD (reader) to PICC (card) Multi-levels Amplitude modulation on carrier frequency Mod. index 14% 0% T = 16/fc= 1,18µs Base band modulation to card 1,7 MHz fc amplitude Data rate = f (nb levels, T symbol) = log2(nb_level)/t fc = 13,56 MHz RF modulation T = 128 /fc (9,4 µs) T = 64 /fc (4,72 µs) T = 32 /fc (2,36 µs) T = 16 /fc (1,18 µs) 2 levels: levels: levels: levels: Mbps 106 kbits/s 212 kbits/s 318 kbits/s 424 kbits/s 212 kbits/s 424 kbits/s 636 kbits/s 848 kbits/s X 2 n 424 kbits/s 848 kbits/s 1271 kbits/s 1695 kbits/s 848 kbits/s 1695 kbits/s 2542 kbits/s 3390 kbits/s soc-eusai 2005 October Grenoble F. Vacherand 8

5 Very High Data Rate Interface From PICC (card) to PCD (reader) Multi-phases modulation on sub carrier frequency Sub-carrier phase Phase changing 3π/2 π π/2 0 fsc = 847KHz to reader 1,7 MHz fc = 13,56 MHz Data rates = f (nb phases, T symbol) = log2(nb_phases)/t 2 f : fs= 848 khz T = 2Ts 424 kbits/s (2,36 µs) T = 1Ts 848 kbits/s (1,18 µs) fs= 1,7MHz T = 2Ts (1,18 µs) 848 kbits/s T = 1Ts 1695 kbits/s (0,59 µs) 4 f : 2 2 (90 ) 848 kbits/s 1695 kbits/s 1695 kbits/s 3390 kbits/s 8 f : 2 3 (45 ) 16 f : 2 4 (23 ) 1271 kbits/s 1695 kbits/s 2543 kbits/s 3390 kbits/s 2542 kbits/s 3390 kbits/s 5085 kbits/s 6780 kbits/s 1.7 Mbps X 2 n soc-eusai 2005 October Grenoble F. Vacherand 9 Very High Data Rate Interface New demodulator architecture for chip receiver Delta modulator into analogue regulation loop Sigma-Delta converter for RX Classical architecture Open loop Magnetic field - Antenna Digital - Magnetic field Antenna New architecture Closed loop modulator Digital Σ analog Integrator Σ digital Digital output Clock soc-eusai 2005 October Grenoble F. Vacherand 10

6 Very High Data Rate Interface Comp JPEG PCD PICC Decomp JPEG Decomp JPEG PCD PICC Comp JPEG 25 Demonstrator for VHDR: Forward and return video transfer from 106 kbps up to 1,7 Mbps Air interface performances : H = 2,3 A/m and DR = 1,7 Mbits/s PCD to PICC link : BER = 10-7 PICC to PCD link : BER = Frames per second / data rates soc-eusai 2005 October Grenoble F. Vacherand 11 Non Volatile Memories Memories challenges for contactless Very fast write time (close to read time) Low power Large storage Secure Non Volatile Memory Families DIELECTRIC PHASE CHANGE MAGNETIC POLYMER MEMS Flash NOR NAND F-RAM ; SET PC-RAM M-RAM Molecular Mechanical Bi stable soc-eusai 2005 October Grenoble F. Vacherand 12

7 Non Volatile Memories: PC-RAM NVM : Phase Change RAM (from CD/DVD-RW optical disks) Phase -Change Alloy Material High Resistivity Change Very High Density Radiation Resistant > 2 ordersof magnitude : < 1KW 1MW > Source : RWTH Aachen data soc-eusai 2005 October Grenoble F. Vacherand 13 Non Volatile Memories: PC-RAM NVM : Phase Change RAM Ultra Fast RD/WR Very Low Programming Power Very Low RD/WR Voltage Amorphizing RESET Pulse current read voltage range Ird < 0.5mA Vrd # 0.4V programming current range voltage Vwr > Vth # 1V TA temperature Crystallizing SET Pulse RD / WR Time : 20 / ns Cycles count : > RD / WR Voltage : 0.4V / 1V No Charge Pump 30 ns 50 ns time Bit/Byte/Word Write Source : Intel Corp. soc-eusai 2005 October Grenoble F. Vacherand 14

8 Non Volatile Memories: CPU Evolution High RF ALU Crypto- Crypto- MMU SENSORS Speed ALU MMU SENSORS Processor RF Processor BUS BUS Cache L1 Cache L1 Cache L2 SECURITY UNIFIED NON VOLATILE MEMORY SECURITY ENERGY RAM ROM EEPROM FLASH TODAY : µp TOMORROW : µsoc Fast and Low power NVM for contactless CPU core Only one type of memory technology (few 10MHz) Flat memory for programming model soc-eusai 2005 October Grenoble F. Vacherand 15 High MIPS / Low Power Chip Technology : Silicon On Insulator TiSi 2 Gate TiSi 2 S G D TiSi 2 Silicon N+ P- N+ Burried Oxide Box SiO 2 Insulator layer Si RFID SOI chip RF front End & Supply Voltage Digital Low Power Low Voltage High Speed High Isolation soc-eusai 2005 October Grenoble F. Vacherand 16

9 MultiTag Reading & Anticollision Protocol Characteristics Determinist Algorithm Characteristics Known Duration: T read = f (Nb Tags, Code Length, Data rate) N-ary Tree Search Algorithms No Random Generator T0 T1 T2 T3 T4 Flow management Reader First In - First Read Tag (Timer Header + ID Code) Short Address for Fast Access (8bits for 256 tags) soc-eusai 2005 October Grenoble F. Vacherand 17 Micro-Sensors Accelerometer Gyro meter Magnetometer Pressure Low power sensors Capacitive High impedance Micro-packaging Micro-switch soc-eusai 2005 October Grenoble F. Vacherand 18

10 Permanent Active Data Monitoring Micro-system Global Power Management Embedded micro-battery (Continuous powering of secure functions) Thin film battery bloc (Temporary powering and back up) External powering Contactless powering Embedded battery back up blocs Low power clock Back up SRAM Managt. soc-eusai 2005 October Grenoble F. Vacherand 19 Above IC Micro battery Above IC Process Li Anode LIPON Solid electrolyte TiS x O y Cathode Current collector Substrat (Si) Above IC micro battery prototype soc-eusai 2005 October Grenoble F. Vacherand 20

11 Permanent Active Security : e-purse Global Power for Electronic Purse µ-battery Recharge External Thin Battery Contactless Power µ-power solutions Thin battery Thickness < 0.4mm Voltage > 2Volts Size 2.2 x 2.9 cm 2 Flexible Rechargeable < 3 mn Energy 20 mah Buttons LCD DISPLAY Thin Battery Recharge Contactless Power Above IC Micro-Battery Chip Energy management µbattery Thickness : 10 µm Capacity : 100 µah/cm² Discharge peak: 1 ma/cm 2 No internal discharge soc-eusai 2005 October Grenoble F. Vacherand 21 Permanent Active Security: Ultra LowPower Contact/contactless Global Power Management µbattery µbattery Charge Controller µbattery Discharge Monitoring MiniBattery Charge Controller MiniBattery Discharge Monitoring P o w e r Contactless Voltage Translator Coil Antenna External Mini Batter Back up RAM EEPROM Erase M U X Contact Real Time Clock Applications Low Power Functions Ultra Low Power Functions soc-eusai 2005 October Grenoble F. Vacherand 22

12 Permanent Active Security: dischargemonitoring Ultra low power voltage threshold monitoring VBAT Oscillator Signal shaping ACT Input VBAT Comparator D FlipFlop Output VREF Current reference Counter Comparator Latch bloc Current ref. Oscillator ACT signal Comparator Latch Total specs 1Hz Pulse rate: hour 1,6V +/-30mV power 2,4nA 0,49nA 0,42nA Active 16nA 0,1 na ~20nA Idle : 0,14 na ~4 na soc-eusai 2005 October Grenoble F. Vacherand 23 Polymer Electronics Printed polymer electronic Printing process On flexible foil Additive techniques Rotary press or Ink jet soc-eusai 2005 October Grenoble F. Vacherand 24

13 Polymer Electronics / cm2 Comparing processes Pentium IV Current Si RFID 1,E+01 IC Mono-Si < 0,5 µm >> 1 m 2 /h 1,E+00 Si TFT A-Si Poly-Si < 5 µm >> 10 m 2 /h 1,E-01 Polymer TFT Organic < 50 µm >> 100 m 1,E-02 2 /h 1,E+03 1,E+04 1,E+05 1,E+06 1,E+07 Targeted Polymer RFID Number of transistors per chip soc-eusai 2005 October Grenoble F. Vacherand 25 Conclusions Next step of road map RFID Evolution Basic Technologies Functions VHDR NVM HM/LP µsensors µbattery Fast transaction Traceability Security Privacy Process evolution Si Process impact Polymer priorities soc-eusai 2005 October Grenoble F. Vacherand 26

14 Thank you for your attention