Voltage/Current Measurement Performance and Power Supply Rejection in All-Digital Class-D Power Amplifiers

Transcription

1 016 IEEE Proceeding of the 4nd Annual Conference of the IEEE Indutrial Electronic Society (IECON 016), Florence, Italy, October 3-7, 016 Voltage/Current Meaurement Performance and Power Supply Rejection in All-Digital Cla-D Power Amplifier M. Mauerer, A. Tüyüz, J. W. Kolar Thi material i publihed in order to provide acce to reearch reult of the Power Electronic Sytem Laboratory / D-ITET / ETH Zurich. Internal or peronal ue of thi material i permitted. However, permiion to reprint/republih thi material for advertiing or promotional purpoe or for creating new collective work for reale or reditribution mut be obtained from the copyright holder. By chooing to view thi document, you agree to all proviion of the copyright law protecting it.

2 Voltage/Current Meaurement Performance and Power Supply Rejection in All-Digital Cla-D Power Amplifier M. Mauerer, A. Tüyüz and J.W. Kolar Power Electronic Sytem Laboratory, ETH Zürich, Switzerland Abtract Low-noie and low-ditortion voltage and current acquiition circuit, both analog and digital, are required for the control ytem of preciion, high-power witch-mode (Cla-D) amplifier ued in nanometer-accuracy mechatronic ytem. In thi paper, the achievable linearity and noie of analog ignal proceing element, uch a enor or active filter, i invetigated and their performance in a cloed-loop control ytem i demontrated. Reitive voltage divider are ufficiently linear but are ubject to reitor noie. Nonethele, a ignal-to-noie ratio (SNR) of 130 db i achievable. Shunt reitor can achieve a total harmonic ditortion (THD), limited by elf-heating, of < 10 db, wherea galvanically iolated, indutrial current enor achieve an inufficient THD of 90 db. High-order active op-amp filter, which are ued, e.g., to amplify and condition a hunt reitor voltage, can achieve a THD of 10 db. Furthermore, a a ubequent ignal digitization i required for the control ytem, it i hown how the SNR of analog-to-digital converter can be improved ufficiently for the dicued application by overampling, and how thi proce affect the feedback ytem phae margin. In order to reveal the performance of a cloed-loop ytem employing the key part of the ignal acquiition component, the reult of the enor analyi are implemented in a comprehenive computer imulation model of a digitally controlled witch-mode power amplifier. The analyzed 400 V, 500 VA converter ytem achieve a THD < 117 db and an SNR (DC-10 khz) >110 db while operating at witching frequencie up to 500 khz. I. INTRODUCTION Amplifier capable of providing high-preciion (i.e., lownoie and low-ditortion) voltage or current ignal at frequencie from DC to everal khz are ued in different application like medical imaging, robotic or mechatronic motion ytem for integrated circuit manufacturing. In the latter, uch amplifier drive ingle- and three-phae actuator like voice coil, magnetic bearing or linear permanent magnet ynchronou machine in emiconductor wafer poitioning or expoure procee with continuou output power of up to kva [1]. Their output ignal i a high-quality torque- (and hence, motion-) producing actuator current, i.e., with a ignal-to-noie ratio SNR > 100 db, and total harmonic ditortion THD < 110 db, at output current fundamental frequencie from DC to 50 Hz []. The ignal quality i critical in a bandwidth from DC to 10 khz, a the mechanical motion ytem provide ufficient attenuation at higher frequencie due to it inertia, which attenuate erroneou torque component. Currently, high-power preciion amplifier are often contructed in a hybrid fahion, where the low-quality, but highpower output of a witch-mode converter i improved by a low-power linear amplifier [3]. A uch etup are complex, u NH (t) Amplifier Control Non-Ideal Supply u u i S1 S 34 S 56 u I (t) Switching Stage Filter Preciion Senor Load Fig. 1: Switch-mode amplifier ytem providing a high-preciion output current for a three- or ingle-phae load. The cloed-loop control ytem attenuate diturbance uch a noie originating from the non-ideal power upply, or low-frequency harmonic generated in the witching tage. inefficient and the dynamic interaction between the witchmode and linear amplifier are difficult to tune, a purely witchmode and digitally controlled amplifier i deired. Fig. 1 illutrate a etup of a witch-mode amplifier providing a controlled output current to a three- or ingle-phae reitiveinductive load, a they occur in mechatronic ytem [1]. Apart from the illutrated buck-type topology, different witching tage topologie can be ued, uch a the dual buck topology, which can achieve lower harmonic ditortion []. The witching tage i upplied by a non-ideal voltage ource, which form the amplifier input voltage u I (t) and include a ource of different diturbing pectral component, u NH (t), and an inductive-reitive erie impedance. In order to attenuate unwanted pectral component originating from the non-ideal upply or other ource of ditortion in the amplifier output, feedback control i commonly employed. Therefore, different ytem tate (i.e., voltage and current) are meaured and a control law i applied. Naturally, both voltage and current meaurement mut provide the required performance in term of noie, linearity and bandwidth uch that the controlled ignal can achieve the deired pecification, a undeired component in the enor output cannot be compenated. In Section II, it i hown how meaurement circuit, uch a reitive voltage divider, hunt reitor and operational amplifier (op-amp) filter circuit can achieve ufficiently low ditortion and noie for the mentioned high-preciion application. Additionally, in digital control ytem, where the control law i executed at regular ampling intant and computed with quantized ignal, the meaurement mut be converted from the analog to the digital domain uing analog-to-digital converter (ADC) [4]. Such device have a limited amplitude reolution and hence, a limited SNR [5]. However, overam /16/$ IEEE 666

3 pling, a digital ignal proceing technique, can be employed to increae the SNR of an ADC, uch that it i ufficient for the dicued application. The main drawback of thi technique, which i an increaed ignal delay time, and it implication for the feedback loop performance of the control ytem, are invetigated. Section III focue pecifically on the linearity and noie of different type of current enor. Finally, in Section IV, a comprehenive computer imulation model of a digitally controlled amplifier, which alo incorporate the reult from the voltage and current enor analyi, i ued to demontrate the achievable power upply rejection and output ignal quality. Amplifier output voltage SNR figure in exce of 110 db and THD of le than 115 db are obtained. Section V preent a ummary and an outlook. Throughout thi work, the definition of THD and SNR are identical to the one preented in [] and [6]. II. VOLTAGE MEASUREMENT PERFORMANCE Voltage proceing circuit element (e.g., amplifier, filter or ADC) are key element to any feedback ytem. Thi ection analyze the noie and ditortion of analog voltage ening and filtering circuit a well a ADC. A. Voltage Sening Voltage ignal are commonly proceed with reitive divider or op-amp circuit. Reitive divider are ued to reduce a voltage to a lower level, e.g., to meaure a high-voltage ignal with low-voltage proceing circuit. If the power diipation of the reitor and hence their reitance variation i kept low (i.e., everal mw), uch divider can achieve a high linearity (cf. ec. III). However, reitor generate electrical noie, mainly thermal noie and exce/flicker noie, which limit the achievable SNR at the divider output [7]. Fig. exemplarily illutrate a frequency-compenated divider that allow to meaure voltage up to 400 V with 3.3 V circuit, a uch voltage level occur in the invetigated mechatronic amplifier. The divider achieve an SNR of 130 db (DC-10 khz) at it output and it linearity i enured by the low thermal diipation of 10 mw per reitor [7]. The parallel capacitor are ued to compenate paraitic capacitance uch that the divider achieve a flat frequency repone in a wide bandwidth [8]. U in 430 V U out 3. V 1. MΩ 1. MΩ 1. MΩ 1. MΩ 36 kω 100 pf 100 pf 100 pf 100 pf 3.3 nf Fig. : A compenated high-voltage divider with an SNR of 130 db and a maximum power lo of 10 mw per reitor. If analog voltage need to be amplified for further proceing, a it i, e.g., required for low (mv) voltage drop of current meaurement reitor, integrated op-amp are commonly ued. Their noie performance can generally be determined from their dataheet, contrary to their linearity, which depend on numerou factor uch a internal contruction, external circuit configuration or input and output impedance [7], [9]. Therefore, the linearity of different op-amp i evaluated experimentally. Fig. 3 (a) illutrate the utilized non-inverting amplifier circuit. The gain i fixed at G = 0 V/V. Note that the non-inverting configuration i more uceptible to introduce ditortion than the inverting configuration, a both op-amp input wing with the input ignal, which change the operating point of the opamp input tage, wherea in the inverting configuration, they are fixed at 0 V [10]. 511 Ω 511 Ω 10 kω 33 pf (a) 4.7 kω 750Ω 750Ω 5.6nF 360Ω 180pF 750Ω 750Ω.nF 360Ω (b) 470pF 60Ω 60Ω 1.8nF 300Ω 80pF Fig. 3: (a): Non-inverting amplifier circuit for comparing different op-amp. (b): 6 th order Butterworth filter with G = 1 V/V, f pa = 300 khz, f top =.5 MHz. A Stop = 100 db. Op-amp: AD860. Fig. 4 how the THD at the input and output of a election of ingle-ended preciion op-amp. Fully-differential amplifier are expected to perform even better [11]. For thi meaurement, a low-ditortion ignal generator a well a high-reolution pectrum analyzer i required [9], [1]. For amplifier input voltage V in < 0.3 V, a THD of the amplified ignal below 110 db can be achieved. Note that the output THD can be below the input THD in uch a meaurement, a two nonlinear ytem (the ignal generator and the amplifier) are connected in erie, i.e., the harmonic already preent in the input ignal can cancel the harmonic introduced by the nonlinearitie of the op-amp [9], [13]. THD Input AD797 AD860 AD8676 LT108 LT113 LT163 OPA87 LME V in (V RMS ) Fig. 4: Comparion of low-ditortion op-amp. Fig. 3 (a) illutrate the circuit. THD i meaured at the amplifier output and include the firt 5 harmonic. The input ignal i provided by a low-ditortion ine generator. The prominent increae in THD hown by ome op-amp at higher output level i due to limited op-amp output wing capabilitie. Signal ource and pectrum analyzer i a Rohde&Schwarz UPV. Op-amp circuit are alo ued in analog filter. Fig. 3 (b) exemplarily illutrate a 6 th order Butterworth low-pa filter implemented with a multi-feedback (MFB) filter topology. With regard to ditortion, the MFB topology i better uited than the alo widely ued Sallen-Key filter topology, a the op-amp are in the inverting configuration [10]. Such a filter can be ued a the analog anti-alia filter of an ADC, and hence, it hould add only little ditortion or noie to the ignal. Fig. 5 illutrate the THD and SNR at the input and output of the filter for different amplitude and frequencie. The filter add 5 db to the THD at it output over a wide operating range. On the other hand, the SNR i nearly identical at the input and output. 667

4 THD, SNR f Input THD v. V in SNR v. V in Output THD v. f SNR v. f V in (V RMS ) Fig. 5: THD and SNR at the output of the MFB low-pa filter (cf. Fig. 3 (b)). THD include the firt 9 harmonic and SNR i evaluated from 100 Hz to 0 khz. The frequency for the input voltage weep i 1 khz and the input RMS amplitude for the frequency weep i V. The plot line are lightly moothed uing pline interpolation. The decreae in SNR at 3.5 V i due to a range witch in the ource. The preented analye demontrate the performance with repect to linearity and noie of common analog voltage proceing element, which are alo required in conjunction with digital ignal proceing circuit (e.g., ADC anti-aliaing filter). In the following ection, the performance of ADC i invetigated. B. Digital Voltage Sening -to-digital converter quantize an analog voltage ignal to obtain a digital ignal with an amplitude reolution of m bit ( m quantization level) at a (contant) ampling rate f S. Due to the limited amplitude reolution, wideband quantization noie i added to the digitized ignal which limit it SNR [5], [6]. The SNR in a frequency band from DC to f S / of an amplitude quantized inuoidal digital ignal with a reolution of m bit can be approximated by [5] SNR = 6.0m db. (1) However, ADC device how SNR figure (SNR ADC ) wore than what eq. (1) ugget, due to additional noie ource and fabrication contraint of integrated circuit. Tab. I lit the THD and SNR of elected high-reolution ADC a tated in their dataheet. Part Bit m f S (MHz) THD SNR ADC SNR (eq.(1), db) ADS ADS AD AD AD TABLE I: Dataheet performance of elected preciion ADC. SNR i meaured from DC to f S/. Fig. 6 (a) and (b) illutrate the baic analog-to-digital converion ytem, whoe goal it i to replicate ignal in the frequency band from DC to f B (the baeband). It operate with a ampling rate f S = f NS, which i cloe to the Nyquit frequency of f B, and the reulting SNR i limited to SNR ADC. In order to prevent unwanted ignal component due to aliaing, an analog low-pa filter (LPF) with an attenuation A at f NS /, that exceed the ADC dynamic range, i placed at the input of the ADC [5]. The ampling frequency mut be lightly higher than f B uch that the anti-aliaing filter can roll off in the frequency interval from f B to f NS /. The quantization noie (due to the limited amplitude reolution of m bit) i evenly ditributed in a band from DC to f NS / (cf. eq. (1)) A 1 0 -A DC DC Low-Pa Filter Baeband Low-Pa Filter Baeband f B f B f NS Quantization Noie u in LPF f OS f S = f NS ADC u in LPF (a) (b) Decimation Downampling Filter m Bit n Bit LPF f f OS (c) (d) ADC Digital m Bit f NS f NS f S = f OS Fig. 6: Two ADC ampling trategie. (a): Nyquit-ampling with f NS. (b): Spectrum with Nyquit-ampling. (c): Overampling at f OS > f NS increae the reolution and lower the order of the analog filter. (d): Spectrum of an overampled ADC ytem. The quantization noie energy i pread over a wider bandwidth. If the SNR of a given ADC i inufficient, overampling, where f S i choen higher than neceary, can be employed to increae the meaured ignal SNR [5]. Fig. 6 (c) and (d) illutrate thi approach. A the ampling frequency f S = f OS i now higher, the energy of the quantization noie i pread over a larger bandwidth (from DC to f OS /) and hence, the SNR in the baeband increae. Furthermore, the analog lowpa filter can roll off in a wider band and can thu be of a maller order, requiring le component (e.g., op-amp), which reduce ignal ditortion and noie (cf. ec. II-A). However, a the ubequent proceing ytem till operate at the lower frequency f NS, which i, e.g., a power converter fixed PWM frequency, the ADC ampling frequency f OS mut be reduced (downampling). In order to achieve thi, the digital ignal mut be low-pa filtered by a decimation filter in order to prevent pectral aliaing component in the output ignal, before the ampling rate can be reduced [14]. Afterward, the digital ignal ha a higher reolution of n > m bit, that correpond to an increaed SNR OS, which, for an overampling ratio (OSR = f OS /f NS ), i given by SNR OS = SNR ADC + 10 log 10 (OSR) db, () which hold from DC to f OS /(OSR) = f NS / [5]. The diadvantage of the overampling technique i the phae lag introduced to the meaured ignal by the digital decimation filter, which, if it i part of a feedback loop, i detrimental for the loop tability margin. Thi phae lag i further invetigated in the following. f f 668

5 1) Digital Decimation Filter Delay: The digital decimation low-pa filter in an overampled ADC ytem, which, ideally, provide an attenuation of A > SNR OS at f OS /(OSR) in order to fully prevent aliaing, can how a coniderable phae lag [14]. Digital IIR filter are preferred for thi application a they can realize a given filter pecification with le tage than FIR filter and conequently, they how a maller phae lag, which, at low frequencie (i.e., in the baeband), increae nearly linear with frequency. Thu, in the following, their performance i aeed by the contant ignal delay T IIR correponding to thi linear phae. SNROS Bit, 5 MHz 16 Bit, 1 MHz 15 Bit, 5 MHz Butterworth Elliptic Chebyhev Type 1 Chebyhev Type Decimation Filter Delay T IIR (µ) Fig. 7: Overampled SNR and the delay of digital decimation filter for different (integer) OSR. The colored point are for a 16 Bit, 5 MHz ADC. The dahed line are the Pareto front of different ADC configuration. In Fig. 7, different digital IIR low-pa filter implementation, operating at different OSR, are compared with repect to their delay [14]. The amplitude reolution and ampling rate f OS of the overampled ytem are given by a certain ADC, e.g., 16 Bit and 5 MHz. Conequently, SNR OS can be evaluated according to eq. () for different OSR (different f NS ), with the aumption that SNR ADC follow eq. (1). The low-pa decimation filter mut provide an attenuation A top of at leat SNR OS at f top = f OS /(OSR). However, lower topband attenuation alo ufficiently uppre aliaing component [14]. For thi analyi, A top i fixed at 80 db. The paband frequency f pa i allowed to range from 0 khz to f top. In order to retrict the filter complexity, only filter order up to 30 are allowed. The paband ripple (where applicable) i et to db. The reulting filter delay T IIR i plotted for every viable filter configuration. Each plotted point in Fig. 7 correpond to a poible filter for a 16 bit, 5 MHz ADC, operating at different OSR. The Pareto front for thi ADC configuration, a well a for different ampling configuration a indicated, are plotted with dahed line. The analyi how how, with a riing OSR (and hence, a riing SNR OS ), the delay of the filter increae. The Chebyhev Type filter offer the bet performance while alo featuring no paband ripple [14]. Note that the reulting filter complexitie are coniderable, with order up to 30, and thu require digital proceing ytem that are capable of implementing uch filter (e.g., FPGA). In ec. IV, the filter delay a invetigated here are conidered in the analyi of a feedback ytem, which reveal the impact on the feedback loop performance. III. CURRENT MEASUREMENT PERFORMANCE Thi ection analyze the linearity and noie of different type of current enor a they are commonly ued in power electronic converter. A hunt reitor provide a imple mean of meauring a current, a the voltage drop acro it i, ideally, proportional to the reitor current i S. However, a the reitance R S i nonzero and many reitive material how a temperature dependence of R S, the hunt voltage u S = R S i S i a function of the aociated momentary thermal lo p(t) = R S i S (t), a it alter the hunt temperature T S [15]. Conequently, the reitor linearity depend mainly on the temperature coefficient α, i.e., R S = R nom (1+α(T S T a )), with T a being the ambient temperature, a well a the thermal impedance Z S of the reitor, which define it temperature in dependence of the momentary thermal power lo p(t): T S = Z S p(t) + T a. Uing thi et of equation, the hunt voltage u S = R S i S i R nom i S (t) u S (t) = 1 αr nom Z S i (3) S (t). If a inuoidal current i S (t) = î in(ωt) i aumed, then the THD of u S can be numerically derived from eq. (3). Uing Z S = K W 1, α = e 6, R nom = 10 mω and î = 10 A, which are value achieved by commercial hunt reitor [16], the reulting THD of u S i 10 db. A lower value for R nom further improve the THD. However, ubequent amplifier ued to proce u S then require more gain which could reult in more ditortion originating from thee circuit. Note that α and Z S are uually not contant, a they can alo vary with temperature and time. Nonethele, thi analyi how that hunt reitor can provide a ufficiently high linearity in current range up to 10 A, a it i required for the invetigated mechatronic current amplifier. If a galvanically iolated current meaurement i required, commonly ued enor, which provide an output voltage or current ignal and frequently include integrated proceing electronic, often rely on magnetic effect [17]. Unfortunately, there i typically no ditortion data of uch enor available and hence, a preciion current ource i ued in the following to invetigate the THD of different type of galvanically iolated current enor, a lited in Tab. II. Nr. Technology Output Type I nom (A RMS ) f BW Linearity (% I nom) 1 AMR, CL Voltage ±0.1 AMR, CL Current ±0. 3 Hall, OL Voltage 0 50 ±1 4 Hall, CL Voltage < Hall, CL Current 5 00 < 0. 6 Fluxgate, CL Current ± TABLE II: Galvanically iolated current enor with different ening principle uch a the aniotropic magnetoreitive effect (AMR) or open/cloed-loop (OL/CL) circuit involving Hall enor. The fluxgate principle excite a magnetic core and utilize it aturation in combination with a compenation principle [17]. f BW i the enor bandwidth. Linearity i the integral nonlinearity error, i.e., the max. deviation from the ideal tranfer curve. Fig. 8 depict the chematic of the low-ditortion current ource. An indutrial voltage amplifier (AE Techron 74) i 669

6 ued to drive the reference current i Ref. A feedback ytem, compoed of a reference hunt R Ref (Burter 18, 10 mω) and a Type-III (lead-lag) compenator, i ued to attenuate harmonic in i Ref originating from the non-ideal power amplifier. R L i ued to bia the power amplifier into a uitable operating point (i.e., table and low harmonic). The low-ditortion reference ignal u Ref i provided by the high-preciion meaurement ytem, which i alo ued to analyze the amplified hunt voltage u S,A and the current enor output voltage u Sen [1]. 100p 750Ω 4.7kΩ FFT u Ref U 1 u S,A 1n 330p 40Ω U 10kΩ G=0 V/V PA.5Ω 511Ω i Ref u S R L Senor R Ref u Sen Fig. 8: Preciion current ource. U 1 operate a a Type-III compenator. U provide the amplified feedback ignal u S,A. All op-amp are LT108A. Fig. 9 illutrate the THD (firt 4 harmonic) and SNR (100 Hz-0 khz) of the different enor output voltage (u Sen ) a a function of the meaured current, at a fundamental frequency of 35 Hz. The meaurement how that the invetigated current enor can only achieve a THD of 90 db, wherea their output noie i alo ignificantly increaed. The ame current ource wa alo ued to invetigate hunt reitor. A expected, no increae in THD or SNR in the hunt output voltage can be oberved. Conequently, if current are to be meaured with low enor-induced ditortion, a required by the dicued mechatronic application, hunt reitor deliver a uperior performance over integrated, galvanically iolated enor. In the following, the obtained reult from the voltage and current enor analyi are incorporated in a imulation of a controlled converter ytem to invetigate the overall achievable converter output noie and ditortion. THD, SNR i Ref (A RMS ) u S,A 1-AMR,CL 4-Hall,CL THD -AMR,CL 5-Hall,CL SNR 3-Hall,OL 6-Fluxgate,CL Fig. 9: THD and -SNR of different galvanically iolated current enor a lited in Tab. II. A low-ditortion current ource (cf. Fig. 8) upplie the reference current (meaured a u S,A). FFT IV. POWER SUPPLY REJECTION AND CLOSED-LOOP PERFORMANCE The upply of a power amplifier i uually not ideal, a there i often wideband noie or grid harmonic preent in the upply voltage pectrum. Additionally, there i a erie impedance, which caue a current dependency of the upply voltage u I (t). The amplifier i required to ufficiently attenuate any upply ditortion component at it output, and, in order to avoid harmonic ditortion, it mut compenate for a drooping upply voltage []. Preciion amplifier often conit of a combination of a witch-mode power converter and a linear amplifier. Such hybrid concept benefit from the high efficiency of the witchmode converter, wherea the output quality i improved by the linear amplifier. There are different circuit topologie of hybrid amplifier [3], [18]. Fig. 10 (a) illutrate a hybrid amplifier tructure which deliver a preciion output current. The non-ideal upply of the witch-mode amplifier i modelled a an ideal voltage ource in erie with a voltage ource u NH (t) that upplie noie and different unwanted pectral component uch a grid harmonic, and a reitive-inductive erie impedance. The linear amplifier i ued, together with a preciion current enor, to attenuate the ripple and other unwanted component in the output current i O. A the witch-mode tage deliver the mot output current, the linear amplifier can operate at a lower power level. Thi facilitate the deign of a low-noie power upply U A for the linear power amplifier. If the witch-mode converter already deliver an output of ufficiently high performance, the hybrid approach depicted in Fig. 10 (b) can be employed [19]. Here, the linear amplifier imply provide a tabilized upply voltage U S for the witch-mode power amplifier. (a) (b) u NH (t) u NH (t) u I (t) Non-Ideal Supply u I (t) U A CTRL i R (t) i C (t) LA CTRL U S u C (t) LA i O (t) SMPA i O (t) Fig. 10: Two hybrid amplifier tructure. (a): The linear power amplifier attenuate undeired current component in the output current. (b): The linear power amplifier provide a tabilized, low-noie upply voltage U S for the preciion witch-mode power amplifier. Linear power amplifier (together with analog control) can achieve a high loop gain over a wide bandwidth which make them well uited to attenuate ditortion component. However, their efficiency i limited and conequently, their uage i retricted to low output power [3]. Furthermore, the combined action of the control ytem of the witch-mode amplifier and the linear tage mut be well tuned in order to enure control tability over a wide operating range [0]. Conequently, thi work propoe the ue of only witchmode converion tage. Fig. 11 illutrate a poible concept, in which a witch-mode upply filter provide a tabilized and adjutable upply voltage U S for the witch-mode amplifier, U A U A 670

7 u NH (t) u I (t) Switched-Mode Supply Filter U S Switched-Mode Power Amplifier i O (t) Fig. 11: A preciion witch-mode converter provide a tabilized, filtered upply voltage U S for the witch-mode power amplifier which deliver the preciion output current i O(t). which provide the high-preciion output current i O. Uing thi approach, the upply voltage of the power amplifier can be varied and hence, it performance can be adapted for different operating condition, e.g., if high output dynamic are required, U S can be increaed wherea the remaining witching component in i O (t) can be reduced by lowering U S. However, depending on the application, the witch-mode amplifier tage alone could provide ufficient power upply rejection and dynamic performance and thu, the witch-mode upply filter converter would not be required. Due to the advent of WBG emiconductor, epecially gallium nitride (GaN) enhancement FET [1], which enable high witching frequencie and thu high controller ampling rate, the control ytem of witched converter can achieve the deired performance, a hown in the following. If a (voltage/current) controller croover frequency of 5 khz... 0 khz i targeted for a mechatronic amplifier, the ampling rate of the control ytem, which i the converter witching frequency f PWM, mut be 100 khz khz in order to achieve a high control performance [4]. In order to demontrate the feaibility of thi power upply rejection approach, a detailed circuit imulation model of a low-noie and low-ditortion witch-mode amplifier ha been developed. The imulation ytem alo incorporate realitic ening technology model a they were invetigated in the foregoing ection in order to reveal achievable performance figure of the dicued amplifier. A. Digitally Controlled Converter Performance A circuit imulation i ued which model a realitic witching tage a well a the digital controller and important non-idealitie and noie ource []. Fig. 1 illutrate the imulation etup and the propoed control tructure, compoed of two cacaded controller, which i expected to deliver a high performance [3]. The ytem i operated a a DC to AC converter, which allow the aement of the harmonic ditortion contribution originating from the witching tage of the converter, which i not poible for a DC output. Tab. III lit the configuration of the imulation model. For the power tage, a conventional buck converter i ued, although thi topology i expected to generate a coniderable amount of harmonic due to the dead time interval required when changing the witching tate of the two tranitor (T 1, T ) to prevent a bridge leg hoot-through []. Nonethele, it i employed here in order to demontrate the ditortion attenuation capability of the control ytem. In order to reduce the complexity of the imulation model, only a ingle-phae ytem with one witching leg i conidered, wherea a inglephae load i uually connected to two witching leg in order u Ref (t) + TIII u-ctrl h f PWM h f f OS Feedforward f + Lead i-ctrl NS+PWM Decimation u NH (t) Digital LP Digital g LP f OS m ADC Dit. + ADC Noie Dit. + ADC m ADC T 1 T C DS u O (t) / 0 R LF L F i F R L CLF C DS C F R ESR LP LP Fig. 1: Simulation model block diagram. The ADC, the analog and digital filter, a well a the time-dicrete controller are modelled in detail and include important noie and ditortion ource. to increae the available voltage at the load and to reduce power upply interaction [4]. In thi analyi, the econd half-bridge i modeled a a contant voltage ource /. The voltage and current meaurement ADC have a reolution of 16 bit and are operated uing overampling in order to increae their SNR. Noie of uniformal pectral ditribution i added at the ADC output uch that it matche the noie level of the AD7961 (SNR ADC = 95.5 db). Additionally, ditortion i created at the output of the ADC with a function y = 1x + A 3 x 3, with the coefficient A 3 deigned uch that a THD of 116 db (at full cale input) reult, a it i the cae with the conidered ADC (AD7961). A hown in ec. II and III, hunt reitor, voltage divider and active analog filter can achieve a higher THD than the ADC and are thu conidered a ideally linear. The analog low-pa anti-aliaing filter and the digital decimation filter are implemented in the digital imulation uing the IIR filter topology and econdorder-ection, in order to enure their numerical tability [14]. The analog anti-aliaing filter i a Butterworth filter with a pa band frequency f p,aa elected a high a poible in order to minimize it phae delay, but with the filter order being fixed to 6, uch that the complexity of the analog filter (and thu, it ditortion and noie) i limited (cf. ec. II-A). The top band attenuation i 98 db and the top band frequency i f S,ADC /. The digital decimation filter i a Chebyhev Type filter and elected according to the optima for each OSR a derived in Fig. 7, i.e., with the pa band frequency f p,dec a high a poible in order to minimize T IIR, without exceeding the maximum filter order of 30. The lower top band frequency of thi filter i f S,ADC /(OSR) and the top band attenuation i fixed to 80 db. The digital noie haper tructure a decribed in [6] i employed in order to achieve a high PWM ignal SNR with the given f PWM, while limiting digital PWM counter frequencie to 50 MHz, a thi frequency i contrained by digital logic. Thi noie haper i, depite uing a low-reolution PWM modulator, capable of generating high-snr modulation ignal in the baeband (DC-10 khz). The witching tranitor are modeled with a contant drainource capacitance C DS, a contant channel reitance R DS,on and a body diode forward drop of 3 V, which can be expected from GaN tranitor []. For implicity, the gate driver are aumed ideal, i.e., the witche turn on and off ideally fat (note that the drain-ource capacitance C DS nonethele enure u O t 671

8 Parameter Value RDS,on uf CDS HEMT channel reitance HEMT body diode fwd. drop HEMT drain-ource capacitance TD Half-bridge dead time RLF Serie reitance of LF CLF Paraitic capacitance of LF CF Filter capacitor RESR Serie reitance of CF UDC DC-link voltage unh (t) Noie and harmonic ource ZI Supply erie impedance uref (t) Output voltage reference RL Load reitance madc ADC reolution SNR ADC ADC SNR, from AD7961 THD ADC ADC THD, from AD7961 uadc Voltage ADC range iadc Current ADC range 80 mω 3V 100 pf Amplitude (dbv) Name 50 n 50 mω 100 pf 7 µf 0 mω 400 V See text. 0.1 Ω nh UDC +0.8 UDC in(π40t) 30 Ω 16 Bit 95.5 db 116 db 0V...430V 50A...50A uo Supply e+03 1e+04 Frequency (Hz) 1e+05 1e+06 Fig. 13: Voltage pectra of the upply (UDC + unh (t)), including wideband noie and different pectral pur, and the amplifier output. Switching frequency fpwm = 500 khz, ADC ampling rate fs,adc = 5 MHz. SNR = 110. db, THD = db. (5) to the SNR, except that the power of the harmonic i alo conidered [5]. Fig. 13 alo illutrate the pectrum of the amplifier output for fpwm = 500 khz and fs,adc = 5 MHz. It how that the pectral component and noie originating from the upply are ignificantly attenuated (A > 40 db) by the converter and only the harmonic of the fundamental remain. The enitivity of the amplifier output to the upply voltage could be even further ameliorated by meauring the upply voltage and uing it a a feedforward term for the control ytem [6]. The reult how that overampling improve the amplifier output noie, a the SNR of the enor i improved. Furthermore, an increaed witching frequency enable a higher voltage controller open-loop croover frequency fc,u (frequency where the open-loop gain become 0 db), which allow a better attenuation of diturbing harmonic and noie by the feedback ytem. Depite uing an inferior converter topology (conventional buck converter intead of a dual buck converter), the remaining noie and ditortion at the amplifier output i compellingly attenuated by the digital feedback ytem. In thi analyi, the pectrum of the output voltage at a reitive load i invetigated. If thi output voltage were applied to a reitive-inductive load, a they are common for mechatronic actuator, noie and ditortion in the output current would be even lower, due to the increaing load impedance with frequency. Although the imulation are performed with an output power of <500 VA, the addition of a econd witching leg, a it i uually done for ingle-phae load, will double the achievable load voltage. Furthermore, by interleaving everal witching leg and operating them with a phae-hifted modulation carrier, the output power, a well a the effective output ripple frequency, can be further increaed [5]. The upply conit of a erie-connection of an ideal voltage ource UDC = 400 V and a ource unh (t) which provide wideband noie and other pectral component. The pectrum of unh (t) i modeled to repreent the pectra of different witch-mode laboratory upplie with output power of 1 kw to 10 kw. It pectrum i illutrated in Fig. 13. Tab. IV lit individual imulation configuration and their reult. Apart from the THD and SNR, the ignal-to-noieand-ditortion-ratio (SINAD) i alo provided, which i imilar V. C ONCLUSION & O UTLOOK Thi paper reveal the noie and ditortion performance of voltage and current acquiition element, both analog and digital, a they are important for the feedback control ytem of low-noie and low-ditortion power amplifier ued in mechatronic application. It i hown how reitive high-voltage (400 V) divider, a well a analog amplifier and active filter employing operational amplifier, can achieve very low noie and ditortion TABLE III: Circuit imulation etup. Thee value are identical in all imulation. The tranitor are modelled after E-mode GaN HEMT. a nonzero tranition time of the witched half-bridge voltage). In order to realize high fpwm and thu alo high controller execution frequencie, the output power i et to 500 W, which i expected to allow witching frequencie up to everal hundred khz without exceive tranitor witching loe [1]. The output filter capacitance CF i choen uch that the power factor at the half-bridge output i λ > 0.98, wherea the output filter inductance value LF i deigned uch that the maximum current ripple (peak-peak) in the inductor i 10 % of the RMS output current of 4. A (cf. Tab. III). Electromagnetic interference i not conidered in thi imulation. A econd filter tage would be required to further provide high-frequency attenuation. Two cacaded controller are utilized (cf. Fig. 1). For the current controller, a lead compenator i ued (cf. eq. (4)), wherea the output voltage uo i controlled by a Type-III (leadlag) compenator (cf. eq. (5)). Both controller are tuned to provide a phae margin of at leat 50 and a gain margin of more than 7 db. They are implemented a time-dicrete controller and executed with fpwm. The reference output voltage and the meaured output voltage are ued a feedforward term to improve the controller dynamic behavior [5]. GLead = ADC GTIII = 1+ ωz ωp1 )(1 + (1 + ωl )(1 + ADC (1 + ωp1 )(1 + (1 + ωp ) ωz ) ωp ) (4) 67

9 Powered by TCPDF ( f PWM f S,ADC (MHz) OSR () n PWM (Bit) L F (µh) f p,aa f p,dec T IIR (µ) f c,u THD SNR SINAD n/a TABLE IV: Simulation reult. SNR and SINAD are meaured from DC to 10 khz and the THD conider the firt 5 harmonic. figure. It i demontrated that a 6 th order analog anti-alia filter can how a THD < 10 db. A high-preciion current ource i ued to invetigate the performance of different type of galvanically iolated, indutrial current enor, both in term of noie and ditortion. The bet achieved THD i 90 db, which i inufficient for the dicued application. Therefore, hunt reitor, which can provide a very low-ditortion (THD < 10 db) and low-noie current meaurement, are preferred. Furthermore, by employing overampling, the SNR of ADC can be ufficiently increaed and enable digital control in ultra low-noie application. Finally, thee reult are incorporated in an extenive computer imulation model which employ all main nonlinearitie and noie ource, in order to demontrate the feaibility and performance of a digitally controlled, witch-mode power amplifier operating with a non-ideal upply. The preented ytem achieve a high power upply rejection ratio (> 40 db), and, depite uing an inferior witching tage topology (conventional buck converter), the reulting output voltage THD i below 117 db at output power of 500 W. Voltage SNR figure in exce of 110 db are alo achieved. The ue of an interleaved topology can increae the output power a well a the effective witching frequency, leading to a more dynamic ytem behavior. In ummary, baed on the propoed digitally controlled witch-mode amplifier, it i hown how low ditortion, low noie and a high power upply rejection can be achieved. Thi obviate more complex hybrid amplifier topologie, leading to more efficient and cot-effective olution. A hardware demontrator will be ued for verification in ubequent reearch work. REFERENCES [1] R. Munnig Schmidt, G. Schitter and J. van Eijk, The Deign of High Performance Mechatronic. Delft Univerity Pre, 011. [] M. Mauerer, A. Tüyüz and J.W. Kolar, Ditortion Analyi of Low- THD/High-Bandwidth GaN/SiC Cla-D Amplifier Power Stage, in Proc. of the Energy Converion Congre and Expoition (ECCE), Sept 015, pp [3] G. Gong, Hybrid Amplifier for AC Power Source Application, PhD Thei, ETH Zurich, Di. No , 009. [4] G.F. Franklin, J.D. Powell and M.L. Workman, Digital Control of Dynamic Sytem. Addion-Weley, 1998, ISBN: [5] W. Keter, The Data Converion Handbook. Elevier, 005, ISBN: [6] M. Mauerer, A. Tüyüz and J.W. Kolar, Gate Signal Jitter Elimination and Noie Shaping Modulation for High-SNR Cla-D Power Amplifier, in Proc. of the Applied Power Electronic Conference (APEC), March 016. [7] C.D. Motchenbacher and J.A. Connelly, Low-Noie Electronic Sytem Deign. Wiley, 1993, ISBN: [8] A. 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