Implementation of a Current-to-voltage Converter with a Wide Dynamic Range

Transcription

1 Journal of the Korean Physical Society, Vol. 56, No. 3, March 2010, pp Implementation of a Current-to-voltage Converter with a Wide Dynamic Range Jae-Hyoun Park and Hyung-Do Yoon Korea Electronics Technology Institute, Seongnam (Received 17 July 2009, in final form 30 September 2009) A current-to-voltage converter (IVC) that has a wide dynamic range and good linearity is described. The proposed IVC is designed and fabricated using 0.35-µm, 3.3 V complementary metaloxide-semiconductor (CMOS) technology. The IVC consists of one transimpedance amplifier (TIA) and two analog-to-digital converters (ADCs). One converter is a higher-bit ADC, and the other is a lower-bit ADC. The higher-bit ADC with N-bit resolution not only determines the upper N bits of the IVC but also generates an adjusting current that is subtracted from an input signal current. With this subtraction, the input signal current can be shifted into the linear operating region of the TIA used. Then, the output voltage of the TIA can be converted by using the lower-bit ADC, which determines the lower bits of the IVC. In the current-to-voltage conversion, this two-step conversion makes it possible for the maximum input current to be enlarged by 2 N times and the dynamic range to be widened by 6N. PACS numbers: Le, e, Qx Keywords: Current-to-voltage converter, Dynamic range, Linearity, Transimpedance amplifier, Two-step conversion DOI: /jkps I. INTRODUCTION In current sensing systems, such as amperometric sensors, a current-to-voltage converter (IVC) is a core building block. An efficient IVC should, therefore, be realized to achieve good performance of the overall sensing system [1 7]. There are specific requirements for an IVC, including low noise, wide dynamic range (DR), linearity, high speed, low power dissipation, stable sensor bias control, and small occupation area [1 4]. Especially, in photodetector applications, a wide DR is often required because the optical intensity has an enormous DR from a moonless night to the glaring sun. For example, the human vision system exhibits an optical DR of about 200 db, but charge coupled devices (CCDs), which represent artificial imagers, exhibit a DR of only about db [8]. Therefore, there is a great deal of on-going research to expand the linear region or to widen the DR [1,8-11]. Generally, current-to-voltage conversion can be performed using a charge accumulation process and the exponential current-voltage (I-V) characteristics of metal-oxide-semiconductor (MOS) transistors. These are caused by the diffusion current, which is a major term in the sub-threshold region [9]. The former has good linearity in signal conversion, but this method requires a linear capacitor and causes a signal delay [2,3,6]. The jhpark@keti.re.kr; Fax: latter has a good conversion speed and a wide DR, but the signal conversion is non-linear or logarithmic [1,3,7]. In contrast to this, we present a complementary metaloxide-semiconductor (CMOS) integrated IVC with a novel conversion algorithm that can achieve both a wide DR and a good linearity in signal conversion. The proposed IVC consists of a trans-impedance amplifier (TIA) and two analog-to-digital converters (ADCs) and can expand the DR by means of iteratively using the linear I-V conversion region of the TIA in order to cover the entire input current range for the TIA with a good linearity, but without a wide DR. The IVC was designed and fabricated using SMIC 0.35-µm, 3.3-V CMOS technology. II. CIRCUIT DESIGN The main algorithm of the proposed IVC is a two-step conversion using one TIA and two ADCs. One converter is a higher-bit ADC and the other is a lower-bit ADC. A signal flow diagram of this two-step conversion algorithm is shown in Fig. 1. The operational procedure is as follows: When a specified maximum input signal current of the IVC is out of the linear input range of the TIA used, the maximum input current can be divided equally into 2 N current blocks, where N is the resolution of the designed higher-bit ADC. The current range of each current block should be smaller than the linear input range -863-

2 -864- Journal of the Korean Physical Society, Vol. 56, No. 3, March 2010 Fig. 2. Generation of the adjusting current by using the higher-bit ADC with two-bit resolution. Fig. 1. Signal flow diagram of the proposed two-step current-to-voltage conversion algorithm. of the TIA used. Let us assume that an arbitrary input current of the IVC is larger than the linear input range of the TIA and is located in a certain current block. In the first step of the conversion, an output voltage of the TIA corresponding to the input current of the IVC should be converted to digital outputs by the higher-bit ADC. An adjusting current can be generated using these digital outputs, a more detailed explanation of which will appear in the following paragraph. The higher-bit ADC output should be latched in internal memories in order to keep information about the originally placed block of the input current. In the second step of the conversion, the input signal current can be shifted to the linear region of the TIA by means of subtracting the generated adjusting current from the input signal current. The TIA converts the resulting current to the second output voltage, which is the input voltage of the lower-bit ADC. Finally, the digital outputs of the overall IVC comprise the upper bits converted by the higher-bit ADC and the lower bits converted by the lower-bit ADC. A circuit diagram for generating the adjusting current using the flash-type higher-bit ADC is shown in Fig. 2. The higher-bit ADC has several comparators, and each comparator has its own reference voltage. The reference voltage of the first comparator is set to the TIA output voltage corresponding to the reference current I ref, which is the maximum current of the first block. Other reference voltages are set using an almost identical method. If these reference voltages are to be determined exactly, a characteristic curve of the designed TIA should be obtained. A thermometer code consists of each comparator s output and is used to calculate the adjusting current. That is, the adjusting current is k times the reference current, where k is the number of ones in the thermometer code. In practice, many TIAs can have saturated output voltages beyond the linear region. Even if not saturated, output voltages cannot be resolved into several reference voltages. Therefore, it is very difficult to set the reference voltages for each comparator. To solve this problem, several clock delays and digital memories should be evaluated for cost and efficiency. The details are as follows: Only one comparator is used for the higher-bit ADC, and its reference voltage is set to the TIA output voltage, which corresponds to the maximum linear input current of the TIA. The output of the comparator is latched in a digital memory. During the next clock cycle, the reference current is subtracted from the input signal current of the IVC, and the resulting current is converted by the TIA. This converted voltage is compared to the same reference voltage, and the result is latched in sequence. These processes are continued until the comparator output goes to zero. As a result, a thermometer code is latched in the digital memories, and an adjusting current corresponding to the latched thermometer code can finally be generated. Thus, the first step of the conversion is complete; the second step of the conversion is identical to the procedure mentioned in the previous paragraph. In this way, the generated adjusting current is subtracted from the input signal current. This current subtraction is executed using Kirchoff s current law, which can be implemented simply by using current mirrors, as shown in Fig. 3. A cascade current mirror is used to prevent errors caused by the finite output impedance of the current mirror. Current directions, such as current sinks or current sources, can be properly controlled using a p-type or an n-type current mirror. A circuit diagram of a complete IVC and its control signals is shown in Fig. 4. The converter consists of a linear TIA with a p-type source-follower as an output buffer, a current subtractor, a ten-bit lower-bit ADC, and a two-bit higher-bit ADC with an adjusting current generator. The linear TIA basically consists of two pairs

3 Implementation of a Current-to-voltage Converter with a Wide Dynamic Jae-Hyoun Park and Hyung-Do Yoon Fig. 5. DC simulation result of the designed IVC. Fig. 3. Current subtraction of an adjusting current from an input signal current. Fig. 6. Layout of the fabricated IVC chip. Fig. 4. Circuit diagram and contol signals of the designed IVC. of transistors [3,5]. One pair is a diode-connected MOS transistor, which can be described as a logarithmic converter in the sub-threshold region [9,10]. The other is a common-source amplifier with a relatively low voltage gain. As shown in Fig 4, two bias current sources, IbiasN and IbiasP, are included in the designed TIA. The linearity and the conversion gain of the TIA can be determined by using IbiasN. The logarithmic characteristic of the diode-connected MOS transistor in the sub-threshold region can be eliminated by using IbiasP. The proposed IVC was designed and fabricated using 0.35-µm 2-poly 4-metal 3.3-V CMOS mixed-signal technology. A DC simulation result for the designed IVC is shown in Fig. 5. An identical I-V conversion curve is repeated four times because the higher-bit ADC has a two-bit resolution, and the IVC has 22 current blocks. Among those four curves, the curve at the very left corresponds to the TIA alone; namely, the higher-bit ADC output is equal to 00. We can see that the TIA has a maximum input current of about 2.5 µa. As the output of the higher-bit ADC is increased by 1 in binary, the next curves appear every two µa, which is equal to the reference current Iref. A layout of the fabricated chip is shown in Fig. 6. The fabricated chips were packaged using 48-pin QFPs (quad flat packages). The fabricated chip was measured using an evaluation system that consisted of a Keithley 2400 system as a programmable constant current source to supply an input signal current, an Agilent DSO7034A oscilloscope to measure the analog output voltage, several light-emitting-diodes (LEDs) with buffers to indicate 12-bit digital outputs, and a micro-processor to generate a master clock and control signals, which are shown in Fig. 4. A schematic diagram of the evaluation system is shown in Fig. 7. III. RESULTS AND DISCUSSION The current-to-voltage conversion characteristic of the fabricated linear TIA itself is shown in Fig. 8. Using the programmable constant current source, the input current

4 -866- Journal of the Korean Physical Society, Vol. 56, No. 3, March 2010 Fig. 7. Schematic Diagram of the evaluation system. Fig. 9. Current-to-voltage conversion characteristic of the overall IVC. Fig. 8. Current-to-voltage conversion characteristic of the linear TIA. was varied from 0 to 3.0 µa in 500-nA steps for currents above 100 na and in 30-nA steps for input currents below 100 na. The output voltage of the TIA was measured by using the oscilloscope. For input signal currents less than 100 na, the TIA had a nonlinear converting characteristic because the diode-connected MOS transistor, which was used as a logarithmic converter, was operating in the sub-threshold region, in which the drain current is dominantly caused by carrier diffusion [9,10]. The TIA, however, has a linear characteristic well suited for an input current range from 100 na to 2.5 µa. Furthermore, the logarithmic characteristic can be eliminated if the internal bias current I biasp is set to 100 na and above. The characteristic curve agrees well with the very left curve of the DC simulation result, as shown in Fig. 5. As mentioned above, the curve can be obtained when the higher-bit ADC output is equal to 00, that is, with no adjusting current. From this result, we can see that the fabricated TIA has a maximum linear input current of about 2.5 µa. The current-to-voltage conversion characteristic of the overall IVC is shown in Fig. 9, where the reference cur- rent is set to 2 µa. As shown on the top axis, the higherbit ADC outputs, which are the upper two bits of the IVC, increase sequentially in increment of the input current of two µa, such as For each block, the analog outputs are inversely linearly proportional to the input current. The lower-bit ADC outputs, which are the lower ten bits of the IVC, also vary linearly from 000h to 3ffh, as shown on the right axis. Therefore, for the overall expanded input current range from 0 to 8 µa, the digital outputs of the fabricated IVC vary from 000h to fffh, as shown in the underlined text, with good linearity. In view of the results so far measured, a maximum linear input current is expanded up to 8 µa, and its DR is approximately 80 db. Because the higher-bit ADC has two-bit resolution, the maximum input current range is expanded by four times, and the DR is widened by 12 db. If the higher-bit ADC has four-bit resolution, the maximum input current and the DR could reach up to 32 µa and 92 db, respectively. IV. CONCLUSION We present a novel current-to-voltage conversion algorithm, named the two-step conversion, that can achieve a wide DR. For verification of this algorithm, we realize an integrated IVC using 0.35-µm, 3.3-V CMOS mixedsignal technology, consisting of a linear TIA and two ADCs. As a result, even though the designed TIA has a maximum linear input current of only 2.5 µa by itself, the overall IVC embodying the two-step conversion with the TIA shows a linear current-to-voltage conversion characteristic up to an input signal current of above 8 µa. Its DR is approximately 80 db. Consequently, this can be generalized because the proposed two-step conversion method expands the maximum input current and the DR by 2 N times and 6N, respectively, without degradation of linearity, where N is the resolution of the higher-bit ADC. This current-to-voltage conversion algo-

5 Implementation of a Current-to-voltage Converter with a Wide Dynamic Jae-Hyoun Park and Hyung-Do Yoon rithm, therefore, can be applied to large-current sensing systems, such as avalanche photodiodes. ACKNOWLEDGMENTS This work was supported by the IT R&D program of ministry of knowledge economy (MKE) / Korea evaluation institute of industrial technology (KEIT), 2009-S , Development of Informative & Electronic Core Technology in Company Needs. REFERENCES [1] D. Mičušík and H. Zimmermann, Electron. Lett. 43, 159 (2007). [2] C. C. Hsieh, C. Y. Wu and T. P. Sun, IEEE J. Solid-St. Circ. 32, 1192 (1997). [3] C. Wang and J. Wang, 4th International Conference on ASIC (Shanghai, China, October 2001). [4] S. E. Hong, J. M. Lim, S. I. Kim and E. S. Nam, J. Korean Phys. Soc. 45, 742 (2004). [5] K. Bult and H. Wallinga, IEEE J. Solid-State Circuits SC-22, 357 (1987). [6] J. F. Johnson, IEEE Trans. Electron Dev. 46, 96 (1999). [7] M. Förtsch, H. Zimmermann and H. Pless, IEEE Sensors J. 6, 385 (2006). [8] M. Schanz, C. Nitta, A. Bußmann, B. J. Hosticka and R. K. Wertheimer, IEEE J. Solid-State Circuits 35, 932 (2000). [9] C. A. Mead, Analog VLSI and Neural Systems (Addison- Wesley, Boston, 1989). [10] M. Schanz, W. Brockherde, R. Hauschild, B. J. Hosticka and M. Schwarz, IEEE Trans. Electron Dev. 44, 1699 (1997). [11] Y. S. Hwang, H. J. Kim, H. Park, H. D. Kang, W. Kim, J. H. So and S. H. Kim, J. Korean Phys. Soc. 54, 2088 (2009).