OVERLAY PERFORMANCE IN ADVANCED PROCESSES

Transcription

1 OVERLA PERFORMANCE IN ADVANCED PROCESSES F. Bornebroek, J. Burghoorn, J.S. Greeneich, H.J. Mergens, D. Satriasaputra, G. Simons, S. Stalnaker, B. Koek ASML, De Run 111, 553 LA Veldhoven, The Netherlands This paper was first presented at the SPIE The 25th Annual International Symposium on Microlithography February 27-March 3, 2 Santa Clara, CA, U.S.A.

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3 OVERLA PERFORMANCE IN ADVANCED PROCESSES F. Bornebroek, J. Burghoorn, J.S. Greeneich, H.J. Mergens, D. Satriasaputra, G. Simons, S. Stalnaker, B. Koek ASML, De Run 111, 553 LA Veldhoven, The Netherlands ABSTRACT To guarantee less than 45 nm product overlay, required for the 13 nm IC technology node, a key component in lithographic tools is a sophisticated wafer alignment sensor that is able to deal with the influences of new, advanced IC processing. To prove that product overlay performance in this range is achievable, overlay results are presented that confirm the operational concept of the new ATHENA alignment sensor on various advanced processes in both front-end as well as back-end-of-line. In particular, the influences related to Chemical Mechanical Polishing (CMP) have been studied. The robustness of the system to large variations of W-CMP process parameters is highlighted. It is argued that full exploitation of the flexibility of the sensor will allow further optimization of its operation in actual production environments and that a product overlay of 35 nm is feasible. 1. INTRODUCTION Driven by aggressive semiconductor technology roadmaps, the required overlay budgets that apply to IC manufacturing process layers are posing a serious challenge for equipment manufacturers. Moreover, for some time already, these roadmaps have shown a considerable acceleration. For example, the dates for availability of R&D tools for the 13 nm and 1 nm technology nodes are being pulled forward in time and are now scheduled for 2 and 21, respectively. [1] single machine 25 nm 13 nm technology node 45 nm product overlay I ILL matched machine 35 nm Traditionally, the improvement of imaging resolution has been the roadmap s driving force and the accompanying improvements in overlay and CD control have been able to play an adequate supporting role. However, with the short-term forecast of a sub-35 nm product overlay requirement, the improvement of the overlay performance has become a primary concern of lithographic tool manufacturers. In general, any product overlay budget of lithographic tools can be built up from the following main contributors: - Single Machine overlay ( Tool-to-Itself ) - Matched Machine overlay ( Tool-to-Tool including reticle contributions) - Process-induced overlay As an example this subdivision with its numbers for the 13 nm technology node is graphically shown in Figure 1. In this paper the focus is on the process-induced overlay contributions and the results of overlay measurements on various advanced processes using ASML s new alignment system ATHENA (Advanced Technology Figure 1 processinduced 11 nm Product Overlay contributions for 13 nm technology node (3σ values) using High-order ENhancement of Alignment) [5] are presented. This new sensor has been introduced recently on state-of-the-art lithographic Step & Scan tools as an addition to the more conventional Through-The-Lens (TTL) alignment system [2]. Although the TTL system has a long record of being process independent, the design and operation of the newly added ATHENA system is mainly intended to deal with overlay issues related to more complex and destructive wafer processing technology. In particular, the effects on alignment accuracy of process-induced mark asymmetry and thin film stacks are being addressed by 1

4 the ATHENA system. Extensive results of the application of ATHENA on e.g. the W-CMP process at particular production sites can be found in reference [6] and [7]. A I ILL 2. ATHENA CONCEPT AND SSTEM DESCRIPTION To guarantee the compatibility in operation with the existing TTL alignment system, the off-axis ATHENA sensor uses the same type of wafer phase grating alignment marks. In the current Step & Scan tools the two sensors act together while performing a full reticle-to-wafer alignment. However, whereas the TTL system was capable of only detecting +1/-1st diffraction orders from these targets using a single wavelength, the ATHENA sensor is designed such that it can independently detect up to the 7th diffraction order from a standard alignment mark (16 µm pitch). In addition, these orders can be collected at two different wavelengths of operation: 633 nm (red) and 532 nm (green). The use of the ATHENA system on process layers is most advantageous if: 1. alignment phase grating marks suffer from polishing-induced asymmetry such as CMP processes (see for example in Figure 2). The detection of higher diffraction orders from standard alignment marks allows the extraction of wafer mark position data that corresponds to the higher spatial frequencies of the same mark. It has been proven that these higher spatial frequencies are less affected by typical wafer polishing processes than the fundamental spatial frequency or pitch of the mark. [4] As a consequence, the obtained high-order alignment results on CMP layers with the ATHENA system are more accurate than the results from a first order system 2. alignment signals reach an unacceptably low level due to destructive interference effects given the use of coherent light sources. These effects may occur in the current single-wavelength system on transparent film stacks or non-ideal alignment mark phase depths. By using two discrete and independent wavelengths for alignment operation, alignment on these stacks can be carried out with more accuracy. The key hardware module of the ATHENA sensor is its sensor frame that contains the imaging optical system. This optical module is an off-axis system and located next to the lithographic exposure lens. The so-called Figure 2 Phase-stepped interferometer images of the surface profiles of a single period of a standard 16 µm alignment mark (A) before, and B) after CMP baseline stability of the sensor with respect to the exposure system is guaranteed by the alignment sequence in which this baseline calibration is automatically updated during each reticle-to-wafer alignment. To maintain stability of neighboring systems such as the wafer stage interferometer system, the ATHENA optical module only contains passive optical components. The various diffraction orders coming off the wafer alignment mark at the two wavelengths are split into separate detection branches according to their wavelength. Each order produces an image of the mark onto its own fixed reference grating pattern inside the module. Heat-dissipating components, i.e. the two illumination laser sources and the optical detectors and electronics, are located at a non-critical position in the lithographic tool. These active components are linked to the optical module by means of optical fiber systems. A schematic layout of the sensor is shown in Figure 3 and a more detailed description of the system can be found in reference. [5] wafer mark Figure 3 modulator modulator detectors Schematic Layout of the Athena system B wavelength 1 CCD I ILL wavelength 2 detectors 2

5 By its design, the ATHENA sensor offers a tremendous flexibility to its user by providing independent alignment results for 7 diffraction orders and 2 wavelengths. In addition, proper methods can be defined to deduce a unique and accurate aligned position from difficult process layers on product wafers. 3. ALIGNMENT METHODOLOG When the overlay performance has to be optimized on a specific process layer, a simple and effective methodology is usually applied. The methodology contains two parameters: - mark layout: in addition to the standard mark with 16 µm pitch, the alignment mark can be enhanced for higher diffraction orders and - alignment recipe, i.e. the selection of the diffraction order and color to be used for determining the final aligned position. The high-order-enhanced alignment mark is laid out in such a way that the space of a standard mark with a 16 µm pitch is subdivided into lines and spaces with a smaller pitch. As an example, in Figure 4 a comparison is shown between a standard mark and two mark layouts that can be used to enhance the 5th and 7th diffraction order efficiencies. Basically, with the equal distribution of n line-segments over the 8 µm space (each having a 8/n µm segment length) the n-th diffraction order corresponding to the basic 16 µm pitch at the operation wavelength will be enhanced. 1 st order, 16 µm pitch 5 th order enhanced 7 th order enhanced Figure µm 1.14 µm 8 µm 8 µm Layouts of a standard 16 µm pitch alignment mark and high-order-enhanced marks Other parameters that play a role in the alignment methodology are the position of the alignment marks on wafers and the number of marks. The general observation is to use the alignment marks located in a ring between 6% and 8% of the wafer radius where the wafer processing is seen to be most stable wafer-to-wafer. As for the number of alignment marks, it was found that using a global align scenario with more I ILL than 4 pairs of marks per wafer offered no additional overlay improvement. [6] The use of a 4-parameter model is recommended to obtain the systematic parameters (wafer, translation, wafer rotation and scaling) from the wafer alignment data. For any given process layer the optimized mark and the recipe can be determined by evaluating a split wafer lot with recommended mark types (as few as 2) for the process stack and comparing the overlay results along with diagnostics data. This straightforward method gives excellent results in most cases, but more sophisticated recipe schemes, in which alignment results from several orders and both colors are combined, can be used to further optimize the performance. This extended optimization can be carried out if further improvement on a process layer is desired. Furthermore, other optimized mark segmentations can be readily implemented. 4. OVERLA RESULTS IN ADVANCED PROCESSES The overlay experiments have been performed at a number of IC manufacturers using their wafer layouts and measurement sequences. Typically, after processing a first layer, a second layer was exposed on the basis of an ATHENA wafer alignment sequence executed on the alignment marks printed in a preceding layer. For the overlay verification, box-in-box type targets were exposed on the wafers and their first-to-second layer overlay was determined using an off-line metrology tool. The obtained data was analyzed yielding the 3σ-values for the individual model parameters and mean plus 3σ-overlay values. 4.1 Shallow Trench Isolation For sub- m devices the formation of an isolating oxide field (LOCOS) in the front-end-of-line processing is being replaced by a more advanced process called shallow trench isolation (STI) in order to improve device packing density. Whereas the former consists of the straightforward thermal growth of an oxide layer, the latter utilizes well-defined etched wells, oxide deposition using CVD and the subsequent application of (oxide-) CMP. These process steps can lead to undefined mark depth and possible asymmetry of the alignment marks A number of wafers were exposed in a batch under single-machine conditions using two 2 µm-segmented full-size PA marks and aligning with ATHENA using a 3

6 Translation Translation scaling scaling rotation Non-ortho Table 1 Overlay results for STI recipe of 5th diffraction order at 633 nm wavelength. One set of process corrections was applied to the batch. The overlay results are shown in Figure 5 and Table 1 (29 fields/wafer, 1 point/field, and 2-point global alignment). These results comply with the overlay requirements as shown in Figure 1 leaving out the matched machine contribution. 4.2 Deep Trench On a batch of 2 wafers the Deep Trench process step was isolated in an experiment. In this particular case a scribe line (SPM) mark with a segmentation of.5 µm was used. The alignment marks were generated in the Deep Trench layer. The first layer was exposed on a DUV wafer stepper and the second layer was exposed on a DUV wafer scanner. The overlay verification was carried out using 36 fields/wafer and 1 point/field. The results are shown in Figure 6 and Table 2. It must be noted that the mark segmentation used does not enhance any higher order used by the ATHENA system. The segmentation was merely applied to make the mark compatible with the design rules of the specific process. The fact that the overlay was exposed under matched frequency Figure Overlay result for STI registration error (nm) machine conditions explains the higher overlay numbers. The larger overlay result for mean plus 3σ must be ascribed to the fact that the DUV stepper (ASML 55 /3) is not intended to operate at a 13 nm design rule. I ILL Translation Translation scaling scaling rotation Non-ortho 4.3 Poly-Si Table 2 Overlay results for Deep Trench frequency Figure registration error (nm) Overlay results for Deep Trench I ILL After poly-si layer deposition, alignment to marks printed underneath is no longer possible. This is due to the fact that the poly-si layer is opaque to the visible light used by the alignment sensor. Under these conditions, new marks are printed and etched in the previous dielectric layer, generally referred to as non-zero marks. However, as a result of the time-controlled etching these non-zero marks are quite deep and have an undefined alignment phase depth. In addition, it has been shown that resist spin-coating effects on such alignment marks might influence the overlay results. [4] Here, 5 wafers out of a 25-wafer batch were aligned using 4-point global alignment with 5th-order-enhanced marks at 633 nm and the overlay was verified on 4 4

7 Translation Translation scaling scaling rotation Non-ortho Table 3 Overlay results for Poly-Silicon points/field and 5 fields/wafer on an off-line metrology tool. One set of process corrections was applied to the batch. In Figure 7 and Table 3 the overlay results are presented. The overlay result complies with the 13 nm node requirement and proves that the ATHENA system is quite insensitive to the various effects that are related to this process. frequency Figure registration error (nm) Overlay Results for poly-silicon 4.4 W-CMP and metal deposition In the near future, W-CMP will remain an important process to be used in contact and lower metal/interconnect layers. For the metal/interconnect layers, zero-layer alignment marks in the silicon substrate can no longer be used as a reference as a result of aluminum metallization. In such a case, so-called non-zero marks have to be printed to act as new references. However, due to the tungsten removal and the subsequent aluminum deposition, these non-zero marks as well as overlay targets are severely degraded and asymmetry and shallow depth are introduced. The ATHENA alignment system has proven to be very effective under these conditions using its high-order detection capability. [6] As an example, in Figure 8 we show the results of an overlay measurement on such a layer: 12 wafers out of a batch of 25 wafers have been evaluated using frame-in-frame targets (5 fields/wafer, 4 points/field and a 4-point global alignment on 7th-order-enhanced marks using 633 nm wavelength). The, overlay results are 24 nm and 25 nm, respectively (mean plus 3σ). I ILL For the W-CMP process, the result is well within the requirement for a 13 nm design rule. To demonstrate the robustness of the overlay performance of ATHENA on W-CMP layers, 22 wafers were subjected to a CMP process of which the parameters were varied over a large range of various settings (splits). The parameters were: - pad type - slurry concentration - polishing speed - polishing direction - pad pressure - extra over polish time. frequency Figure registration error (nm) Overlay results for W-CMP and metal deposition For each wafer from each split the first layer was aligned and exposed on an I-line stepper. For the second layer this was repeated on a DUV wafer scanner using the ATHENA as well as the TTL alignment sensor. Two pairs of 7th-order-enhanced scribe line marks were aligned using a simple recipe consisting of only the 7th order at 633 nm. The mark location was near the x-axis at approximately 65% of the wafer radius. The x- and y-marks were chosen to be in neighboring scribe lines. The overlay on 28 frame-in-frame targets per wafer was measured using an off-line metrology tool. One process offset was used for all the wafers in the batch to correct for a matching offset. I ILL 5

8 The overlay verification over all 22 wafers yielded 55 nm and 64 nm maximum overlay errors in - and -direction, respectively. The overlay results from all wafers are shown in Figure 9 and Figure 1 as histograms. As in Table 4 we summarize the 3σ-values of the systematic wafer parameters over the 22 wafers as measured by the ATHENA system. These plots clearly show the strength of the ATHENA alignment concept and plainly demonstrate its enlarged insensitivity to CMP-induced mark position variations. Whereas the TTL system accounts for very large overlay errors over the whole parameter window, the ATHENA system shows a maximum overlay error of 64 nm. percentage [%] Figure overlay error Overlay results for W-CMP wafer split using ATHENA I-15.ILL 4 The ATHENA overlay results can be explained by taking into account the unrealistically large parameter variation and the fact that the experiment was performed under matched machine conditions. In addition, please note that a part of the overlay error consists of non-correctable registration errors that are introduced by the metal deposition process (PVD). [3] [7] percentage [%] overlay error Figure 1 Overlay results for W-CMP wafer split using TTL I-156.ILL Table 4 W-CMP overlay results for 22 wafer split with large variations of process parameters using ATHENA Translation Translation scaling rotation Maximum overlay Maximum overlay As an example of process parameter dependence, we show the effect of large variation of the polishing rotational speed. Six process splits among the 22wafers represent the study of the impact of CMP tool speed settings using a rotational CMP tool setup. A platen holding a hard polish pad rotates at a fixed speed of 13 RPM, while the rotational speed of the head holding one wafer has been varied from 53 RPM to 153 RPM. The default process setting for this W-CMP process is 11 RPM. In Figure 11 the measured wafer rotation is shown for the 1st diffraction order. The wafer rotation shows a clear linear dependency on the rotation difference between the CMP tool head and platen. In a production environment this means that the process corrections would need continuous adjustment according to the process variation. Figure 11 also shows that the linear dependency is greatly reduced by the use of 7th order ATHENA. This means that process corrections will become more stable by using the ATHENA system in a production environment. wafer rotation offset [mrad] Figure 11 1 st order 7 th order rotation difference [RPM] Modeled wafer rotation as a function of polish speed difference between head and platen. Measured results for 1st and 7th order are shown. I-158.ILL 6

9 4.5 Cu-Damascene In the process of increasing device speeds the use of copper in back-end metallization is advantageous over aluminum, since the electrical conductivity of copper is better than that of aluminum. The combination of copper CVD and electro-plating enables improved filling of small features, as compared to metal sputtering. As a result, the parasitic capacitance between these small metal lines is reduced. Using inter-layer dielectric materials with low dielectric constants the capacitance can be decreased even further. These materials are usually referred to as low-k materials. frequency registration error I-1513.ILL Figure 12 Overlay results for Cu-Damascene process Table 5 Overlay Results Cu-Damascene Translation Translation scaling scaling rotation Non-ortho A batch of 6 s has been processed up to the 5th metal level of a dual-cu-damascene process. Here, regular PA-type marks (16 µm pitch without segmentation) have been exposed in the dielectric layer preceding the 2nd metal layer. These marks are of the so-called floating type, i.e. no metal pad is available below the mark. An alignment recipe using the 3rd order of the green alignment branch was used. In Table 5 the overlay data is presented (15 fields/wafer, 4 points/field). The overlay results in this experiment are slightly higher than the required 45 nm product overlay. However, since regular 16 µm pitch marks have been used, an improvement of the overlay can be anticipated by applying the high-order-enhanced marks. 5. FUTURE IMPROVEMENTS It must be underlined that all results as shown above have been obtained using simple alignment mark and recipe methodology. ATHENA s full potential as the alignment sensor for the next-generation IC technology can be realized by further implementation of its embedded application flexibility. First, it can be expected that further optimization of the alignment recipes will improve the overlay behavior. As shown, the initial use of so-called static recipes using single diffraction orders and single colors, gives good results. This methodology can easily be extended to the use of so-called dynamic recipes. In these recipes the final aligned position is an intelligent weighted average of the aligned position information of the various diffraction orders and wavelengths thereby greatly enlarging the operational power of the sensor system. Second, the functionality of the system can be advanced by variation of the alignment mark types: the applied alignment mark layout should be explored to ensure high robustness to process variation. In addition, mark layout with e.g. a specific segmentation will inherently determine the diffraction orders that are likely to be successful candidates to be chosen for an alignment methodology. It is the equipment supplier s goal to minimize the effort for the user in the implementation of this improved alignment methodology in his new process layers. To achieve optimal results on future types of process layers the user needs only to provide processed wafers with the expected process variation range containing recommended alignment marks. The applications software evaluates the overlay performance on each mark type and location per wafer. Based on the data analysis, the best mark type, mark location and number of marks will be recommended in conjunction with the appropriate alignment recipe. To comply with the overlay requirement for the 1 nm technology node a considerable decrease of the contributions of single machine and matched machine overlay must be attained as well. This is illustrated by in 7

10 Figure 13. To meet the 35 nm product overlay requirement for this node, all overlay contributors should be further reduced. For the single machine contribution the alignment repeatability and accuracy as well as the wafer stage accuracy will have to be increased. For tool-to-tool matching, the overlay contribution can be reduced by controlling the image field distortion induced by both the lens and the reticle and by lowering the wafer grid distortion. single machine 2 nm processinduced 1 nm Figure 13 1 nm technology node 35 nm product overlay Product Overlay contributions for the 1 nm technology node (3σ values) 6. CONCLUSION As a conclusion, the results of alignment performance verification on the various advanced processes show that current and near-future overlay requirements can be met by using the ATHENA alignment sensor. Already a simple implementation of its capabilities provides good overlay performance on various process layers, such as W-CMP, STI and Cu-Damascene. In the case of W-CMP the ATHENA sensor was shown to be robust against large variations of the process parameters. I-1514.ILL matched machine 25 nm ACKNOWLEDGEMENTS The authors gratefully acknowledge the contributions of Merritt Philips, Allan Dunbar, Ron Schuurhuis, Pui Lam, Paul Hinnen, Maurits van der Schaar, Richard van Haren and Alex van der Hoff. The authors thank Jan van der Werf of Philips Research Laboratories for the phase-stepped interferometer images. REFERENCES [1] The International Technology Roadmap for Semiconductors, 1999 edition [2] S. Wittekoek, M. van den Brink, H. Linders, J. Stoeldraijer, J.W.D. Martens and D. Ritchie, Deep UV Stepper with Through The Lens Alignment, Proc. SPIE, vol.1264, 199, p [3] P. Dirksen, C. Juffermans, A. Leeuwestein, C. Mutsaers, A. Nuijs, R. Pellens, R. Wolters, J. Gemen, Effect of processing on the overlay performance of a wafer stepper, Proc. SPIE, vol. 35, pp , 1997 [4] J.H. Neijzen, R. Morton, P. Dirksen, H. Megens, F. Bornebroek, Improved wafer stepper alignment performance using an enhanced phase grating alignment system, Proc. SPIE, Vol. 3677, 1999 [5] J. v. Schoot, F. Bornebroek, M. Suddendorf, M. Mulder, J. v.d. Spek, J. Stoeten, A. Hunter, P. Rummer,.7 NA DUV Step & Scan system for 15 nm imaging with improved overlay, Proc. SPIE, vol. 3679, pp , 1999 [6] G. Rivera, L. Rozzoni, E. Castellana, G. Miraglia, P. Lam, J. Plauth, A. Dunbar, M. Phillips, Overlay Performance on tungsten CMP Layers Using the ATHENA Alignment System, Proc. SPIE Microlithography, 2, this volume [7] R. Seltmann, W. Demmerle, M. Staples, A. M. Minvielle, B. Schulz, S. Muehle, Overlay budget considerations for an all scanner fab, Proc. SPIE Microlithography, 2, this volume A further reduction of the process-induced contribution to the product overlay can be accomplished by fully applying the system s flexibility to dedicated process conditions. 8

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