CMOS Image Sensors aka Monolithic Active Pixel

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1 DESY University Hamburg Instrumentation seminar 22 nd October 2010 CMOS Image Sensors aka Monolithic Active Pixel Sensors(MAPS) for scientific applications Dr Renato Turchetta STFC-RAL Rutherford Appleton Laboratory Oxfordshire, UK ac uk tel. : (+44) fax. : (+44)

2 2 Acknowledgements A. Clark, R. Coath, J.P. Crooks, P. Gasiorek, N. Guerrini, A. Jain, B. Marsh, I. Sedgwick, M. Stanitzki, M. Tyndel (Rutherford Appleton Laboratory) R. Henderson, W. Faruqi, G. McMullan (MRC-Laboratory of Molecular Biology) G. Van Hoften (FEI) A. Nomerotski, M. Brouard, C. Vaillance (Oxford University) P. Dauncey (Imperial College, London) J. Velthuis, J. Goldstein, D. Cussans (Bristol University) R. Speller, A. Olivo, G. Royle (UCL) and many others! (apology for missing names!)

3 3 Outline Introduction. What is industry up to Detection in CMOS CMOS sensor architecture Integration vs single particle detection. Integration Single particle detection Pixel choice Speed limit Examples Conclusions INMAPS technology INMAPS demonstrated Examples Single Photon Avalanche Detectors (SPAD)

4 4 Outline Introduction. What is industry up to Detection in CMOS CMOS sensor architecture Integration vs single particle detection. Integration Single particle detection Pixel choice Speed limit Examples Conclusions INMAPS technology INMAPS demonstrated Examples Single Photon Avalanche Detectors (SPAD)

5 CMOS image sensors CMOS = Complementary Metal-Oxide-Semiconductor = NMOS + PMOS (Re)-invented in the early 90s. NASA s Jet Propulsion Laboratory (E. Fossum s group) could be considered as the (re)birthplace Charge Coupled Devices (CCD) were the dominant imaging device at the time (not anymore!) Standard CMOS technology all-in-one detector-connection-readoutconnection readout very small pixels low power consumption radiation resistance system-level cost / Increased functionality random access (Region-of-Interest ROI readout) high speed (column- or pixel- parallel processing) ease of use for end users

node 10xMFS Scaling bracket from E. Fossum, IEEE T-ED ED, vol.

6 6 The Megapixel Race Front Side Illuminated (FSI) 20xMFS MFS = Minimum Back Side Illuminated (BSI) Feature Size = technology node 10xMFS Scaling bracket from E. Fossum, IEEE T-ED ED, vol. 44, n. 10, 1997 Adapted from S. Wuu (TSMC) et al., 2009 IISW, June 2009

7 7 Pixel size for common formats Medium Pixel format Number of pitch DSLR megapixels (μm) Format

8 8 Outline Introduction. What is industry up to Detection in CMOS CMOS sensor architecture Integration vs single particle detection. Integration Single particle detection Pixel choice Speed limit Examples Conclusions INMAPS technology INMAPS demonstrated Examples Single Photon Avalanche Detectors (SPAD)

9 9 Detection of visible light Standard substrate is ~ 5 µm thick, ~10s Ohm cm charge collection by dff diffusion From A. Theuwissen, Charge Coupled Devices

10 10 UV, X rays, s 1 m 1.E+06 1.E+05 ion length (µm) Absorpti 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 Photon energy (kev)

11 11 Electrons Energy loss E by ionization 1 m From A. Cole, Absorption of 20 ev to 50 kev Electron Beams in Air and Plastic, Radiat. R 38 7 (1969) Number N of electron-hole pairs generated in silicon N E[eV] 3.6 Res. 38, 7 (1969). Most probable value: ~80 electron-hole pairs per micron (Minimum Ionising Particles MIP)

12 12 Detection in CMOS Passivation layers and NMOS Diode NMOS Front Side Illumination routing (SiO2 + metal) A few µm N+ N+ N+ N+ P-Well N-Well P-Well ~1 µm P-epitaxial layer ~ µm 20 µm Sensitive volume P-substrate Back-thinning Back Side A few Illumination i hundred d µm

13 13 Detecting charged particles First image of high energy electrons (~GeV) obtained with MAPS (beginning First images in an electron 2000) microscope, LMB-MRC Cambridge 19 February 2003

14 14 Outline Introduction. What is industry up to Detection in CMOS CMOS sensor architecture Integration vs single particle detection. Integration Single particle detection Pixel choice Speed limit Examples Conclusions INMAPS technology INMAPS demonstrated Examples Single Photon Avalanche Detectors (SPAD)

15 CMOS image sensor architecture. Digital camera pixels: only a few transistors and only NMOS... Why only NMOS? See later. From:

16 16 Integrating sensor architecture Reset, Select, ec Transfer signals Can include ADCs, e.g. column parallel

17 17 Stitching D B B D Reticle size is just over 2cm x 2cm stitching Reticle is subdivided in blocks C A A C Up to single sensor per wafer Sensors of different sizes on the same C A A C wafer D B B D

18 18 Stitching D B B D Reticle size is just over 2cm x 2cm stitching Reticle is subdivided in blocks C A A C 56 mm Up to single sensor per wafer 56 mm Sensors of different sizes on the same C A A C wafer D B B D

19 19 Outline Introduction. What is industry up to Detection in CMOS CMOS sensor architecture Integration vs single particle detection. Integration Single particle detection Pixel choice Speed limit Examples Conclusions INMAPS technology INMAPS demonstrated Examples Single Photon Avalanche Detectors (SPAD)

20 20 Outline Introduction. What is industry up to Detection in CMOS CMOS sensor architecture Integration vs single particle detection. Integration Single particle detection Pixel choice Speed limit Examples Conclusions INMAPS technology INMAPS demonstrated Examples Single Photon Avalanche Detectors (SPAD)

21 21 Pixel choice. Integrating g sensors RESET 3T RESET 9T TX 4T SELECT SELECT Column Fewer transistors higher fill factor In-pixel CDS not possible higher noise Can be very rad-hard CDS=Correlated Double Sampling Column Lower fill factor In-pixel CDS possible very low noise Can be rad-hard Shared architectures 1.75T pixels Add snapshot,..., 5T, 6T,... STFC IP Derived from 3T Allow multiple integration time very high dynamic range

22 22 4T sensor (Fortis) Conversion gain at output: 65.0μV/e- Linear dynamic range: 4,970 Most probable noise: 3.6e- Linear full well capacity: 17,900e- Maximum full well capacity: 27,350e- Maximum dynamic range: 7,597 Noise histogram Average noise: 4.5e- Noise (in e-, before board noise correction)

23 23 9T (LAS) Image of a laser point Standard readout High-dynamic range readout T int0 = 80, T int1 = 30, T int2 = 1

24 24 High Dynamic Range (LAS) ignal (DN Effectiv ve) >140dB Dynamic range can be extended further if overlap is reduced or even Seliminated 100 (depending on Light Intensity (nw/cm^2) image requirements)

25 25 Speed example. A 4kx4k sensor Rea dout sp peed (fp s) Simplest readout: use only one line per column on one metal (routing) level Wafer limit (200 mm) Reticle limit Pitch (in μm) )

26 26 Speed example. A 4kx4k sensor s) peed (fp Readout sp Allow multiple l readout lines on the same routing level Wafer limit Reticle limit Pitch (in μm) )

27 27 Speed example. A 4kx4k sensor s) peed (fp Readout sp Add a metal level for routing Pitch (in μm) )

28 28 Speed example. A 4kx4k sensor s) peed (fp Readout sp and another one Pitch (in μm) )

29 29 Wafer scale sensor Rea dout sp peed (fp s) One sensor = a single 200 mm wafer Simple readout case Aspect ratio = n. column/n. rows

30 30 Transmission Electron Microscopy Direct detection in general and TEM (Transmission Electron Microscopy) in particular require sensors with specific characteristics. CMOS sensors present several advantages when compared to alternatives like film or CCD sensors: Film: very yg good resolution, non digital, needs time for development, poor S/N for weak exposure CCD with phosphor: not direct detection (radiation hardness), phosphor ruins spatial resolution, good for tomography. CMOS: direct detection, good spatial resolution, good sensitivity (single electron)

31 Radiation hardness Every block has been designed accordingly to radiation hardness requirements, using ELT (Enclosed Layout Transistors), substrate contacts and circuit redundancy.

31 31 Radiation hardness Every block has been designed accordingly to radiation hardness requirements, using ELT (Enclosed Layout Transistors), substrate contacts and circuit redundancy. Radiation can create positive charge at the thin/thick oxide interface (bird s beak) Such positive charge can short-circuit source and drain of the MOS transistors. Test under electron beam showed that the sensor was still operating after being irradiated with of Me/px. 31

32 32 Sensor specifications 61x63 mm 2 silicon area 0.35 m CMOS process 16 million pixels 4Kx4K array Analogue outputs Frame rate in excess of video rate Radiation hard characteristics Pixel binning Region Of Interest readout Operating voltage up to 300keV Binning 1X, 2X and 4X DQE 0.5 Nyquist, 300keV Readout noise lower than 0.1pe/px Dynamic range 16 bits Radiation hardness of several 100 s of million electrons/px

33 33 Some results Gold reflections at Low Dose FEI Falcon TM 2.3Å Gold lines at 1.1Å/pixel TEM Mag 96kx* 4kx4k CCD 2.3Å Gold lines at 0.9Å/pixel TEM Mag 120kx* Magnifications were chosen such that Nyquist was as close as possible to 23A

34 34 Outline Introduction. What is industry up to Detection in CMOS CMOS sensor architecture Integration vs single particle detection. Integration Pixel choice Speed limit Examples Conclusions Single particle detection INMAPS technology INMAPS demonstrated Examples Single Photon Avalanche Detectors (SPAD)

35 35 How much CMOS in a CMOS sensor? NMOS Diode NMOS PMOS N+ N+ N+ N+ P+ P+ P-Well N-Well P-Well N-Well P-substrate (~100s m thick) 100 % efficiency only NMOS in pixel no complicated electronics Complicated electronics NMOS and PMOS,i.e. CMOS low efficiency

36 36 The INMAPS process NMOS Diode NMOS PMOS N+ N+ N+ N+ P+ P+ P-Well N-Well P-Well N-Well Deep P-Well P-substrate (~100s m thick) Standard CMOS with additional deep P-well implant. Quadruple well technology. 100% efficiency and CMOS electronics in the pixel. Optimise charge collection and readout electronics separately!

37 37 INMAPS application. Pixel with timing capability preshape Gain 94µV/e Noise 23e- Power 8.9µW 150ns hit pulse wired to row logic Shaped pulses return to baseline 50 µm pixel µ p Over 150 transistors, N and PMOS

through cell 10 real-dpw 60 0 50 0 10 20 30 40 50 ignal % total si 40 30 20 GDS+DPW GDS-DPW Real+DPW

38 38 Experimental proof Amplitude results With/without deep pwell 60 Profile B; through cell Compare 50 Simulations GDS Measurements Real gnal % total si GDS+DPW GDS-DPW Real+DPW Profile F; through cell 10 real-dpw ignal % total si GDS+DPW GDS-DPW Real+DPW Position in cell (microns) Pixel profiles 10 0 real-dpw F Position in cell (microns) B

39 39 Response to visible light A white light source focused to a 2.2µm 2µm spot size was used to horizontally scan across three adjacent pixels to determine the charge collection efficiency of FORTIS ADC Cou unt (DN) 5x10 4 4x10 4 3x10 4 2x10 4 1x10 4 0x10 4 Crosstalk between pixels (15μm pitch) Diode Metal on pixel Horizontal Distance (µm)

40 40 High resistivity 5x10 4 ADC Coun nt (DN) 4x10 4 3x10 4 2x10 4 1x10 4 Crosstalk reduced due to increase in depletion region of diode and reduction in charge drift Diode Metal on pixel 0x Horizontal Distance (µm)

41 41 41 Time Of Flight Mass Spectroscopy py Courtesy of A. Nomerotski et al., Oxford University

42 42 42 Time Of Flight Mass Spectroscopy py Courtesy of A. Nomerotski et al., Oxford University

43 43 Pixel architecture Charge Collection Diodes Preamplifier Shaper Comparator

44 44 Sensor specifications 72 by 72 pixel array 70 um x 70 um pixel size 4 diodes per pixel Time-code resolution < 100 ns 4 x 12 bit time-code storage registers per pixel Less than 1 us dead time within a pixel following a hit At least 20 experimental cycles per second External Trigger enabled Optional analogue readout of intensity information

45 45 Outline Introduction. What is industry up to Detection in CMOS CMOS sensor architecture Integration vs single particle detection. Integration Single particle detection Pixel choice Speed limit Examples Conclusions INMAPS technology INMAPS demonstrated Examples Single Photon Avalanche Detectors (SPAD)

46 46 Counting visiblelight photons Single Photon Avalanche Detector (SPAD)

47 Single Photon Avalanche Detectors (SPAD) STFC development

New process development. Diodes operated below breakdown.

(Geiger mode) Target (ideal) specifications Low Dark Count

All in CMOS, so that other Dead time: <100 (<10) ns

47 47 Single Photon Avalanche Detectors (SPAD) STFC development with a leader CMOS Image Sensor foundry. New process development. Diodes operated below breakdown. Photon triggers avalanche large charge pulse yes/no response (Geiger mode) Target (ideal) specifications Low Dark Count Rate (DCR): <1000 (<1) Hz Timing resolution: <200 (<20) ps All in CMOS, so that other Dead time: <100 (<10) ns functionalities can be integrated with the SPAD within a pixel, e.g. Time-to-Digital converters, counters, First single pixel silicon back in October-November. More than one iteration might be needed to achieve the performance

48 48 Outline Introduction. What is industry up to Detection in CMOS CMOS sensor architecture Integration vs single particle detection. Integration Single particle detection Pixel choice Speed limit Examples Conclusions INMAPS technology INMAPS demonstrated Examples Single Photon Avalanche Detectors (SPAD)

49 49 Conclusions Direct detection of photons from IR cut off up to low energy X rays Direct detection of charged particles Indirect detection of high energy gy photons Low noise sensors (3.6 e rms demonstrated) and moving towards single (visible light) photon detection ( SPAD) Dynamic range can be in excess of 20 bits High speed ~10 10 pixel/sec for standard imaging Single particle detection now possible (INMAPS process) fast timing better than 100ns Large area sensor up to wafer scale: 200 mm for 180nm and 300 mm for 90nm Radiation hardness in excess of 10 Mrad demonstrated

A MAPS-based readout for a Tera-Pixel electromagnetic calorimeter at the ILC

A MAPS-based readout for a Tera-Pixel electromagnetic calorimeter at the ILC STFC-Rutherford Appleton Laboratory Y. Mikami, O. Miller, V. Rajovic, N.K. Watson, J.A. Wilson University of Birmingham J.A.