HANA Semiconductor (Ayutthaya) Co. Ltd. Die Design Rule For Assembly Of Plastic Devices

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Vivien Gregory
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1 HANA Semiconductor (Ayutthaya) Co. Ltd. Die Design Rule For Assembly Of Plastic Devices 1.0 PURPOSE : 1.1 To define the rules to be observed to facilitate review of process ability of devices prior to production loading. 1.2 To provide the recommended and minimum/maximum requirements for die design and layout of integrated circuit devices and corresponding packages. This design will be compatible with existing assembly equipment to achieve high reliability and high assembly yields. Recommended: Represents normal capability, which is widely available with standard set, ups and process control. Minimum/Maximum : Represents leading edge technology with very limited capacity and requires engineering support on first time build For minimum/maximum: A price adder may be required since the total cost is higher (longer set up time, etc.) 2.0 SCOPE: 2.1 This specification shall be applicable to all packages assembled at Hana Semiconductor Ayutthaya Co., Ltd..0 REFERENCE DOCUMENTS:.1 Mil-STD-88.2 PEN00 Design Control Procedure 4.0 MATERIALS / EQUIPMENTS / TOOLS NEEDED: 4.1 N/A.0 REQUIREMENTS / INFORMATION:.1 Safety Requirements / Information:.1.1 N/A.2. Process Requirements / Information:.2.1 N/A. QC Requirements / Information:

2 ..1 N/A.4 Environmental Management System Requirements / Information:.4.1 N/A. Maintenance Requirements / Information:..1 N/A.6. Other Requirements / Information:.6.1 Responsibilities Process engineers are responsible to determine and define Hana machine and process capability, which shall be the basis for establishing the design, rules as stated in this specification Marketing is responsible to ensure that all customers are aware of Hana design rule and responsible to notify customers on possible assembly yield losses and reliability risks for products that are out of Hana design rule. 6.0 PREPARATION / SET UP: 6.1 N/A 7.0 PROCEDURES: 7.1 Die/Wafer related design rules Wafer diameter and wafer thickness Wafer diameter: Wafer diameter shall be, 4,, 6 and 8 (76, 102, 127, 12 and 20 mm) Wafer thickness Wafer thickness is very important to meet the existing assembly equipment capability and to maintain balanced flow of mold compound between top and bottom cavities at mold process, and to maintain defined loop height as specified in wire bond specification. The thickness must be within the design rule. Violation of design rule will cause loss of yield, quality, and reliability problems. Wafer thickness requirements shall be classified into 2 categories: A) Wafer thickness per wafer diameter. Wafer thickness on this category is important for wafer handling at wafer mount, wafer saw and wafer back grinding process to prevent yield loss and quality/reliability related problems. Wafer diameter Wafer thickness(min max) Inch MM Mil Micron

3 B) Wafer thickness per package type. Wafer thickness per package type is required to obtain a balanced flow of mold compound in top/bottom mold cavities in conjunction to wire bond material and/or die coat material. Package type Min. thickness Max. Thickness Recommended thickness Mil Micron Mil Micron PDIP 00 See item PDIP 600 Section A SOIC SOIC SOIC TSOP TSOT SOT2, SC MSOP (Standard) MSOP U (Power pad) QSOP PLCC QFP (10x10/14x14) QFP (14x20) VSOP SOT LGAB, LGAC (package thickness 0. mm) SOT

4 TO92 QFN / DFN / LGAB (udfn : package thickness 0.7 mm) C. Maximum thickness with die coat Wafer thickness of device, which requires die coat is very important to meet the existing equipment capability and to maintain gap between top of package and coating material at mold process. The design must be within the wafer thickness design rule. Violation of design rule will cause yield loss. Wafer thickness with die coat shall be classified by die size. Die size (mils) Max. Wafer thickness(mils) < 100 Per thickness in section B Minus from Max wafer thickness in section B > 200 Minus from Max. wafer thickness in section B Wafer configuration Scribe Street Geometry Street with A Scribe street Device Street without pattern Figure 1: Scribe street width (A) The scribe street opening is defined as the glass free area between the edges of product die scribe ring. The opening should not contain active circuit elements.

5 Scribe street width Wafer thickness Mini mum saw street width Without test pattern With test pattern Mils Micron Mils Micron Mils Micron < 16 < > Note. For 8L-VSOP of Phillips wafer the scribe street width are not less than 0 micron or 2.0 mils Scribe street edge Recommend scribe street edge shall be overlap from active metal: 1.2 mils minimum Wafer back lap preparation: Wafer back lap shall be grind in In-Feed pattern and wafer backside preparation can be with or without gold deposition Note: Back lapped wafers are preferred as they provide better conductive epoxy die attach and tape mounting adhesive Reject Die Identification Indicator for all of reject die (ink die, test die, mirror die) is ink or laser. Black color for ink dot is recommended and its position should be accurate.

6 Ink dot size and thickness requirements. Die size Min ink dot size Diameter Thickness Mil Micron Mil Micron < 20 <08 > > 127 Reject any transparent ink, translucent ink > 8 > 20 (not opaque) and metallization under the > 10 > 24 Ink can be seen at 100X magnification on > 1 > 81 Microscope inspection. Reject ink dot thickness > 200 > 000 > 20 > 08 more than 0.8 mils ( 20.2 Micron ) Die attach related Maximum die size is governed by die pad size. See Item for minimum gap between die edge and die attach pad edge Minimum gap between die edge and die pad edge by die length (see Figure 2 for illustration). Die Length (C) Min. gap between die edge to die attach pad edge(mils) Without Ground Bond With Down Bond (DAP TO LD) With Down Bond (BDP TO DAP) (A) (B) (B1) < mils mils mils mils mils mils mils > 00 mils 2 40

7 Figure 2 : Gap Between Die Edge and Die Pad Edge

8 7.1. Wire bond related opening Minimum bond pad opening A (Figure ) Wire size Single bond Double bond Triple bond Mil Micron Mil Micron Mil Micron Mil Micron x.0 76 x 76.0 x x x x x.7 94 x 94.7 x x x x x x x x x x x x x x 0 4. x x x x x x x x 67 Figure Bond Pad Opening ( A ) and Bond Pad Pitch ( P )

9 Min. bond pad pitch P (Figure 2) Wire diameter Pad pitch Mil Mil Micron , Wire length and loop height per package type. Package type Lead count Wire size Wire length Loop height Min Max Min-Max Nominal Mil Mil/Micron Mil/Micron Mil/Micron Mil/Micron PDIP 00 8, 14, 16, 18, 20, 22, / / / / / 0 12 / 0 PDIP , 28, 2, / / / 0 PLCC 2, 44, 68 10/ / /0 SOIC 10, SOIC 208 8, 14, , 1., 2.0 SOIC 00 16, 20, 24, TSOP 2, MSOP 8, , 1.0 QSOP 10 16, 20, 24, / /240 80/ /048 80/ /048 60/124 60/124 80/ / / / / / / / / / / / / 0 12 / 0 12/0 12/0 6/12 6/12 6/12 6/12 12/0 12/0 QFP 44, 2, , 200/ / /24 80, , 200/ / /0 TSOT2,, 6, 8 0.8, 1.0, 60/ / /12 SC70, SOT2,,, 6, 8 0.8, 1.0, 60/ / /12 VSOP SOT22 4, 1.0, 2.0 / / / /24 LGAB, LGAC, 6, /12 21/ 8-11/ /24

10 (Package thickness 0. mm) SOT89, TO92 2, 1.0, 60/ / /24 QFN, DFN, LGAB (udfn : Package thickness 0.7 mm) All 1.0, 80/ / / Bonding pads shall ideally be located on the perimeter of die and shall be located within an area defined by lines extending inward from the package post to the center of the die (Figure 4) Figure 4: Pad Location Weld placement from lead tip: 10 mil (24 microns) typical Maximum distance from bond pad to die edge: 2 mil (6 microns)

11 Maximum wires per lead by package type. PACKAGE LEAD COUNT PDIP 00 8, 14, 16, 18, 20, 22, 24 WIRE SIZE (Mil) 1.0 NO OF WIRE PER LEAD (MAX.) PDIP , 28, 2, 40 SOIC 10 8, 14, SOIC SOIC 00 16, 20, 24, TSOP 2, 40, 44 STP 22, 40 TSOT2, 4,, 6 0.8, SC70, SOT 2 & VSOP, 4,, 6 0.8, SOT144 / MSOP 8, , 1.0 QSOP 10 16, 20, 24, QFP 44, 2, 64, 80, SOT22 4, QFN All An equal number of pads on each side of die, equally or symmetrically arranged is recommended (Figure 4).

12 Special case of corner bond pad arrangement: careful consideration should be given to die size, bond pad size and lead widths such that wire lengths and wire angles are optimized (Figure ). Minimum wire angle: 40 degrees Figure : Corner Bond Layout 7.2 Special design/guideline requirements for very small packages (packages with body width of less than 0.10 inches) Determining maximum pad size: Code: (A) Package body to edge of lead = 0.00 inch min. (B) Lead tip length = 0.00 inch min. (C) Lead tip to pad = 0.00 inch min. (based on leadframe thickness) (D) Package body to edge of pad = inch min. (E) Coined area of lead shoulder = inch min. Max. Pad width = Pkg. Width - 2(A+B+C)* Max. Pad length = Pkg. Length - 2D *Max pad calculation may not be applicable for fused pin to DAP option. 8.0 FORMS / APPENDICES:

13 8.1 Table 1: Wafer thickness per package type (IR) Package type SO-JM 10 8 Min. thickness See item Section A. Max. Thickness Recommended thickness Mil Micron Mil Micron Using leadframe without Downset. MSOP SOT

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