PI5A100 Precision, Wide Bandwidth 4PDT Analog Switch

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1 Single Supply Operation (+2V to +6V) Rail-to-Rail Analog Signal Dynamic Range Low On-Resistance (6Ω typ with V supply) Minimizes Distortion and Error Voltages On-Resistance Matching Between Channels,.Ω typ On-Resistance Flatness, <2 Ω typ Low Charge Injection Reduces Glitch Errors, Q = 6pC typ Replaces Mechanical Relays High Speed. t ON, 8ns typ. Low Crosstalk: MHz Low Off-Isolation: MHz Wide -3dB Bandwidth: 23 MHz High-Current Channel Capability: >ma TTL/CMOS Logic Compatible Low Power Consumption (.µw typ.) Small QSOP- Package Saves Board Area Applications Audio, Video Switching and Routing LAN Switches Telecommunication Systems Battery-Powered Systems PIA Ω. Ω Ω ON Functional Block Diagram, Pin Configuration and Truth Table 1 Decoder Vcc 1 NO NO 2 12 NO NO3 3 Ordering Information Part Number Package PIAW Narrow SOIC- PIAQ QSOP- Switches shown for logic "" input. = Normally Closed; NO = Normally Open 1

2 PIA Absolute Maximum Ratings Voltages Referenced to Gnd V CC...-.V to +7V V, V, V, V NO (Note 1)... -.V to Vcc +2V...or 3mA, whichever occurs first Current (any terminal except,no,)...3ma Current,, NO, (pulsed at 1ms, % duty cycle)... 12mA Thermal Information Continuous Power Dissipation Narrow SO & QSOP (derate 7mW/ º C above +7 º C) mW Storage Temperature º C to +1 º C Lead Temperature (soldering, s) º C Note 1: Signals on, NO,, or exceeding Vcc or Gnd are clamped by internal diodes. Limit forward diode current to 3mA. Caution: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Electrical Specifications - Single Supply (V CC = ±%, = V, V H = 2.V, V L =.8V) Ω 2

3 PIA Electrical Specifications - Single Supply (continued) (V CC = + V ±%, = V, V H = 2.V, V L =.8V) Ω Notes: 1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in this data sheet. 2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. Guaranteed by design R ΟΝ = R ΟΝ max R ΟΝ min Flatness is defined as the difference between the maximum and minimum value of on-resistance measured. 6. Leakage parameters are % tested at maximum rated hot temperature and guaranteed by correlation at +2ºC. Off Isolation = 2log [ V / (V NO or V ) ]. See figure Between any two switches. See figure Ω Ω Ω Ω µ µ 3

4 PIA Electrical Specifications - Single +3V Supply (V CC = +3V ±%, = V, V H = 2.V, V L =.8V) Ω µ

5 PIA Typical Operating Characteristics (T A =+2ºC, unless otherwise noted) R ON vs. V RON vs. V and Temperature Vcc = +2V CC R ON ( Ω W ) V +7V (Ω) RON 12 8 A B C V (V) V ( V ) 2 Leakage Currents vs. Analog Voltage na Leakage Current vs. Temperature V CC = 1nA V CC = Leakage (pa) 8 I A(ON or IB(ON) I A(OFF) or IB(OFF) Leakage pa pa 1pA I (ON) I (OFF) -8.1pA N O, N C, V (V).1pA - 8 Temperature (ºC) ( C) º 1 Charge Injection vs. Analog Voltage - Crosstalk and Off-Isolation vs. Frequency Q-Charge Injection (pc) V CC = V V = 3V CC (db) V CC = Off Isolation Crosstalk V (V) Frequency (MHz)

6 PIA -1 Insertion Loss vs. Frequency Input Switching Threshold vs. Supply Voltage -2 Insertion Loss (db) dB Point V, (V) V CC = R L = WΩ Frequency (MHz) V CC (V) 2 R ON vs. V and Single Supply 2 Switching Times vs. Temperature 2 1 t ON, t OFF (ns) 1 t ON, t OFF ton t OFF (ns) t ON t OFF V CC (V) - 8 Temperature (ºC) Supply Current vs. Temperature Supply Current vs. Input Switching Frequency 1 V CC = V CC = 1.2 (n A).1 I CC (ma) 1..8 Icc Temperature ( C) Frequency (MHz) 6

7 PIA Test Circuits/Timing Diagrams Switch Input Logic Input +3V* NO or Vcc R L Ω C L 1pF V OUT Logic Input Switch Output +3V V V % t r <2ns t f <2ns t OFF V OUT 9% 9% t ON C L CLUDES FIXTURE AND STRAY CAPACITAE R V OUT = V L NO ( R L + R ON ) LOGIC PUT WAVEFORMS VERTED FOR SWITCHES THAT HAVE OPPOSITE LOGIC * 1.V FOR 3V SUPPLY Figure 1. Switching Time V G Logic Input R G NO or C L 1nF V OUT V OUT OFF OFF ON ON V OUT OFF OFF Q = ( V OUT )(C L ) Figure 2. Charge Injection 7

8 PIA Test Circuits/Timing Diagrams (continued) nf nf Signal Generator dbm 1 N1 ΩΩ W Ω Analyzer W Ω or NO V or 2.V Analyzer V or 2.V WΩ 2 NO2 WΩ Figure Off Isolation Figure Crosstalk nf nf Capacitance Meter f = 1kHz or NO V or 2.V Capacitance Meter f = 1kHz or NO V or 2.V Figure Channel-Off Capacitance Figure 6. Channel-On Capacitance nf R g= W Ω or NO Vcc Vo R L WΩ Figure Bandwidth 8

9 PIA Applications Information Positive Supply Overvoltage Protection Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings, because stresses beyond the listed ratings may cause permanent damage to the devices. Always sequence on first, followed by V-, and then logic inputs. If power-supply sequencing is not possible, add two small signal diodes or two current limiting resistors in series with the supply pins for overvoltage protection (Figure 8). Adding diodes reduces the analog signal range, but low switch resistance and low leakage characteristics are unaffected. V g NO V- Figure Overvoltage protection is accomplished using two external blocking diodes or two current limiting resistors. SVGA R-G-B S-Video Connector RGB to Composite Encoder Y Composite C Sync R G B Sync PIA R or Luma.7V G or Composite.71V B or Chroma.28V H-Sync-.3V VGA Connector Select Composite Connector 9

10 PIA Ω Ω with an unsurpassed Ω Stereo Audio Input From DAC Stereo Audio Output kwω J1 J2 32WΩ Select Enable Z3 2.V Z 2.V Vcc -3V -V Z1 Z2 Z1/Z2 - Dual SMT V Zener 22kWΩ -3V Pericom Semiconductor Corporation 238 Bering Drive San Jose, CA Fax (8) 3-1

11 Pericom Standard Packages and Dimensions HEIGHT PERI PACKAGE DRAWG JEDEC P PITCH LGTH WIDTH (max.) CODE TYPE NUMBER PUB 9 MILS MM MILS MM MILS MM MILS MM A TSSOP-8 PD-11 MO-13ED TSSOP-6 PD-12 MO-13EE BQSOP- PD-129 MO-1BB B BQSOP-8 PD-12 MO-1AB BQSOP-8 PD-1211 MO-1BC C SC7- PD-191 MO-23AA FA TQFP-32 PD-181 MS-C/ABA FB LQFP-32 PD-182 MS-C/BBA LQFP-2 PD-183 MS-C/BCC SSOP-1 PD-123 MO-1AB SSOP- PD-123 MO-1AC H SSOP-2 PD-12 MO-1AE SSOP-2 PD-12 MO-1AG SSOP-28 PD-12 MO-1AH J PLCC-32 PD- MO-2AE PLCC- PD-2 MO-7AC K TSSOP-8 PD-132 MO-19AE TSSOP-6 PD-132 MO-19AF TSSOP-8 PD-138 MO-13AA TSSOP-1 PD-139 MO-13AB L TSSOP- PD-13 MO-13AB TSSOP-2 PD-1311 MO-13AC TSSOP-2 PD-1312 MO-13AD TSSOP-28 PD-1313 MO-13AE NA PBGA-26 PD-21 MO LFBGA-11 PD-22 MO NB LFBGA-6 PD-23 MO LFBGA-96 PD-2 MO TFBGA-6 PD-2 MO-19B PDIP-8 PD-171 MS-1BA PDIP-1 PD-172 MS-1AA P PDIP- PD-173 MS-1AB PDIP-2 PD-17 MS-1AD PDIP-2 PD-17 MS-1AF PDIP-28 PD-176 MS-1AG QSOP- PD-121 MO-137AB Q QSOP-2 PD-122 MO-137AD QSOP-2 PD-123 MO-137AE QSOP-28 PD-12 MO-137AF R TSSOP-2 PD-131 N/ A TSSOP-2 PD-132 N/ A SOIC- PD- MS-13AA S SOIC-2 PD-6 MS-13AC SOIC-2 PD-7 MS-13AD SOIC-28 PD-8 MS-13AE T SOT23- PD-1911 EIAJ SC-7A SOT23-6 PD-1912 EIAJ SC-7A U MSOP-8 PD-11 MO-187AA V SSOP-8 PD-11 MO-118A A SSOP-6 PD-12 MO-118A B SOIC-8 PD-1 MS-12AA W SOIC-1 PD-2 MS-12AB SOIC- PD- MS-12AC Notes: 1. Dimensions are nominal and for reference only; specific min/max tolerances are available in the PD drawings, or per JEDEC Standard Outlines, Publication 9 Package height dimensions are maximum limits, from package top to the seating plane; length does NOT include mold flash of up to mils, depending on package type. 2. Assembly Materials: Leaded packages use Copper leadframe, spot silver plated~1µ inch in die attach area, semi-bright finish; adhesive Die Attach epoxy, gold wire thermosonic bonding, and epoxy novolac molding compound encapsulant. Lead finish is~8% Sn/1% Pb solder plate. BGA type packages use BT polymer substrate, adhesive die attach epoxy, gold wire thermosonic bonding, and epoxy novolac molding compound encapsulant. Solder balls are~63% Sn/37% Pb composition. Pericom reserves the right to substitute qualified and approved alternate materials when necessary, and which does not affect a products form, fit, function or reliability.

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