HIERARCHICAL MODELING FOR VLSI CIRCUIT TESTING

Transcription

1 HIERARCHICAL MODELING FOR VLSI CIRCUIT TESTING

2 Other books in the series: THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE VLSI, COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING Consulting Editor Jonathan Allen Logic Minimization Algorithms for VLSI Synthesis. R.K. Brayton. G.D. Hachtel. C.T. McMullen. and Alberto Sanngiovanni-Vincentelli. ISBN Adaptive Filters: Structures. Algorithms. and Applications. M.L. Honig and D.G. Messerschmitt. ISBN Introduction to VLSI Silicon Devices: Physics. Technology and Characterization. B. EI-Kareh and R.1. Bombard. ISBN Latchup in CMOS Technology: The Problem and Its Cure. R.R. Troutman. ISBN Digital CMOS Circuit Design. M. Annaratone. ISBN The Bounding Approach to VLSI Circuit Simulation. C.A. Zukowski. ISBN Multi-Level Simulation for VLSI Design. D.D. Hill and D.R. Coelho. ISBN Relaxation Techniques for the Simulation of VLSI Circuits. J. White and A. Sangiovanni-Vincentelli. ISBN X. VLSI CAD Tools and Applications. W. Fichtner and M. MorC Editors. ISBN A VLSI Architecture for Concurrent Data Structures. W.1. Dally. ISBN Yield Simulation for Integrated Circuits. D.M.H. Walker. ISBN VLSI Specification. Verification and Synthesis. G. Birtwistle and P.A. Subrahmanyam. ISBN Fundamentals of Computer-Aided Circuit Simulation. W.J. McCalla. ISBN Serial Data Computation. S.G. Smith. P.B. Denyer. ISBN X. Phonologic Parsing in Speech Recognition. K.W. Church. ISBN Simulated Annealing for VLSI Design. D.F. Wong. H.W. Leong. c.l. Liu. ISBN Polycrysta/line Silicon for Integrated Circuit Applications. T. Kamins. ISBN FET Modeling for Circuit Simulation. D. Divekar. ISBN VLSI Placement and Global Routing Using Simulated Annealing. C. Sechen. ISBN Adaptive Filters and Equalizers. B. Mulgrew. C.F.N. Cowan. ISBN Computer-Aided Design and VLSI Device Development. Second Edition. K.M. Cham. S-Y. Oh. J.L. Moll. K. Lee. P. Vande Voorde. D. Chin. ISBN: Automatic Speech Recognition. K-F. Lee. ISBN Speech Time-Frequency Representations. M.D. Riley. ISBN X. A Systolic Array Optimizing Compiler. M.S. Lam. ISBN: Algorithms and Techniques for VLSI Layout Synthesis. D. Hill. D. Shugard. J. Fishburn. K. Keutzer. ISBN: Switch-Level Timing Simulation of MOS VLSI Circuits. V.B. Rao. D.V. Overhauser. T.N. Trick. LN. Hajj. ISBN VLSI for Arti/iciall1!te/ligence. J.G. Delgado-Frias. W.R. Moore (Editors). ISBN Wafer Level Integrated Systems: Implementation Issues. S.K. Tewksbury. ISBN The Annealing Algorithm. R.H.J.M. Otten & L.P.P.P. van Ginneken. ISBN VHDL: Hardware Description and Design. R. Lipsett. C. Schaefer and C. Ussery. ISBN X. The VHDL Handbook. D. Coelho. ISBN Unified Methods for VLSI Simulation and Test Generation. K.T. Cheng and V.D. Agrawal. ISBN ASIC System Design with VHDL: A Paradigm. S.S. Leung and M.A. Shanblatt. ISBN BiCMOS Technology and Applications. A.R. Alvarez (Editor). ISBN Analog VLSllmplementation of Neural Systems. C. Mead and M. Ismail (Editors). ISBN The MIPS-X RISC Microprocessor. P. Chow. ISBN Nonlinear Digital Filters: Principles and Applications. I. Pitas and A.N. Venetsanopoulos. ISBN Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. D.E. Thomas, E.D. Lagnese. R.A. Walker. J.A. Nestor. J.V. Rajan. R.L. Blackburn. ISBN VLSI Design for Manufacturing: Yield Enhancement. S.W. Director. W. Maly. A.J. Strojwas. ISBN Testing and Reliable Design of CMOS Circuits. N.K. 1ha. S. Kundu. ISBN

3 HIERARCHICAL MODELING FOR VLSI CIRCUIT TESTING by Debashis Bhattacharya Yale University and John P. Hayes The University of Michigan.., ~ KLUWER ACADEMIC PUBLISHERS Boston/Dordrecht/London

4 Distributors for North America: Kluwer Academic Publishers 101 Philip Drive Assinippi Park Norwell, Massachusetts USA Distributors for all other countries: K1uwer Academic Publishers Group Distribution Centre Post Office Box AH Dordrecht, THE NETHERLANDS Library of Congress CataJoging-in-Publication Data Bhattacharya, Debashis, Hierarchical modeling for VLSI circuit testing / by Debashis Bhattacharya, John P. Hayes. p. cm. - (The Kluwer international series in engineering and computer science. VLSI, computer architecture, and digital signal processing.) ISBN-13: e-isbn-13: : / I. Integrated circuits-very large scale integration-testing. 2. Integrated circuits- Very large scale integration-computer simulation. I. Hayes, John P. (John Patrick), II. Title. III. Series. TK '5 '0287-dc CIP Copyright 1990 by Kluwer Academic Publishers Softcover reprint of the hardcover 1st edition 1990 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmined in any form or by any means, mechanical, photocopying, recor ding, or otherwise, without the prior written permission of the publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts

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6 TABLE OF CONTENTS Preface ix 1 INTRODUCTION 1.1 BACKGROUND 1.2 PRIOR WORK Test Generation for Combinational Circuits Test Generation for Sequential Circuits High-level Test Generation Fault Simulation Design for Testability OUTLINE CIRCUIT AND FAULT MODELING VECTOR SEQUENCE NOTATION CIRCUIT AND FAULT MODELS Circuit Model Fault Model CASE STUDY: k-regular CIRCUITS 48 3 HIERARCHICAL TEST GENERATION VECTOR CUBES TEST GENERATION Repetitive Circuits Pseudo-Sequential Circuits High-Level Test Generation Algorithm IMPLEMENTATION AND EXPERIMENTAL RESULTS Circuit Description Data Structures Program Structure Experimental Results DESIGN FOR TESTABILITY 4.1 AD HOC TECHNIQUES Array-Like Circuits

7 viii Tree-Like Circuits LEVEL SEPARATION (LS) METHOD Functions Realizable by One-Dimensional ILA's Functions Realizable by Two-Dimensional ILA's CASE STUDY: ALU CONCLUDING REMARKS SUMMARy FUTURE DIRECTIONS. 131 APPENDIX A: PROOFS OF THEOREMS A.1 PROOF OF THEOREM 3.2 A.2 PROOF OF THEOREM 3.3 A.3 PROOF OF THEOREM 4.1 BIBLIOGRAPHY Index

8 Preface Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing problem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models. This provides a direct way for comparing the high-level method to conventional low-level approaches. It also makes the approach truly hierarchical-a unique and useful feature. We then develop a systematic test generation algorithm for bus faults in high-level circuits, which we have implemented in a computer program called VPODEM. In addition to presenting a theory of hierarchical modeling and testing, the book also describes the results of experiments that apply VPODEM to various types of logic circuits. These results indicate that the high-level approach alone can produce test sets with good coverage of SSL faults. The tests sets are also smaller and require less test generation effort than traditional methods, especially when the circuits being tested are moderately or highly regular. Moreover, by using VPODEM hierarchically to generate tests for any SSL faults not covered by the high-level analysis alone, 100 percent coverage of all detectable faults can can be guaranteed for any circuit. We also report

9 x some new design-for-testability methods to make circuits more amenable to the high-level testing methodology. This work should be of interest to circuit designers, test engineers, and others concerned with the testing of complex digital systems. To make the book self-contained, we have included a short tutorial on traditional testing problems and approaches in Chapter 1. Our high-level circuit and modeling techniques are developed in Chapter 2, along with a suitable notation for describing the behavior of hierarchical systems. The test generation algorithm and its implementation (VPODEM) are covered in Chapter 3, and an experimental evaluation of VPODEM's performance is presented. Chapter 4 proposes methods to enhance the testability of digital circuits at the high level. Chapter 5 summarizes the book and suggests some directions for future research. Most of the material in this book was developed over the past few years as part of the first author's Ph.D. dissertation research at the University of Michigan. This research was supported by a grant from the National Science Foundation and by a fellowship from International Business Machines Corporation. We wish to express our gratitude to both of these organizations. Thanks are also due to Daniel E. Atkins, Ronald J. Lomax, John F. Meyer and Trevor N. Mudge of the University of Michigan for their comments, as well as to Virginia Folsom for secretarial assistance.

10 HIERARCHICAL MODELING FOR VLSI CIRCUIT TESTING