TIMING ANALYSIS AND OPTIMIZATION OF SEQUENTIAL CIRCUITS

Transcription

1 TIMING ANALYSIS AND OPTIMIZATION OF SEQUENTIAL CIRCUITS

2 TIMING ANAL YSIS AND OPTIMIZATION OF SEQUENTIAL CIRCUITS Naresh Maheshwari Iowa State University Sachin S. Sapatnekar University of Minnesota ~. " SPRINGER SCIENCE+BUSINESS MEDIA, LLC

3 ... " Library of Coogress Catalogiog-io-Publicatioo Data Maheshwari, Naresh, Timing analysis and optimization of sequential circuits I Naresh Maheshwari, Sachin S. Sapatnekar. p.cm. lnc1udes bibliographical references and index. ISBN ISBN (ebook) DOI / lntegrated circuits-very large scale integration-design and construction-data processing. 2. Computer-aided design. 3. Time-series analysis-data processing. 1. Sapatnekar, Sachin S., D. Title. TK M '5--dc CIP Copyright 1999 by Springer Science+Business Media New York Second printing Originally published by Kluwer Academic Publishers in 1999 Softcover reprint of the hardcover lst edition 1999 AII rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any fonn or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written pennission of the publisher, Springer Science + Business Media. LLC. Printed on acid1ree paper.

4 Dedicated to our parents

5 Clock. n.: A machine of great moral value to man, allaying his concern for the future by reminding him what a lot of time remains to him. A mbrose Bierce in "The Devil's Dictionary"

6 Contents List of Figures Preface ix XIII 1. INTRODUCTION Performance Optimization of VLSI Circuits Outline of the Book 5 2. TIMING ANALYSIS OF SEQUENTIAL CIRCUITS Introduction Combinational Delay Modeling Clocking Disciplines: Edge-Triggered Circuits Resolving Short Path Violations Clocking Disciplines: Level-clocked Circuits Clock Schedule Optimization for Level-Clocked Circuits Timing Analysis of Domino Logic Concluding Remarks CLOCK SKEW OPTIMIZATION The Notion of Deliberate Clock Skew Is Clock Skew Optimization Safe? Clock Tree Construction Clock Skew Optimization Clock Skew Optimization with Transistor Sizing Wave Pipelining Issues Deliberate Skews for Peak Current Reduction Conclusion THE BASICS OF RETIMING Introduction to Retiming A Broad Overview of Research on Retiming Modeling and Assumptions for Retiming Minperiod Optimization of Edge-triggered Circuits 74

7 viii TIMING ANALYSIS AND OPTIMIZATION OF SEQUENTIAL CIRCUITS 4.5 Level-clocked Circuits Concluding Remarks MINAREA RETIMING The Leiserson-Saxe Approach The Minaret Algorithm Minarea Retiming of Level-Clocked Circuits RETIMING CONTROL LOGIC Minperiod Initial State Retiming via the State Transition Graph Minperiod Initial State Retiming via Reverse Retiming Minarea Initial State Retiming Maintaining Initial States With Explicit Reset Circuitry MISCELLANEOUS ISSUES IN RETIMING Retiming and Testing Verification Issues Retiming for Low Power Retiming with Logic Synthesis Retiming for FPGA's Practical Issues Conclusion CONCLUSION 169 References 171

8 List of Figures 1.1 A typical area-delay tradeoff curve in transistor sizing A general sequential circuit. S 2.2 An example of a pipelined system. S 2.3 Illustration of the clocking parameters for a register An example of a composite cell An example of an RC tree The Critical Path Method (CPM) Circuit delays obtained from the Critical Path Method Example illustrating the advantages of using level-sensitive latches Phase i of a k-phase clock with all times relative to the local time zone Illustration of the phase shift operator A typical domino circuit An Example Circuit The advantage of nonzero clock skew The perils of zero skew H-tree layout for clocking Zero-skew merge of two subtrees [Tsa93] 1993 IEEE A merging segment between two points, with x = t) A combinational block in a sequential circuit Double-clocking Zero-clocking Example illustrating the importance of combining sizing and skew optimization An example illustrating symbolic delay propagation algorithm A model of a synchronous sequential circuit Clock network routing considerations Modified CPM Illustrating the idea of wave pipelining An example illustrating logic signal separation constraints. 61

9 x TIMING ANALYSIS AND OPTIMIZATION OF SEQUENTIAL CIRCUITS 4.1 Effect of retiming on clock period Effect of retiming on number of registers Equivalent initial states in reverse retiming A correlator circuit Graph model of the correlator example Retimed graph of the correlator An example of a circuit with long path violation Using clock skew to correct the long path violation Retiming for clock period reduction Relationship between retiming and skew An example circuit ASAP retiming of the example circuit, with the ASAP constraint graph ALAP retiming of the example circuit, with the ALAP constraint graph Effective skews at FF's after ASAP retiming across a gate Example illustrating the change in the critical path with the clock period IEEE The latch shift operator The ability of a latch to absorb some skew Worst-case situation for remaining skew Unconditional register sharing at multiple fanouts Model for maximum register sharing at multiple fanouts Possible FF locations after retiming Example illustrating the approach An example circuit Retiming for clock period optimization Alternate retiming for clock period optimization (a) Original circuit. (b) Retimed circuit Forward retiming of a combinational logic node IEEE Example of an impossible retiming IEEE Adding minimal reset logic to make the retiming possible IEEE Retiming of the modified circuit IEEE Determining the retimed circuit that preserves the initial state IEEE Conventional minarea retiming Example of variation in the number of FF's with the initial state Another example of variation in the number of FF's with the initial state An example circuit where lower bound r is achievable A min area retiming without an equivalent initial state A minarea retiming with an equivalent initial state. 131

10 LIST OF FIGURES xi 6.13 Effect of justification choices on the number of FF's An example of a pruning technique Conditional register sharing at multiple fanouts An example of FF sharing An example of positive retiming An example of negative retiming The reset mapping IEEE Explicit reset circuitry Retiming using an explicit reset IEEE Effect of retiming on sequentially redundant faults: (a) the initial circuit, and (b) the retimed circuit IEEE Example illustrating the effect of forward retiming on replaceability Retiming structures with gated clocks IEEE Retiming precharged logic structures IEEE Effect of FF sharing on delay. 166

11 Preface While a decade ago, most books related to integrated circuits began with the phrase, "With the increasing complexity of VLSI circuits...," the new and trendy catch-phrase today is "deep submicron effects." Both of these phrases have been the subject of numerous jests, but it is undeniably true that with the increasing complexity of VLSI circuits and the onset of deep submicron effects, circuit design is becoming more complex. In such an environment, a paradigm shift is being seen, leading to the need for a more synergistic interaction between designers and CAD tools. Our excellent spies tell us that the preceding words will not be applauded 1 [ by the engineers for whom this book is written, and therefore, we feel obligated to switch from the language of Dilbert cliches to plain English. On the performance front, there is a vital need for techniques to design fast, low power chips with the minimum area for increasingly complex systems, while on the economic side, there is the vastly increased pressure of time-to-market. This book considers the problem of analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. The state of the art in analysis and optimization techniques are described for circuits using edge-triggered or level-sensitive memory elements. The introductory chapter overviews techniques used for performance optimization of combinational and sequential circuits. Chapter 2 describes the edge-triggered and level-triggered clocking disciplines, and compares the two in terms of their relative advantages and disadvantages. Edge triggered circuits are relatively easier to design since they effectively decouple individual combinational blocks and reduce the complexity of the design, and this chapter begins with an overview of some efficient timing analysis techniques for edge-triggered circuits. The design of level-clocked circuits is more complicated than edgetriggered circuits, but offers significant performance enhancements in terms of reductions in area and the ability to operate at higher clock frequencies. The

12 xiv TIMING ANALYSIS AND OPTIMIZATION OF SEQUENTIAL CIRCUITS CAD techniques for clock period verification are correspondingly more computationally expensive. In the next part of the chapter, the state of the art in methods for formulation clocking constraints and verifying the correctness of a clocking discipline is described, followed by a discussion of clock schedule optimization and timing analysis methods for domino circuits. Chapter 3 describes a technique proposed for improving the circuit behavior, where the clocking network is designed to permit nonzero skews at the flip-flops/latches. A good amount of research has been carried out in this area in the recent past, and it has been found to give large improvements in the circuit performance. After motivating the section with an outline of the potential benefits of deliberate skew, a linear program formulation for optimal skew calculation is described. Next, the process of combining skew optimization with gate sizing, a circuit optimization technique, is detailed. Other applications of deliberate skews are also outlined, followed by a discussion on the design of clocking networks to provide deliberate nonzero skews. Chapters 4 and 5 deal with retiming, a technique used to improve the performance of the circuit by relocating memory elements. While the concept and a problem solution approach were first outlined in 1983, there has been a flurry of work in the last few years and this method has been transformed from a theoretically interesting, yet computationally expensive technique to one that can handle practical circuit sizes of tens of thousands of gates in minutes. Chapter 6 addresses the issue of retiming in finite state machines where it is important to retain the initial state of a circuit, or where the power-on states should remain the same. Several new algorithms for each of these problems have been proposed in the recent past, and these are described here. Finally, in Chapter 7, the application of retiming to aid other optimizations is described. The authors would like to acknowledge a number of sources. Thanks are due to all of the graduate students in our research group and collaborators who have worked on problems related to those discussed in this book. In particular, the work of Weitong Chuang, Rahul Deokar and Harsha Sathyamurthy has contributed greatly to our progress in this area. We would like to acknowledge our collaborators, Professor Ibrahim Hajj at the University of Illinois, and Jack Fishburn at Bell Labs. Jack has been a major source of inspiration to the second author in this work, and a special vote of thanks is due to him. We are grateful to Liang-fang Chao, Madhav Desai, Tony Drumm, Narendra Shenoy and Bapi Vinnakota for several discussions. Professor Sudhakar Reddy introduced us to test issues in retiming, and we are grateful to him for this. We would also like to thank Mahesh Ketkar for his efforts; his careful proofreading of the book has saved us from several major embarrassments. The work on this book was carried out at Iowa State University and at the University of Minnesota. We owe a debt of gratitude to the faculty, students and staff of both institutions for their support. We would also like to acknowledge the financial support of our funding agencies, specifically the National Science Foundation (contracts MIP and MIP ), the Semiconductor Research Corporation (contract 98-DJ-609), Intel Corporation, Digital Equipment

13 PREFACE xv Corporation, Cadence Design Systems, and a Lucent Technologies/DAC Graduate Scholarship. The first author thanks IBM for the opportunity to work with them over two summers. The credits for the cover are due to the excellent graphic designers at the University of Minnesota Printing Services. The help of Carl Harris and the staff at Kluwer Academic Publishers is also acknowledged. Last, but not the least, we would like to thank our family and friends for their support. Although we have attempted to provide a reasonably thorough overview of sequential timing optimization methods, we are acutely aware that no such effort can be entirely complete. We would like to apologize, in advance, for any omissions or errors and attribute them to the human factor. In closing, we reproduce an appropriate quotation from Jean de la Bruyere: "Making a book is a craft, as is making a clock." We hope that our craftsmanship is of adequate quality. N ARESH MAHESHW ARI SACHIN SAPATNEKAR