PIPELINED LATTICE AND WAVE DIGITAL RECURSIVE FILTERS

Transcription

1 PIPELINED LATTICE AND WAVE DIGITAL RECURSIVE FILTERS

2 THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE

3 PIPELINED LATTICE AND WAVE DIGITAL RECURSIVE FILTERS by Jin-Gyun Chung Chonbuk National University Keshab K. Parhi University of Minnesota... " KLUWER ACADEMIC PUBLISHERS Boston / Dordrecht / London

4 Distributors for North America: Kluwer Academic Publishers 101 Philip Drive Assinippi Park Norwell, Massachusetts USA Distributors for all other countries: Kluwer Academic Publishers Group Distribution Centre Post Office Box AH Dordrecht, THE NETHERLANDS Library of Congress Cataloging-in-Publication Data A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN-13: DOl: / e-isbn-13: Copyright 1996 by Kluwer Academic Publishers Softcover reprint of the hardcover 1 st edition 1996 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts Printed on acid-free paper.

5 To Hyunseon, Eunseon and Heeshim To Corinne

6 CONTENTS PREFACE 1 INTRODUCTION 1.1 Background 1.2 Iteration Bound and Retiming 1.3 Pipelining 1.4 Outline 2 PIPELINE INTERLEAVING IN DIGITAL FILTERS 2.1 Inefficient Single/Multi-Channel Interleaving 2.2 Efficient Single-Channel Interleaving 2.3 Efficient Multi-Channel Interleaving Xl PIPELINING DIRECT FORM RECURSIVE DIGITAL FILTERS 3.1 Clustered Look-Ahead Pipelining 3.2 Stable Clustered Look-Ahead Filter Design 3.3 Scattered Look-Ahead Pipelining Without Decomposition 3.4 Scattered Look-Ahead Pipelining with Power-of-Two Decomposition 3.5 Scattered Look-Ahead Pipelining With General Decomposition 3.6 Constrained Filter Design Techniques 3.7 Linear Bidirectional Systolic Array Architectures 3.8 FIR versus IrR Filters 3.9 Pipelining in State Space Filters

7 PIPELINED LATTICE AND WAVE DIGITAL RECURSIVE FILTERS 3.10 Low-Power Direct Form Filters 46 4 ROUNDOFF NOISE IN PIPELINED RECURSIVE DIGITAL FILTERS Introduction Scaling and Roundoff Noise SVD of IIR Filters Scaling and Roundoff Noise Computation Using SVD Roundoff Noise in Pipelined IIR Filters Roundoff Noise Computation Examples Using SVD 74 5 SCHUR ALGORITHM Introduction Computation of Schur Polynomials An Inner Product Formulation Orthogonality of Schur Polynomials Orthonormality of Schur Polynomials ti - j) Orthonormality of Reverse Schur Polynomials Polynomial Expansion Algorithm Power Calculation Using Schur Algorithm 91 6 DIGITAL LATTICE FILTER STRUCTURES Introduction Derivation of Basic Lattice Filter Derivation of One-Multiplier Lattice Filter Derivation of Normalized Lattice Filter Derivation of Scaled Normalized Lattice Filter Roundoff Noise Calculation in Lattice Filters PIPELINING OF LATTICE I1R DIGITAL FILTERS Introduction Pipelining Property of the Schur Algorithm Pipelining of Lattice IIR Digital Filters Design Examples of Pipelined Lattice Filters Pipelining Lp.vels and Output Roundoff Noise 140

8 Contents 7.6 Low-Power CMOS Implementation of Lattice IIR Filters PIPELINING OF ORTHOGONAL DOUBLE-ROTATION DIGITAL LATTICE FILTERS Introduction Synthesis of ODR Digital Lattice Filters Pipelining of ODR Digital Lattice Filters Examples of Pipelined ODR Digital Lattice Filters PIPELINED LATTICE WDF DESIGN FOR WIDEBAND DIGITAL FILTERS Introduction Direct Lattice WDF Synthesis in Digital Domain Roundoff Noise Characteristics of WDFs Pipelining by DIFIR Method MF FIR and Linear Phase IIR Filters Examples of Pipelined Lattice WDFs SYNTHESIS AND PIPELINING OF LADDER WDFS IN DIGITAL DOMAIN Introduction Classical Doubly-Terminated Lossless Network WDF Adaptors Synthesis of Ladder WDFs Synthesis of Pipelinable Ladder WDFs 190 A APPENDIX A: DERIVATION OF (3.3), (3.5) AND (3.23) 199 A.1 Definition of ri in (3.3) 199 A.2 Pipelining with Clustered Look-Ahead 200 A.3 Derivation of (3.23) 202 B DERIVATION OF CASE (A) IN SECTION

9 PIPELINED LATTICE AND WAVE DIGITAL RECURSIVE FILTERS C DERIVATION OF CASE (E) IN SECTION C.l General 207 C.2 Computation of C.3 Computation of 102 and C.4 Computation of III 209 REFERENCES 211

10 PREFACE Recursive or infinite impulse response (IIR) digital filters are used in large number of applications. Typically, a filter spectrum can be met with a much lower order IIR filter than FIR (finite impulse response). However, IIR digital filters are more difficult to design (especially for linear phase); these also suffer from roundoff and quantization noise and limit cycles. Therefore, study of IIR filter topologies which are less sensitive to roundoff and quantization noise is important. Furthermore, in VLSI implementations, study of properly scaled structures is important since these systems can be implemented using the same word-length for all the signals in the entire system. In addition to noise behavior, other hardware related performance issues such as speed, area and power need to be considered. To this end, study of pipelined digital filter topologies is important. Pipelining involves placing latches at appropriate locations and reduces critical path. This leads to an increase in the clock rate as well as signal sample rate. Alternatively, where achieving high speed is not important, the pipelined topologies can be operated with lower supply voltage for lower power. Low power consumption is extremely important in portable applications for increasing battery life. While FIR digital filters can be pipelined at arbitrary levels, recursive digital filters cannot be easily pipelined due to the presence of feedback loops. Thus, design of pipelined topologies for recursive digital filters is a challenge. In the past, there was no need to design pipelined filter topologies because the concurrency due to pipelining could not be exploited in microprocessors or programmable digital signal processors. The innermost loop in all recursive signal processing algorithms contains one delay operator since these are designed for sequential implementation in software programmable processors. However, pipelining can be easily exploited in VLSI implementations of digital filters. This book presents pipelined topologies for several types of recursive digital filters using look-ahead transformation and constrained filter design approaches. It is also shown that pipelining often reduces the roundoff noise in a digital filter. The pipelined recursive lattice and wave digital filters presented in this book are well suited where increasing speed and reducing area or power or roundoff noise are important. These are ideal for wireless and cellular co dec applications where low power consump-

11 PIPELINED LATTICE AND WAVE DIGITAL RECURSIVE FILTERS tion is important and in radar and video applications where higher speed is important. The outline of the book is as follows. In Chapter 2, we discuss pipeline interleaving in recursive filters for filtering of multiple channels simultaneously. Chapter 3 presents pipelining of direct-form recursive digital filters and demonstrates the usefulness of these topologies in high-speed and low-power applications. Chapter 4 discusses fundamentals of scaling in digital filters and analyzes the roundoff noise of the pipelined direct-form filters. Chapter 5 addresses Schur polynomials which form the basis of design for lattice and wave digital filters. Chapter 6 presents approaches to designing four different types of lattice digital filters which include basic, one-multiplier, normalized, and scaled normalized structures. The roundoff noise in these lattice filters is also studied in this chapter. Chapter 7 presents approaches to design pipelined lattice digital filters for the same four types of structures. Chapter 8 presents pipelining of orthogonal double-rotation digital filters which eliminate limit cycle problems. Chapter 9 presents pipelining of lattice wave digital filters and shows how linear phase narrow-band sharp-transition recursive filters can be implemented using this structure. This example is motivated by a difficult filter design problem in a wireless codec application. Chapter 10 presents pipelining of ladder wave digital filters. The topics presented in this book were developed during 1985 to During these ten years, the authors were influenced and encouraged by large number of people to whom they remain grateful. They are especially indebted to David G. Messerschmitt who took early interest in VLSI digital filters, Mos Kaveh, Sayfe Kiaei who provided the wireless codec example in Chapter 9, Hojun Kim, and Michael Soderstrand. They appreciate the help received from Santosh Misra and Bin Fu in preparation of part of Chapter 4 and from Tracy Denk in proofreading. Thanks are also due to Bill Sander of the Army Research Office and John Cozzens of the National Science Foundation for their support of the research that led to this book. They thank Bob Holland of Kluwer Academic Publishers for his invitation to write this book.

12 PIPELINED LATTICE AND WAVE DIGITAL RECURSIVE FILTERS

13 1 INTRODUCTION 1.1 BACKGROUND In order to exploit VLSI for high performance, we need to understand the characteristics of the scaled VLSI technologies. For example, VLSI offers a greater potential for complexity than speed, favors replication of one function, and imposes a high cost in performance for non-localized communication. Design costs can be minimized by composing the system as a replication of simple processing elements. These considerations favor implementations which feature arrays of identical or easily parametrized processing elements (since, these are easily given a software procedural definition) with mostly localized interconnections (for reduced communication costs). This has led to an interest in systolic- and wavefront-array implementations [1, 2]. High performance can be achieved by using exotic high speed technologies, such as bipolar or GaAs which allow us to gain performance without modification of the algorithm. On the other hand, we can use a low cost VLSI technology such as CMOS and yet gain impressive performance by exploiting concurrency. Concurrency is usually manifested in the form of pipelining or parallelism or both. Concurrent architectures can be derived by implementing the existing algorithms in new ways. To be more precise, we do not change the transfer function or the input-output characteristics of the algorithm, but we do change the internal structure of the algorithm, thereby impacting the finite precision effects but nothing else. This is referred to as recasting the structure of the algorithm. Different forms of recasting a specified algorithm can lead to realizations with entirely different properties and implementation complexities. In this book, we show that appropriate recasting of the structure of an algorithm can have a dramatic effect on the performance of an implementation. 1

14 2 CHAPTER 1 The challenge in achieving high performance implementations is mostly in recursive systems, since as we will see, the recursion or the internal feedback negates the most obvious ways of improving performance. This is because the computational latency associated with the feedback loop in recursive systems limits the opportunities for pipelining and/or parallel processing. In nonrecursive systems, we can place latches across any feed-forward cutset without changing the transfer function (at the expense of latency) and achieve the desired level of pipelining. However, recursive systems cannot be pipelined at an arbitrary level by simply inserting latches, since the pipelining latches would change the number of delay operators in the loop, and hence the transfer function of the implementation. We can overcome this recursive bottleneck by changing the internal structure of the algorithm to create additional logical delay operators inside the recursive loop, which can then be used for pipelining. High sampling rate realizations of recursive digital filters using block processing have been suggested [3]-[18]. In block processing, input samples are processed in the form of non-overlapping blocks and outputs are also generated block by block. Thus, we can increase the block size (i.e., the number of samples in a block) arbitrarily to achieve arbitrarily high sampling rate recursive system realizations. The best known block structure reported so far for recursive digital filtering requires a linear multiplication complexity with respect to the block size. The block state update operation as well as the pipelined state update operation in recursive filters belong to the class of look-ahead computation techniques [19, 20]. In this book, we only discuss the pipelining approach. The block processing and fine-grain pipelined block processing approaches are addressed in [18]. The issue of low-power implementation is of great concern due to the increasing demand for high performance portable products. The power consumption in CMOS circuits is proportional to the square of the supply voltage. Therefore, for a quadratic improvement in the power consumption, it is necessary to reduce the supply voltage. However, we should pay a speed penalty for the supply voltage reduction. In [21, 22], it was shown that pipelining or block processing can successfully be used to restore the performance degradation caused by reduced supply voltage. In addition to the high throughput and low-power consumption, finite wordlength effect is one of the most important factors to be considered in VLSI implementations. When a digital filter transfer function is implemented using fixed-point arithmetic, it invariably involves quantization of signals and coefficients due to the finite word-length of the digital system. As a result, the overall input-output behavior is not ideal. Therefore, much research has been

15 Introduction 3 carried out to search for low-sensitivity or low-noise structures such as basic and normalized lattice filters [23, 24], scaled normalized lattice filters [25]-[27], ODR (orthogonal double-rotation) digital lattice filters [28], and WDFs (Wave Digital Filters) [29]-[32]. In this book, we study efficient pipelining of IIR direct-form and low-sensitivity structures such as lattice and WDFs. This chapter is organized as follows. Section 1.2 reviews iteration bound and retiming. Section 1.3 discusses the applications of pipelining and look-ahead pipelining techniques. The outline of this book is given in section ITERATION BOUND AND RETIMING Iteration Bound Any digital system involving loops or recursions has a lower bound on the achievable iteration period, referred to as the iteration period bound, or simply the iteration bound [33,34]. It is not possible to achieve an iteration period less than the iteration bound; this bound is fundamental to a specific algorithm and is independent of the number of processors available. The iteration bound is given by the maximum of the loop bounds over all the loops in a digital system. The loop bound is defined as the total computation time of the loop divided by the number of delays inside the loop. The loop, for which the loop bound is same as the iteration bound, is referred to as the critical loop. As an example, consider the DFG (Data Flow Graph) in Fig The nodes (A, B, and C) in the DFG represent instructions or tasks. The directed arcs represent communication between the nodes and have delays (D) associated with them. These delays represent memory or states in the DFG. The DFG in Fig. 1.1 has three loops denoted as L 1, L 2, and L 3 The loop bounds are 20, 30, and 10, respectively. Therefore, the iteration bound is 30 units and the lower bound on the feasible iteration or sample period is 30 units. The iteration period bound can be improved by increasing either the number of pipeline stages inside the recursive loop, the block size, or both. Since, pipelined realizations can be achieved with less increase in hardware (as opposed to linear increase as in block processing), it is hardware efficient to use pipelined algorithms first for high speed IIR filter implementations, and then combine block processing with pipelining only if sufficient speed cannot be generated

16 4 CHAPTER 1 20 o Fig.1.1 A DFG: the node computation times for A, B, and C are respectively 10, 20, and 30 units. ~ -2 Z-2 Z-1 ~~ /> Fig. 1.2 The delays on the incoming edges are reduced by one, while increasing the delays on the outgoing edges by one. by using pipelining alone_ Thus, block processing in itself is not an efficient way for implementing high speed custom IIR digital filters. However, block processing is useful for software programmable implementations on generalpurpose coarse-grain multiprocessors Retiming The process of retiming involves moving around the delays in a circuit such that the total number of delays in any loop remains unaltered, and the inputoutput behavior of the system is preserved [1, 35]. Removal of a fixed number of delays from each of the incoming edges of any node, and addition of the same fixed number of delays to each of the outgoing edges of the same node is a basic retiming operation. An example is shown in Fig (Throughout this book, "D" and "Z-l" are used interchangeably to represent a delay.) By repeatedly applying the basic retiming operation, delays can be moved to the desired locations such that the critical path of the circuit is minimized. For example, the sample rate of the circuit in Fig. 1.3-(a) is limited by one multiplication and one addition. However, the two delays in the loop can be

17 Introduction 5 a u(n) 1.. Cf y(n) ~ (a) u(n) y(n) (b) Fig.1.3 (a) A recursive circuit before retiming. (b) The circuit after retiming. The two delays have been distributed such that the critical path is halved. distributed such that the critical path is halved as shown in Fig. 1.3-(b). In Fig. 1.3-(b), the multiply and add circuit of Fig. 1.3-(a) is divided into two parts ml and m2 such that the computation time of ml is approximately the same as that of m2. Then one delay is moved forward to a point between ml and m2. This results in an increase of clock speed by a factor of two since the critical path has been halved. 1.3 PIPELINING In this section, it is shown that the pipelining technique can be used for high speed or low-power consumption. Notice that the pipelining technique can also be used for area reduction when it is combined with the folding technique [36]. Finally, look-ahead pipelining methods are briefly introduced.

18 6 CHAPTER 1 register 1 logic 1 register 2 logic 2 register M logic M ] segment 1 ] segment 2 ] segment M OUT Fig. 1.4 An M level pipelined data path High Sample Rate Application In a nonpipelined data path, only a fraction of the hardware is actively involved in data processing at any particular time. As a result, the next input data cannot be fed into the circuit until the processing of current input data is complete. For example, if the computation time of the nonpipelined data path is To, next input data sample can be fed into it only after To units of time. By M level pipelining, the data path is separated into M segments by inserting registers as shown in Fig If we assume that the computation time of each segment is the same, then the computation time of each segment, Tp, is given by: (1.1) Therefore, if Tr is the response time of each pipelining register, the pipelined data path may be clocked with clock period Tp + Tr units of time. As a result next input data samples can be fed into the pipelined circuit after Tp + Tr units of time. In most cases, we can disregard Tr since Tp» Tr. Therefore, the pipelined data path can be clocked approximately M times faster than the

19 Introduction 7 u v-o--v+au u(n) , o~ cb~.csj J- D x(n) (a) u(n)----, o~ cb.& MDJx(n) (b) Fig. 1.5 (a) A first order recursive filter and (b) The first order recursive filter with (M - 1) inserted registers. nonpipelined one. This increase in throughput has been made at the expense of increased output latency and hardware complexity. It may be noted that while pipelining increases system latency, retiming does not alter the system latency. In a recursive filter, the output is a function of its previous outputs. Therefore, recursive filters cannot be pipelined at an arbitrary level by simply inserting registers. Consider a first-order recursive filter described by x(n + 1) = ax(n) + bu(n), (1.2) and shown in Fig. 1.5-(a). The next state x(n + 1) is computed by multiplying the current state x(n) by a and then adding the product to bu(n). Consider obtaining an M level pipelined version of this implementation by inserting (M - 1) additional registers inside the loop as shown in Fig. 1.5-(b).

20 8 CHAPTER 1 The clock period of this implementation can be reduced by M times since, by the application of retiming, the critical path can be reduced by M times. However, as is clear from the Fig. l.5-(b), x(n + 1) is available only M clock cycles after x(n) and u(n) are available. Thus, the sample u(n + 1) can be input only M cycles after u(n) is input. As a result, the sample period of the implementation will increase to M clock periods, and there is no improvement in sample rate Low-Power Application The issue of low-power design is of great concern, particularly in high performance portable applications. Furthermore, as the density and size of the chips and systems continue to increase, the difficulty in providing adequate cooling might either add significant cost to the system or provide a limit on the amount of functionality that can be provided. In addition, many computation tasks currently require real-time processing. Once the real-time requirements are met, there is no advantage in increasing the computation throughput. This fact, along with pipelining, can be used to provide significant power savings in CMOS digital designs. The power dissipation in a well-designed digital CMOS circuit can be approximated as (l.3) where Ct is the total switching capacitance, Vdd is the supply voltage and /clk is the clock frequency. Due to the quadratic relationship of Vdd to the power consumption, reducing the supply voltage is clearly the key to the lowpower operation even after taking into account the modifications to the system architecture. If Vdd is reduced, we should pay a speed penalty (i.e., increase in the propagation delay To) as can be seen from the following equation: (1.4) where Cl is the capacitance along the critical path in the circuit, \It is the device threshold voltage and K, is a process dependent parameter. In any circuit the clock period has to be greater than the propagation delay of the critical path. The propagation delay (To) is associated with charging and discharging of the various gate and stray capacitances present on the critical path. Notice that To increases dramatically as Vdd approaches V t.