Digital Integrated Circuit Design I ECE 425/525 Chapter 1

Transcription

1 Digital Integrated Circuit Design I ECE 425/525 Chapter 1 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR (daasch@ece.pdx.edu) R.Daasch, Por tland State University 1 Apr il 2016

2 Dr ivers for bigger, better, faster integrated circuits Computers - big iron mainframes to Palm Pilots Data Communication - aka The Internet Wireless - cell phones, wireless LAN, wireless WAN Enter tainment Lifestyle R.Daasch, Por tland State University 2 Apr il 2016

3 Logic Complexity Catch Phrase Date Complexity (gates / chip) Single Transistor 1958 <1 Unit Logic Multi-Function Complex Function Medium Scale Integration Large Scale Integration ,000 Very Large Scale Integration ,000-20,000 Ultra Large Scale Integration ,000- System-on-Chip ,000,000- R.Daasch, Por tland State University 3 Apr il 2016

4 Logic Complexity Catch Phrase Date Size Number (µm) (x 1, 000) Single Transistor 1958 Unit Logic 1960 Multi-Function 1962 Complex Function Medium Scale Integration 1967 Large Scale Integration Very Large Scale Integration Ultra Large Scale Integration Change phrase to describe transistor Itsy Bitsy ,000 Teensy Weensy ,000 Incredibly Small ,000 Unbelievably Tiny ,000 Rediculously Small ,000 Damn This is Tiny ,000 Smaller than tobacco smoke par ticles (STSMP) ,000 R.Daasch, Por tland State University 4 Apr il 2016

5 Tr ansistor count is for an average size die ( 100mm 2 ) Human hair has a thickness of about 100,000 nanometers (100 µm, 0.1 mm) Sales (billions) Year Worldwide Semiconductor Sales Moore s Law The number of transistors per chip doubles every one and R.Daasch, Por tland State University 5 Apr il 2016

6 one-half years. New mater ials are beginning to replace Silicon, SiO 2 in the transistor Additional metals and other materials (e.g. carbon nanotubes) continue to be discussed Research active in memor ies and logic Prototypes only no products as of yet R.Daasch, Por tland State University 6 Apr il 2016

7 IBM Technology Summary Cu-32 Process generation 32nm Technology SOI HKMG Supply voltage (VDD) 0.9V/0.85V Wireable gates 400million Total levels of metal 11 edram compilers Other memory compilers HSS cores Fast Trc edram (SRAM alternative) Multi-banked edram (bandwidth optimized) Pseudo two-por t edram One- & two-por t SRAMs Dual-por t SRAM Ternar y CAM Tw o-and four-por t RA latches, ROM One-por t and dense two-por t register files 6G supporting PCI-Express Gen1 and Gen2 15G chip-to-chip core supporting low-power optical 15G backplane core 16G Fibre Channel 28G backplane core 32G Fibre Channel PCI-Express PCI-Express Gen1, Gen2 and Gen3 R.Daasch, Por tland State University 7 Apr il 2016

8 IBM Technology Summary Cu-32 (continued) Multi-Vt, Regular Vt, mezzanine Vt, ultrahigh Vt Clock gating (by design or through synthesis) Po wer supply, IPinvoltage islands can use Base Power management different supply voltages) Selective voltage binning Low-power SRAMsSemi-custom Voltage island power gating (turn off unused areas of a chip) Dynamic voltage scaling (modify power supply on-demand, with feedback) Full custom Dynamic frequency scaling (modify clock ondemand, with feedback) But frequencies are stalling with scalling IEEE why-cpu-frequency-stalled Spectr um R.Daasch, Por tland State University 8 Apr il 2016

9 SEM of a Intel 90nm transistor ; from IEEE Spectrum, October 2002 Single gate transistor controls channel from one side only R.Daasch, Por tland State University 9 Apr il 2016

10 from Multigate Device, Wikipedia 2013 Tr ansistor fin extends above the plane of Silicon wafer Double gate transistor controls channel from both sides R.Daasch, Por tland State University 10 Apr il 2016

11 from Multigate Device, Wikipedia 2013 Intel Tri-gate transistor controls channel from both 22nm Note all transistors are one size All transistors have a single common gate electrode On right SEM five transistor (sources) drains are shorted together R.Daasch, Por tland State University 11 Apr il 2016

12 Mater ials are changing from pure Silicon to complex str uctures that strain a lattice to engineer improvements to the fundamental electronic structure; from IEEE Spectrum, October 2002 R.Daasch, Por tland State University 12 Apr il 2016

13 The enormous flexibility comes with several costs Technology - \ billion or more for fabr ication plants with equipment and facilities Talent - materials, devices, hardware designers, software designers, mechanical engineering, chemical engineering, business (marketing, sales) Complexity - hardware design, software design, test design, tools for fabr ication and test R.Daasch, Por tland State University 13 Apr il 2016

14 The taxonomy of CMOS digital circuit technology Digital Circuits Clocked=No Clocked=Yes Static Circuits Dynamic Circuits Rail=1 Rail=2 Rail=1 Rail=2 Classical CMOS CVSL CMOS Domino Logic SSD Logic Classical CMOS Tw o complementar y logic blocks, one of NFETs, the other PFETs low static power, speed okay, signals are single rail R.Daasch, Por tland State University 14 Apr il 2016

15 Domino Logic Single logic block of(generally) NFETs, low static power more average power and faster than classical CMOS, two distinct phases controlled by a global clock Tr ansmission Gate Logic Doesn t fit into taxonomy ver y well; depending on the view looks static or dynamic R.Daasch, Por tland State University 15 Apr il 2016

16 Design Hierarchy Design is an art, a discipline, acraft and a science Designs should be appealing to the eye (ar t and craft) Design is a rigorous study (discipline and a science) Tr aditional top-down design flow System specification project concept; exter nal requirements High(First)-Level Model behavior design (VHDL/Ver ilog); system blocks specification; behavior verification; internal requirements; begin test plan Logic Synthesis structure and logic design (VHDL/Ver ilog); subsystem interface requirements; area, power, timing resource specification; logic ver ification; refine and iterate test plan R.Daasch, Por tland State University 16 Apr il 2016

17 Circuit Design technology mapping; interface design; area, power, timing allocation; circuit ver ification and simulation; converge test plan Physical Design area, power, timing closure; physical simulation; test plan ver ification Manufactur ing packaging, engineering prototypes, test and validation; Product production, test and validation; Top-down approach reflects an organizational approach for products but a poor way to study CMOS design This course will use bottom-up approach that mixes circuit and physical design R.Daasch, Por tland State University 17 Apr il 2016

18 Full-Adder Design Example Sum = ABC + ABC + ABC + ABC Sum = A+B+C Carry = AB + AC + BC Physical Design; Area, power, timing Propagation Delays (50%) 1.2ns Tr ansition Delays (10%-90%) 1.2ns Circuit Area <1500µm 2 DynPower (@ V DD = 5V f max = 20MHz) <1mW Circuit Design; circuit topology, CMOS technology CMOS technology - static (classical) CMOS Circuit topology - two interconnected sub-blocks for sum and carry R.Daasch, Por tland State University 18 Apr il 2016

19 Merge into a single, two output, complex-gate in transistor schematic The var ious transistor-level alter natives permit physical design tradeoffs Circuit designers (versus a VHDL programmer) have the added flexibility realizing the complex gates More familiar gates such as INVERTER, NAND2 and NOR2 can also be used R.Daasch, Por tland State University 19 Apr il 2016

20 NFET and PFET symbols, respectively MOSFET - Metal Oxide Semiconductor, Field Effect Tr ansistor Four terminal device; gate, source, drain and body Three terminals used for signal paths in integrated circuits Tw o types determined by the charge carrier NFET electron (e )current from source to drain PFET hole (h + )current from source to drain R.Daasch, Por tland State University 20 Apr il 2016

21 01 01 Inverter In Out Po wer supply voltage (global) Circuit design var iables Independent adjustment of length (L) and width (W) of each transistor (local) R.Daasch, Por tland State University 21 Apr il 2016

22 NAND2 In A In B Out Circuit design var iables Po wer supply voltage (global) In A In A In B Adjust each transistor length and width independently (local) Assign signals In A and In B to gate inputs independently (local) In B 01 R.Daasch, Por tland State University 22 Apr il 2016

23 In A In B Out In A In B In B In A Circuit design var iables Po wer supply voltage (global) Independent adjustment of length and width of each transistor (local) Independent assignment of In A and In B to inputs Inter nal logic states are stored in registers and memories Registers are assembled from latches or flip flops Memor ies are assembled from specific memory cell designs (SRAM, DRAM, CAM...) R.Daasch, Por tland State University 23 Apr il 2016

24 DATA 1 0 CLK Q Qbar Prototype Latch Latches clocked by one clock and clock (φ and φ) or two clocks (φ 1 and φ 2 ) Mux above is simplified from traditional NAND-NAND by pass transistor logic DATA 1 0 CLK 1 0 CLK Q Qbar Prototype (positive-edge) Flip-Flop R.Daasch, Por tland State University 24 Apr il 2016

25 Latches are combined to provide simple flip-flop behavior Physical design of the gates translates the ideal cartoons of PFET and NFET into mask layers Each mask layer has a minimum printing feature ranging from 2λ to 3λ Top view of the design typically shows the 3D effects with stipple patterns, color or both Stick diagrams are a simplified top view to per mit a quick and easy estimate of the physical design complexity Cross-section is rarely used in design and quite common in the discussion of the fabr ication process and device operating character istics R.Daasch, Por tland State University 25 Apr il 2016

26 Regular Design Circuit blocks used like Lego blocks Divide subsystem into similar circuit building blocks Iterate in X direction, Y direction for one-dimensional expansion and X,Y directions for arrays A N-bit ripple, carr y full-adder is assembled from N copies of 1-bit full adder circuits A N-bit by W-word memory is assembled from N W copies of 1-bit register At higher design hierarchy levels entire processors may be copied R.Daasch, Por tland State University 26 Apr il 2016

27 Modular ity well defined interfaces and function Analogous software concepts are the C-function or For tran subroutine Block inputs control but are isolated from function and outputs Block outputs are valid inputs to other blocks Temporal (time) and physical interfaces are equally impor tant Locality inputs and outputs are physically and temporally close Inter nal details of circuit hidden from inputs and outputs Modular and Regular circuits can be wired by placement alone R.Daasch, Por tland State University 27 Apr il 2016