Co Capping Layers for Cu/Low-k Interconnects

Transcription

1 IBM Research Co Capping Layers for /Low-k Interconnects Chih-Chao Yang IBM Co-Authors: International Business Machines Corp. P. Flaitz, B. Li, F. Chen, C. Christiansen, and D. Edelstein Applied Materials Inc. S.-Y. Lee, P. Ma 2010 IBM Corporation

2 Practical Points Dielectric capping layer Continual scaling of interconnect dimension Dielectric capping layer Low-k Barrier rrent density increase Low-k Risk of Electromigration (EM) Failure! / Dielectric capping layer interface Dominates diffusion path Weakest site in resisting EM failure Metallic capping layer Slows the diffusion Enhances EM resistance Dielectric Metallic 2 AMC, Albany, NY, Oct. 5-7, IBM Corporation

3 Metallic capping layer Low-k Barrier Practical Points Metal cap on interconnects to reduce transport and void growth- tradeoff b/w EM improvement and resistivity increase. Additional liabilities: line-to-line leakages, yield degradation, capacitance increases. Example: Implementation of a selective metal cap via electroless deposition technique Prevents contamination of dielectric surface from plating bath line-to-line leakages, yield degradation, other reliability related issues, impact on overall interconnect capacitance. Adds processing steps- Pre-/ Post-cleans Increased wafer process cost 3 AMC, Albany, NY, Oct. 5-7, IBM Corporation

4 Introduction Experimental Data - Selectivity Check - TEM Analysis Outline - Electrical Measurements - Reliability Summary 4 AMC, Albany, NY, Oct. 5-7, IBM Corporation

5 Background CVD Co Process Alternate liner approach in BEOL *, technology extendibility Reliable liner layer for -low k integration Selective metal cap in advanced / Low-k interconnects interconnect EM enhancement No undesirable impact on leakages, yields, electrical resistance * T. Nogami, et al., IEEE Int. Interconnect Technology Conf., AMC, Albany, NY, Oct. 5-7, IBM Corporation

6 Experimental Details Blanket wafers: selectivity of CVD Co on vs. low-k dielectrics Patterned wafers: electrical and reliability evaluations Liner/ Seed: 300mm platform: degas, Ar + sputter, PVD TaN, and PVD seed. Conventional electroplating and CMP Selective CVD Co cap layer on exposed interconnects Blanket NBLoK (SiC x N y H z ) dielectric capping layer TEM analysis on patterned wafers Feasibility of the CVD Co cap in the /low-k system: Inline parametric measurements, electromigration (EM) and time-dependent-dielectric-breakdown (TDDB) tests. 6 AMC, Albany, NY, Oct. 5-7, IBM Corporation

7 Selectivity Check X-Ray Fluorescence (XRF) spectroscopy - selectivity of the CVD Co deposition process between and low-k dielectric blanket substrates Deposit Co Thickness [A] Co on and dielectrics Deposit Time k1~2.7 k2~2.4 k3~2.2 Higher Co deposition rate on than on dielectrics, No obvious deposition rate difference observed among the dielectrics. Observed deposited Co thickness difference is attributed to the result of different incubation time exhibited between and dielectric substrates. 7 AMC, Albany, NY, Oct. 5-7, IBM Corporation

8 TEM Analysis Co selectivity check- intra-line/ dielectric surface Scanning Transmission electron microscopy (STEM) image and energy dispersive X-ray spectroscopy (EDX) analysis result. NBLoK Co ~1.8nm from 2x process time Confirmation of selective Co deposition on surface with no detectable nucleation on the exposed dielectric surface 8 AMC, Albany, NY, Oct. 5-7, IBM Corporation

9 NBLoK /Co/ interfacial properties Energy dispersive X-ray (EDX) electron energy-loss spectroscopy (EELS) profiles. Co NBLoK (SiC x N y H z ) Co NBLoK O - A small amount of O at the NBLoK/Co interface within the NBLoK. - The amount of O is in the range of that normally detected for NBLoK cap interfaces. - No detectable O is observed at the Co/ interface. 9 AMC, Albany, NY, Oct. 5-7, IBM Corporation

10 Electrical Measurements Patterned wafers: 32nm CMOS test vehicles consisting of one single damascene M1, four dual damascene Mx levels, and one Al termination level. After M2 polish, some wafers were selectively capped with various amount of CVD Co. Line-to-line leakage/yield measurements Leakage rrent [A] Leakage rrent Yield CVD Co Process Time Yield [%] Leakage currents increases and yields decreases with increasing the process time. No leakage current increase or yield degradation are observed on 2x and 4x process time splits. Complete selectivity is NOT observed when the process time is up to 6x, which is an indication of Co nucleation on intra-line dielectric surface. 10 AMC, Albany, NY, Oct. 5-7, IBM Corporation

11 Electrical Measurements Final parametric open/ short measurements- post Al termination level Comb-Serpentine Yield Yield Links of Via Chain Yield Yield Final M2 parametric yield measurements after additional 3 dual damascene and 1 Al termination levels. No line-to-line leakage current increase observed after next level process for both control and Co wafers. No open/short yield degradation observed at both the defect monitor structures. Demonstration of stable parametric yield prior and post CVD Co metal cap deposition 11 AMC, Albany, NY, Oct. 5-7, IBM Corporation

12 Electrical Measurements Resistance comparison between at-level and final measurements Line-Res Kevin Via-Res No line resistance increase observed due to the CVD Co cap process- an indication of very limited reaction between Co cap and interconnect. No Kelvin via resistance observed- supporting good thermal stability of the Co capped interconnect. 12 AMC, Albany, NY, Oct. 5-7, IBM Corporation

13 Reliability Test- EM Electromigration (25 ma/um 2 at 345 o C) Structure- dual damascene multi-level via-line Electron flow: single contact to 50nm wide line located below Failure criterion: 10% resistance increase Failure distribution: Lognormal Obvious EM resistance enhancement for Co-capped interconnects 13 AMC, Albany, NY, Oct. 5-7, IBM Corporation

14 Reliability Test- TDDB Module-level time-dependent dielectric breakdown (TDDB) test comb- serpentine structure with ~60 nm spacing Multiple constant electrical biases at 120 o C Failure criterion: leakage current increased by an order of magnitude Control No Co Co-4x Co-2x At high V, Co-4x shows the longest time-tobreakdown (tbd) and Co-2x shows the shortest tbd. Co-4x > Control > Co-2x Voltage acceleration factors (which are the slopes of lines) are in favor of the Co-2x. Co-2x > Control > Co-4x At low V, the three processes show very compatible tbd. Co-2x ~ Control ~ Co-4x No TDDB performance degradation observed from the Co cap process. 14 AMC, Albany, NY, Oct. 5-7, IBM Corporation

15 Conclusions A selective CVD Co cap deposition process was investigated for /low-k integration. Enhancement of interconnect electromigration resistance through this approach was demonstrated with supporting parametric measurements. This Co-capped interconnect structure also shows good thermal stability, which is a critical reliability requirement. This selective CVD Co cap process is a good candidate for reliable BEOL /low-k integration. 15 AMC, Albany, NY, Oct. 5-7, IBM Corporation

16 Acknowledgements This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities. 16 AMC, Albany, NY, Oct. 5-7, IBM Corporation