Recent Trends in Semiconductor IC Device Manufacturing

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1 Recent Trends in Semiconductor IC Device Manufacturing August 2007 Dr. Stephen Daniels Executive Director National Centre for Plasma

2 Moore s Law Moore s First Law Chip Density will double ever 18months. This means that memory sizes, processor power, etc. all follow the same curve Moore s Second Law The cost of building chip fabrication plants will continue to increase (and the return on investment to decrease) until it becomes fiscally untenable to build new plants i.e. while it may be technologically possible to continue to double the density of chips every 18months, the cost of achieving this goal will eventually surpass the profit Sustained for the last 4 decades!!

3 Industry trends Reduced linewidth - 65nm Increased wafer size - 300mm New Materials e.g. Cu/Low-k, High-k New Processes e.g. ALD, ECP, Immersion Litho Increased packing density > Price trend: From $100 per transistor to 10 million transistors per $!!!

4 Economic Realities Rising Fab Costs Greater Market Fragmentation Smaller Product Volumes Shorter Product Lifecycles Increased R&D Costs Ongoing business fluctuations New Trends: Manufacturing Alliances and R&D Partnerships Emergence of Low-Cost OEM Alternatives Yield is core to profitability

5 Topics du Jour From Semicon West 07 High-k and Metal Gate Next Shrink 45nm or 32nm Solar (& large area processing) Opportunities Growing Market for LEDs

6 Integrating New High-k dielectric materials with metal gate electrodes Oxynitride currently used as gate dielectric for CMOS Logic and Memory for current state of the art Often only 5 atomic layers used leads to gate leakage exacerbated by further scaling The ability to integrate high-k/metal gates will address the power consumption issue, one of the industry's major barriers to scaling semiconductor technology and continuing on Moore s Law path Dramatically reduces transistor leakage current a major source of unwanted power consumption HEAT Wafer costs will increase by roughly 4 percent with the introduction of chips based on high-k dielectrics and metal gates high-k/metal gate technology is expected to be initially implemented in 45nm low power devices followed by high performance chip designs

7 Fabrication Costs The operational costs of 300mm wafer production is significantly more expensive than 200mm wafer production In modern fabs, metrology costs can account for circa 20% of fab costs Current process monitoring generally incorporates stand-alone metrology, which is costly, time consuming, and requires additional steps

8 Integrated Metrology vs Stand-Alone Metrology Integrated metrology measures every wafer as it proceeds through the production line Off-line metrology relegated to calibration, tool matching,.. Currently huge risks due to lack of sensors, process models, cost Technical, Operational, Economic factors driving industry towards APC/AEC

9 Process Control - why now? The move to 65nm and lower Smaller process windows More expensive wafers The move to 300mm wafers More expensive wafers Higher capital equipment cost The erosion of margin Time to market Shorter cycle times Manufacturing costs

10 Current process control approaches 1. Tool-state SPC monitoring on all processed wafers 2. Wafer-state inline monitoring on sampled subset of wafers ISSUES Tool-state does not reflect wafer-state Limited wafer set, time delay on wafer-state sampling leads to yield loss, more advanced sensors required Yield is core to profitability

11 Process Control Issues Inability to identify problems until end-of-line Running test wafers to confirm problems Replacing components until the problem goes away Difficulty in localizing the problem

12 Advanced Process Control Options: A. Measure wafer-state on all wafers - very expensive, limits thruput B. Develop model which links wafer-state to processstate and measure process-state (Virtual Metrology) - physics/chemistry/control problem, work in progress C. Measure process-state to monitor faults - Fault Detection and Classification (FDC)

13 The Components of an APC Course Correction Framework (ITRS) Run-to-run (R2R) control - adjusts process parameters to compensate for drift in machine parameters Fault Management Fault Detection and Classification (FDC) - catches faults, initiates repair, reduces mis-processing of wafers and scrap

14 R2R Control Feed-Forward Model Model Process Module N-1 Metrology Process Module N Metrology Process Module N+1 Model Model Feed-back

15 Example Front-End CMP Integrated Ellipsometry Module Taken from K. J. Stanley et al, Proc Winter Simulation Conf.

16 Summary Many exciting opportunities and challenges facing the industry The semiconductor industry continues to promise greater rewards, with compound annual growth rates forecasted to be in the high single digits for many years to come Growth opportunities in emerging market sectors Technological Innovations in both the front end and backend Metrology becoming more critical and expensive Time for APC is fast approaching