Envisioning the Future of Optoelectronic Interconnects:

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1 Envisioning the Future of Optoelectronic Interconnects: The Production Economics of InP and Si Platforms for 100G Ethernet LAN Transceivers Shan Liu Dr. Erica Fuchs Prof. Randolph Kirchain MIT Microphotonics Consortium

2 This research seeks to quantify: Cost Competitiveness of Alternative 100G Ethernet LAN Transceivers Cost Structure of InP vs. Silicon Material Platform A Case Study Roadmap Motivation InP 100G Ethernet -Ever growing demand for bandwidth -A draft standard by 2010 Transceivers nm, single mode, < 1 km Si?

3 Competing Technology Solutions for 100GE Material Platform Key Component Light Source (Laser) Material InP/GaAs Modulator InP/GaAs, Si Laser Driver Si Transmit Modulator Driver InP/GaAs Mux/Demux, Waveguide InP, Si PIN/APD detector InP/GaAs, Ge, SiGe TIA InP/GaAs Receive

4 Competing Technology Solutions for 100GE Design Architecture + + Laser Modulator Mux/Demux + + Waveguide detector TIA + Driver + Isolator + Transceiver Integration Discrete InP TOSA + Hybrid Receiver Design 1 & 2 10 Hybrid x 10 G Transceiver DML Array Design 3 Si Photonics Chip Design 4

5 Method: Process-Based Cost Model Projecting cost: Minimum efficient fabrication line for a defined annual volume of good device produced 26 inputs per process: Equipment, floor space, material, labor, cycle time, yield, etc. Conventional model: COO, CRM Product Description Process Model Processing Requirements Operations Model Resource Requirements Financial Model Production Cost Operating Conditions Factor Prices

6 Front-end fabrication: Complete Design 1, TO-CAN Design 2, DML Array Design 3, Hybrid Transceiver Progress To-Date In Progress Design 4, Two Chip (0.18 um Si optical flow) Back-end packaging and assembly

7 Design One: To-Cans (complete) Thin-film filter To-Can Submounts Header Cap Photodiode Laser Lens Isolator Drive Electronics Transmitter Fiber Receiver AWG demux TIA 10 photodetectors

8 Design Two: DML Array (complete) 10 by 10G DML Len s Triangular prism with thin film filters Drive Electronics Transmitter Fiber Receiver AWG demux TIA 10 photodetectors

9 Design Three: Hybrid (complete) 10 by 10G DML Fiber MPD WG mux/demux TIA Transceiver chip 10 photodetectors detector array M Connector F Connector Substrate Integrated WG, modulator, detector chip Flex/PCB Laser array, MPD Optical Coupling Fiber, pigtail Mechanical Housing o-e-m Submount

10 Design Four: Source: CTR, Mark Beals Two Chip Modulator, detector M Connector F Connector Substrate Integrated WG, modulator, detector chip Flex/PCB Laser array Optical Coupling Fiber, pigtail Mechanical Housing o-e-m Submount

11 Result 1: DML Discrete (10G) vs. Array (10 x 10G) Economy of Scale APV = 60 K Discrete: $32 Array: $56 Unit Cost discrete laser Laser array Annual Production Volume

12 Result 2: Cost Comparison of Design One, Two, Three Unit Cost Annual Production Volume APV = 60 K To-Can: $220 DML Array: $150 Hybrid: $115 Design 1 TO-CAN Design 2 DML Array Design 3 Hybrid

13 Result 2: Cross-Over of Design One, Two, Three 100 Unit Cost Difference Design 1 TO-CAN Design 2 DML Array Design 3 Hybrid Annual Production Volume

14 Result 3: Cost Breakdown of Design One, Two, Three 60,000 APV 250 Unit Cost Receiving Components Isolator Light Guiding Components Laser 0 Design 1 TO-CAN Design 2 DML Array Design 3 Hybrid

15 Result 2: Cross-Over of Design One, Two, Three Reducing Isolator cost by 20% 100 Unit Cost Difference Design 1 TO-CAN Design 2 DML Array Design 3 Hybrid Design 1 TO-CAN Old Design 2 DML Array Old Annual Production Volume

16 Progress in Modeling Si Photonics Case Process flows for Two Chip and One Chip solutions Determined comparable end-point designs in all solutions Model Development Identified 30 additional Si process modules Data Collection Identified possible tool and tool cost for each process step Conduct on-going interviews with equipment manufacturers Acquired data on each of the 9 lithography steps for Design 4

17 Assessed Yield Impact for Si Photonic CMOS Flow: Systematic Yield Impact New Ge CMP process High thermal treatment Defect Driven Yield Loss Based on historical experience with the 0.18 um node manufacturing health

18 Yield Impact Analysis 0.18 um Al/SiO2 Process Flow Comments Optical flow additional yield impact Excursion / systematic component Rev MAB Total Impact = # # Pattern Si waveguides at this photo step in order to put planarized oxide around the Expose Active Area & Si WG waveguides. Two STR pattern modules # Thicker oxide needed to match Ge Dep, Undoped TEOS thickness slight defect issue with thicker film # Deposit Nitride Nitride for Ge CMP stop on nitride nitride film defects # Expose Active Area litho defects # Ge Etch Ox Resist Def Insp little extra just to be sure extra metro # Etch Active Area Etch thicker oxide more etch, extra defects # Strip Ge Etch Ox Resist descum defects # Strip Active Resist sulf defects # assume Ge defects wont matter during Selective Ge Epi Ge EPI Growth dep, the area fraction is very small # This is the big variable. Lower bound is defect limited, ie tear outs; upper bound Planarize wafers (CMP) is systematic issue # # Assume no impact due to low feature Etch density; poly stringers on Ge CMP Polysilicon electrode prep'd surface? # # Resist Strip Sulf defects #

19 Conclusion Goal Finding the most cost effective strategies Cost modeling on all four designs in PBCM Scale Material Platform Integration Immediate Results Four functionally equivalent designs Hybrid design is the most competitive solution. Adding Design 4 and the back-end? Wafer cost from Sematech s s Cost Resource Model for the Design 4. Benchmark with future PBCM results

20 Special Thanks Erica Fuchs Randy Kirchain Mark Beals Lionel Kimerling

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