The impact of Triangular Defects on Electrical Characteristics and Switching Performance of 3.3kV 4H-SiC PiN Diode

Transcription

1 The impact of Triangular Defects on Electrical Characteristics and Switching Performance of 3.3kV 4H-SiC PiN Diode Yeganeh Bonyadi, Peter Gammon, Roozbeh Bonyadi, Olayiwola Alatise, Ji Hu, Steven Hindmarsh, Philip Mawby School of Engineering of University of Warwick Coventry, United Kingdom Abstract In this work the impact of a surface morphological defect, i.e. the triangular defect on fabricated 4H-SiC PiN diodes is explored. Diodes are intentionally fabricated on triangular defects on wafers with 35 (PiN1), and 30 (PiN2) μm 4H-SiC epitaxial layers in order to understand their impact on the resulting electrical characteristics and switching performance. We show for the first time the impact of triangular defects on switching characteristics of 3.3kV SiC PiN diodes fabricated on and off-defects and prove that the existence of triangular defects limit the active area of the devices and creates a short through the drift region, which increases the leakage current by almost times than the devices off-defect. TEM images obtained from the defects verified these electrical results. Also, the reverse characteristics show that both substrates suffer from soft breakdown. The switching results show that the presence of triangular defects does not negatively affect the carrier lifetime of devices on-defect. In contrary, there is some evidence (especially in lower current values) that the amount of stored charge is increased. However, this depends on the ratio of defect to the active area of the devices. Keywords 4H-SiC, Triangular defect, PiN diode, Forward and Reverse I-V Characteristics, Clamped Inductive Switching. I. INTRODUCTION 4H-SiC is a promising wide bandgap semiconductor material for high voltage and high-temperature applications. SiC PiN diodes have lower on-state power losses, lower leakage current, and lower reverse recovery loss compared to their Si unipolar counterparts [1,2]. This is due to the conductivity modulation effect, which lowers the resistance of the thick, low-doped drift region needed to block high voltages. Hence, the use of these bipolar devices in high voltage applications is very attractive. However, the potential of SiC bipolar devices is significantly limited when SiC devices are fabricated on technology killing defects such as triangular defects and 3C inclusions. The formation of triangular defects depends on many factors including the substrate defects, foreign particles falling down onto the wafer before or during epitaxy and growth conditions (such as C/Si ratio and temperature) [3]. Triangular defects show substantial increase in leakage currents and decreased breakdown voltages. This has been reported for 3C triangular inclusions [4,5] resulting in >50% reduction in blocking voltage of PiN diodes [6]. Thus, it is important to understand the behavior of defects in SiC epitaxial layers and substrates. In this paper we look in more detail at the electrical characteristics of PiN diodes intentionally formed on and off of triangular defects. Wafers with 30 and 35 m 4H-SiC epitaxial layers from different manufacturers are used in order to understand their impact on the resulting electrical characteristics. Section II describes the material characteristics and device fabrication, the forward and reverse I-V characteristic is presented in section III, section IV discusses the experimental setup and clamped inductive switching tests results, and section V concludes this study. II. EXPERIMENTAL DETAILS The PiN diodes used in this work were fabricated in-house using two different 4-inch n-type (0001) Si face, 4 off axis 4H-SiC wafers. The first wafer (forming PiN1) was acquired from supplier A, and consisted of a 1 μm p-type top contact doped above 1.5x10 19 cm 3 on top of a 35 μm thick drift region of 2x10 15 cm 3 n-type doping. The other wafer were acquired from supplier B with a top contact layer of 1μm thick p-type doping up to 1x10 19 cm 3, having a 30 μm thick drift region with 2x10 15 cm 3 n-type doping (PiN2). Both wafers are prime grade. A. Material Characteristics Photoluminescence spot analysis was performed at triangular defect area and the bulk area using a 325 nm wavelength source. The location of the defect can be specified using optical microscope. The optical microscopic view of PiN2 epi layer sample is shown in Fig. 1. The peak corresponding to 4H- SiC (380 nm) was detected as well as the existence of stacking faults (SF from 420nm-564nm), Threading Edge Dislocations (TED range>700nm), Threading Screw dislocations (TSD >600nm), and other polytypes [7]. The thicker epilayer (PiN1) has lower concentration of defects compared to PiN2 with more defective epilayer. Hence, it is important to see the correlation of these epi-defects on the electrical performance of the fabricated PiN diodes [8]. This work was supported by the EPSRC Grant on Underpinning Power Electronics Devices Theme EP/L007010/1 at the University of Warwick and has used cleanroom facilities funded by Advantage West Midlands and the European Regional Development Fund through the Science City Energy Efficiency project /16/$ IEEE

2 Figure 1: PL images using 325 nm wavelength source at the defect (1st, 2nd, and 3rd scan area) and bulk (4th scan area) and the optical microscopic view of a 30 m (PiN2) epitaxial layer sample. B. Scanning Electron Microscopy Figure 2 shows SEM images of the defects, where the triangular surface defects are generated with obtuse angles. Formations of pits with diameter at top parts were often observed in the substrates. Bending, wavy and step-like vertical fine lines were observed at surfaces as well. In the SEM image the foreign material is also visible which is thought to drop from a CVD furnace environment at the initial stage of the epitaxial film growth process and are the origins of the surface defects. front (Ti/Al) and backside (Ti/Ni) of PiN diodes after a rapid thermal annealing process at 1000 C for 2 minutes in inert ambient [9]. A high anode doping concentration was used to help thermionic field emission at the metal-semiconductor interface, in order to decrease the anode ohmic contact resistance. Epitaxial layers were grown in a continuous growth run to minimize the effects of interface recombination on the overall carrier lifetime of the devices [10]. After the contact anneal, a 1 m thick layer of Al and a 1 m thick layer of Ag were evaporated on to front and backside of the dies, respectively. The active area of all the devices were 4.53 x 10-4 cm 2. A photograph of a DCB-mounted PiN diode die is shown in Figure 3(b). Each die contains over 90 PiN diodes of varying active areas. Figure 3: (a) Cross-section view of fabricated PiN diode and the electrical impact of triangular defect on the device (b) Photograph of DCBmounted 4H-SiC PiN diode die. III. RESULTS AND DISCUSSION A. Forward I-V Characteristics The forward characteristics of diodes on- and off-defect for PiN1 and 2 are shown respectively in Figures 4(a), (b). A small leakage path at <2V is present on-defect (Figure 4(a)) and the resistance is 2.83 times higher. This is due to the existence of the triangular defect, which performs as a high resistance short of the p-type region, causing the leakage, but restricting the effective device areas represented in Figure 3(a). Figure 2: High resolution SEM images of an obtuse triangular defect. C. Device Fabrication The cross-sectional schematic of the fabricated PiN diodes on and off the triangular defects is shown in Figure 3(a). After laser cutting, the dies underwent standard RCA cleaning. The next fabrication process was to define individual active areas of PiN diodes both on and off triangular defects and mesa-isolate the individual anodes. Ohmic contacts were then formed to the

3 Figure 4: Forward logj-v characteristics for PiN diodes fabricated on and off-defect on (a) PiN1 (35 m layer) and (b) PiN2 (30 m layer). B. Reverse I-V Characteristics Figure 5, represents the reverse characteristic of both diodes, on and off-defect. This is equally affected by the high resistance leakage path, and as a the devices on-defect have a leakage current 6-8 orders of magnitude higher than their offdefect equivalents and both suffer from soft breakdown. Dissimilarities between the off-defect (really, off triangular inclusion) diodes propose the existence of other possibly conductive defects not realized in the PL or microscope pictures. As seen in Figure 5, the leakage current of the offdefect devices on PiN1 is below the noise base of the parameter analyzer, while PiN2 has a higher leakage. The most defective wafer, PiN2, with higher defect density (but lower drift region thickness) showed higher leakage current compared to PiN1, with lower defect concentration. IV. EXPERIMENTAL SETUP AND DISCUSSION The switching characteristic of SiC PiN diodes are evaluated using clamped inductive switching circuit which reproduces the current commutation between the high side diode and low side transistor. The switching rate of the transistor/diode pair is modulated by the gate resistance used during switching. The experimental setup and the equivalent circuit used in this experiment are shown in Figure 6. The test rig is shown in Figure 6(a) and it was used to capture the switching characteristic of the fabricated PiN diodes and the SiC MOSFET. In this test, the SiC MOSFET is a 1200V/10A Cree device with part number C2M Two pulses are applied to the gate of the low side SiC MOSFET. During the first pulse, the inductor is charged and during the second pulse the turn-on and turn-off waveform of the devices are captured. When the MOSFET is off, the current is free-wheeling through the fully charged inductor and the diode. As the transistor is switching on, current commutates from the diode to the transistor at a rate that depends on the RC time constant of the MOSFET. The experiments here have been performed at room temperature with gate resistor of 10 and the supply voltage of 40V. The results shown in Figure 7 compare the reverse recovery waveform of the devices formed on and off of the defect with different currents for PiN1 and PiN2. Figure 7(a) indicates that when the ratio between the defect area and the active die area is small, the devices on and off defect switch in a similar behaviour; i.e. the leakage current is small and the reverse recovery shape for both on and off defect devices stays the same. No evidence of change in the carrier lifetime and hole recombination rate is observed. As the device is switched off and the excessive amount of minority carriers are extracted from the drift region, the depletion regions are formed as the slope of the current changes from the negative slope to positive. Consequently, both devices should block and prevent current from passing through. However, this is not the case for the devices on-defect. Due to the fact that the area of defect is a large portion of the effective die active area, there are significant amount of leakage current going through the device. Figure 5: Reverse leakage current of both PiN diodes fabricated on and off-defect.

4 (b) Figure 6: Clamped inductive switching test rig (b) Circuit diagram of a clamped inductive switching circuit. [1] DC Power Supply. [2] Test Chamber. [3] Function Generator. [4] Current probe Amplifier. [5] Oscilloscope. [6] Inductor. [7] Differential voltage probe. [8] Voltage probe. [9] and [14] Current Probes. [10] and [11] DUTs. [12] Drive MOSFET. [13] Gate Drives. [14] DBC mounted 4H-SiC PiN diode [15] DC capacitor. This can also be confirmed by looking at the reverse I-V characteristics of the devices both on and off-defect shown in Figure 5. As can be seen in this graph, the leakage current of the devices on-defect are 4 orders of magnitude higher than the off-defect devices of the same size. Figure 7(b) shows that the device off-defect has higher current ringing and oscillation in comparison to the device ondefect. The ringing is due to the rapid decrease of the junction capacitance due to formation of high reverse electric field across the device. This drop device capacitance coupled with the stray inductance of the circuit causes oscillations in the device behaviour. Another side-effect of the leakage current induced by the defect on the device is that due to injection of carriers into the device through the defects, the depletion regions cannot form and block the voltage, hence the device capacitance does not drop down as rapidly as it does in the device off-defect. Hence, the ringing damps down quickly and the value of the current becomes equal to the leakage current of the device seen at Figure 5. Previous work [11] has suggested that compared to defectfree regions, the carrier lifetime is severely reduced by the presence of stacking faults corresponding to triangular surface defects and three-dimensional 3C-SiC inclusions. The switching measurements presented in Figure 7 show no decrease in stored charge, suggesting either that few extra stacking faults are present around the defect, or that their impact on recombination is minor. In fact, on the contrary, in Figure 7(b) there is some evidence (especially in lower current values shown in black) that the amount of stored charge is increased, though the reason for this is unclear, and dependent on the size and depth of the defect. This is verified by TEM analysis shown in Figure 8 where the existence of grain boundary and hence leakage path through the drift region is observed. Figure 8(b) shows the diffraction pattern from three different areas around the defect and the grain boundary. It can be seen that the orientation of the 4H-SiC crystal is different in areas (1) and (2). Area (3) shows the diffraction pattern of the grain boundary. Figure 7: Reverse recovery current waveform for devices fabricated on and off-defect on (a) PiN1 and (b) PiN2 at room temperature conditions using 40V supply voltage and a 10 gate resistance. (a)

5 REFERENCES (b) Figure 8: (a) TEM image and (b) diffraction patterns of the triangular defect area showing the grain boundary and the leakage path. V. CONCLUSIONS In this paper the impact of obtuse triangular defects on fabricated 4H-SiC PiN diodes is investigated. Diodes were formed on wafers with 30 and 35 μm 4H-SiC epitaxial layers. We have shown that the existence of these defects limit the active area of the devices and creates a short path through the drift region which increases the leakage current almost times higher than the devices off-defect in diodes fabricated on 35 μm epitaxial layer with low defect density. Hence, devices fabricated on epi layer with greater defects, show a very poor forward and reverse characteristics. Also, the reverse bias shows that all substrates suffer from soft breakdown. We showed for the first time the impact of triangular defects on switching characteristics of 3.3kV SiC PiN diodes fabricated on and off-defects. In the switching results of the devices presented in this paper, the amount of stored charge is not decreased. This can either be due to the presence of few extra stacking faults around the defect, or the fact that they have a minimal effect on recombination rate. The verification of our results, were achieved using TEM images taken from these defects which showed the existence of grain boundaries that act as a leakage path through the drift region of the PiN diodes with defects. [1] Peter Gammon, Silicon and the wide bandgap semiconductors, shaping the future power electronic device market, in Proc. 14th Int. Conf. Ultimate Integr. Silicon, Mar. 2013, pp [2] R. Bonyadi et al., Compact electro-thermal reliability modelling and experimental characterisation of bipolar latch-up in SiC and CoolMOS power MOSFETs, IEEE Trans. Power Electron., vol. 30, no. 12, pp , Dec [3] Dong Lin, Sun Guo-Sheng, Zheng Liu YuJun, Liu Xing-Fang, Zhang Feng, Yan Guo-Guo, LI Xi-Guang, Wang Zhan-Guo, and Yang Fei, Characterization of Obtuse Triangular Defects on 4H-SiC 4 off-axis Epitaxial Wafers, Chin. Phys. Lett., 30(9), (2013). [4] T. Kimoto et. al., Performance Limiting Surface Defects in SiC Epitaxial p-n Junction Diodes, IEEE Transaction Electron Devices 46 (1999), p [5] Kimoto T, Miyamoto N, Matsunami H. Performance limiting surface defects in SiC epitaxial layers p n junction diodes, IEEE Trans Electron Devices, 1999; 46(3): [6] Neudeck PG, Electrical impact of SiC structural crystal defects on high electric field devices, Mater. Sci. Forum 2000; : [7] R. E. Stahlbush, K. X. Liu, Q. Zhang, J. J. Sumakeris, Whole-Wafer Mapping of Dislocations in 4H-SiC Epitaxy, Mater. Sci. Forum (2007) 295. [8] Y. Bonyadi, P. M. Gammon, R. Bonyadi, V. A. Shah, C.A. Fisher, D. M. Martin, P. A. Mawby, "Characterization of 4H-SiC PiN Diodes Formed on Defects Identified by PL Imaging", Materials Science Forum, Vol. 858, pp , [9] Craig A. Fisher, Michael R. Jennings, Yogesh K. Sharma, et al., Improved Performance of 4H-SiC PiN Diodes Using a Novel Combined High Temperature Oxidation and Annealing Process, IEEE Transactions on Semiconductor Manufacturing Vol 27 (3), Aug 2014, p [10] K. Nakayama et al., Characteristics of a 4H-SiC PiN diode with carbon implantation/thermal oxidation, IEEE Trans. Electron Devices, vol. 59, no. 4, pp , Apr [11] S.I.Maximenko, J.A.Freitas, P.B.Klein, A.Shrivastava, T.S.Sudarshan Cathodoluminescence Study of the Properties of Stacking Faults in 4H- SiC Homoepitaxial Layers. Applied Physics Letters, 94, (2009). ACKNOWLEDGMENT The authors would like to thank the EPSRC Project on Underpinning Power Electronics Devices Theme EP/L007010/1 at the university of Warwick and The Centre for Power Electronics. They would also like to thank Dr. M. Crouch and the cleanroom staff at the University of Warwick for support during device fabrication.