MC14541B. Programmable Timer

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Programmable Timer The MC454 programmable timer consists of a 6stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, an automatic poweron reset circuit,

1 Programmable Timer The MC454 programmable timer consists of a 6stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, an automatic poweron reset circuit, and output control logic. Timing is initialized by turning on power, whereupon the poweron reset is enabled and initializes the counter, within the specified range. With the power already on, an external reset pulse can be applied. Upon release of the initial reset command, the oscillator will oscillate with a frequency determined by the external RC network. The 6stage counter divides the oscillator frequency (f osc ) with the n th stage frequency being f osc /2 n. Features vailable Outputs 2 8, 2, 2 3 or 2 6 Increments on Positive Edge Clock Transitions uiltin Low Power RC Oscillator (± 2% accuracy over temperature range and ± 20% supply and ± 3% over processing at < khz) Oscillator May e ypassed if External Clock Is vailable (pply external clock to Pin 3) External Master Reset Totally Independent of utomatic Reset Operation Operates as 2 n Frequency Divider or Single Transition Timer Q/Q Select Provides Output Logic Level Flexibility Reset (auto or master) Disables Oscillator During Resetting to Provide No ctive Power Dissipation Clock Conditioning Circuit Permits Operation with Very Slow Clock Rise and Fall Times utomatic Reset Initializes ll Counters On Power Up Supply Voltage Range = 3.0 Vdc to 8 Vdc with uto Reset Supply Voltage Range = Disabled (Pin 5 = ) Supply Voltage Range = 8.5 Vdc to 8 Vdc with uto Reset Supply Voltage Range = Enabled (Pin 5 = V SS ) PbFree Packages are vailable* PIN SSIGNMENT WL, L YY, Y WW, W PDIP4 P SUFFIX CSE 646 SOIC4 D SUFFIX CSE 75 TSSOP4 DT SUFFIX CSE 948G SOEIJ4 F SUFFIX CSE MRKING DIGRMS 4 4 MC454CP WLYYWW WLYWW 4 54 LYW MC454 WLYWW = ssembly Location = Wafer Lot = Year = Work Week R tc 4 C tc NC NC ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. R 5 MODE MR 6 9 Q/Q SEL V SS 7 8 Q NC = NO CONNECTION *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 February, 2005 Rev. 8 Publication Order Number: MC454/D

2 MXIMUM RTINGS (Voltages Referenced to V SS ) Symbol Parameter Value Unit DC Supply Voltage Range 0.5 to +8.0 V V in, V out Input or Output Voltage Range, (DC or Transient) 0.5 to V I in Input Current (DC or Transient) ± (per Pin) m I out Output Current (DC or Transient) ±45 (per Pin) m P D Power Dissipation, per Package (Note ) 500 mw T mbient Temperature Range 55 to +25 C T stg Storage Temperature Range 65 to +0 C T L Lead Temperature, (8Second Soldering) 260 C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ C From 65 C To 25 C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be constrained to the range V SS (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or ). Unused outputs must be left open. ORDERING INFORMTION Device Package Shipping MC454CP PDIP4 500 Units / Rail MC454CPG PDIP4 (PbFree) 500 Units / Rail MC454D SOIC4 55 Units / Rail MC454DG SOIC4 (PbFree) 55 Units / Rail MC454DR2 SOIC Units / Tape & Reel MC454DR2G SOIC4 (PbFree) 2500 Units / Tape & Reel MC454DTR2 TSSOP4* 2500 Units / Tape & Reel MC454F SOEIJ4 50 Units / Rail MC454FEL SOEIJ Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications rochure, RD80/D. *This package is inherently PbFree. 2

3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICL CHRCTERISTICS (Voltages Referenced to V SS ) Characteristic Output Voltage V in = or 0 0 Level Symbol V OL V Level V in = 0 or OH Input Voltage 0 Level (V O = 4.5 or 0.5 Vdc) (V O = 9.0 or.0 Vdc) (V O = 3.5 or.5 Vdc) (V O = 0.5 or 4.5 Vdc) (V O =.0 or 9.0 Vdc) (V O =.5 or 3.5 Vdc) Level Output Drive Current (V OH = 2.5 Vdc) Source (V OH = 9.5 Vdc) (V OH = 3.5 Vdc) (V OL = 0.4 Vdc) Sink (V OL = 0.5 Vdc) (V OL =.5 Vdc) V IL V IH I OH I OL 55 C 25 C 25 C Min Max Min Typ Max Min Max Unit Vdc (Note 2) Input Current I in ± 0. ± ± 0. ±.0 dc Input Capacitance (V in = 0) C in 7.5 pf Vdc Vdc Vdc Vdc mdc mdc Quiescent Current (Pin 5 is High) uto Reset Disabled I DD dc uto Reset Quiescent Current (Pin 5 is low) I DDR dc Supply Current (Notes 3 & 4) (Dynamic plus Quiescent) I D I D = (0.4 /khz) f + I DD I D = (0.8 /khz) f + I DD I D = (.2 /khz) f + I DD 2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 3. The formulas given are for the typical characteristics only at 25 C. 4. When using the on chip oscillator the total supply current (in dc) becomes: I T = I D + 2 C tc f x 3 where I D is in, C tc is in pf, in Volts DC, and f in khz. (see Fig. 3) Dissipation during poweron with automatic reset enabled is typically = Vdc. dc 3

4 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHRCTERISTICS (Note 5) (C L = 50 pf, T = 25 C) Characteristic Symbol Min Typ (Note 6) Max Unit Output Rise and Fall Time t TLH, t THL = (.5 ns/pf) C L + 25 ns t TLH, t THL = (0.75 ns/pf) C L ns t TLH, t THL = (0.55 ns/pf) C L ns Propagation Delay, Clock to Q (2 8 Output) t PLH, t PHL = (.7 ns/pf) C L + 34 ns t PLH, t PHL = (0.66 ns/pf) C L + 27 ns t PLH, t PHL = (0.5 ns/pf) C L ns Propagation Delay, Clock to Q (2 6 Output) t PHL, t PLH = (.7 ns/pf) C L + 59 ns t PHL, t PLH = (0.66 ns/pf) C L ns t PHL, t PLH = (0.5 ns/pf) C L ns t TLH, t THL t PLH t PHL t PHL t PLH Clock Pulse Width t WH(cl) Clock Pulse Frequency (50% Duty Cycle) f cl MR Pulse Width t WH(R) Master Reset Removal Time t rem 5. The formulas given are for the typical characteristics only at 25 C. 6. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance ns s s ns MHz ns ns PULSE GENERTOR R Q/Q SELECT MODE MR Q C L PULSE GENERTOR R Q/Q SELECT MODE MR Q C L V SS V SS (R tc ND C tc OUTPUTS RE LEFT OPEN) 20 ns 20 ns 20 ns 20 ns 90% 50% % 50% DUTY CYCLE Q 90% 50% % t PLH 50% 90% % t TLH 50% 50% t PHL t THL Figure. Power Dissipation Test Circuit and Waveform Figure 2. Switching Time Test Circuit and Waveforms 4

5 EXPNDED LOCK DIGRM 2 3 R tc C tc 2 3 OSC RESET 8STGE C 2 COUNTER 8 RESET C 8STGE COUNTER RESET OF 4 MUX 8 Q UTO RESET 5 POWERON RESET = PIN 4 V SS = PIN 7 6 MSTER RESET MODE 9 Q/Q SELECT FREQUENCY SELECTION TLE Number of Counter Stages n Count 2 n TRUTH TLE State Pin 0 uto Reset, 5 uto Reset Operating uto Reset Disabled Master Reset, 6 Timer Operational Master Reset On Q/Q, 9 Output Initially Low fter Reset Output Initially High fter Reset Mode, Single Cycle Mode Recycle Mode 3 TO CLOCK CIRCUIT INTERNL RESET 2 C tc R TC Figure 3. Oscillator Circuit Using RC Configuration 5

6 TYPICL RC OSCILLTOR CHRCTERISTICS FREQUENCY DEVITION (%) R TC = 56 k, C = 00 pf V = V V = 0, f =. = V, T = 25 C = 20 k, f = 7.8 = V, T = 25 C T, MIENT TEMPERTURE ( C) Figure 4. RC Oscillator Stability 0 25 f, OSCILLTOR FREQUENCY (khz) f S FUNCTION OF C (R TC = 56 k ) ( = 20 k ) = V f S FUNCTION OF R TC (C = 00 pf) ( 2R TC ) 0..0 k k 0 k.0 m R TC, RESISTNCE (OHMS) C, CPCITNCE ( F) OPERTING CHRCTERISTICS Figure 5. RC Oscillator Frequency as a Function of R tc and C tc With uto Reset pin set to a 0 the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a. oth types of reset will result in synchronously resetting all counter stages independent of counter state. uto Reset pin when set to a provides a low power operation. The RC oscillator as shown in Figure 3 will oscillate with a frequency determined by the external RC network i.e., f = 2.3 R tc C tc if ( khz f 0 khz) and 2 R tc where k The time select inputs ( and ) provide a twobit address to output any one of four counter stages (2 8, 2, 2 3 and 2 6 ). The 2 n counts as shown in the Frequency Selection Table represents the Q output of the N th stage of the counter. When is, 2 6 is selected for both states of. However, when is 0, normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 2 8 ). The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition and Q/Q select pin is set to a 0 the Q output is a 0, correspondingly when Q/Q select pin is set to a the Q output is a. When the mode control pin is set to a, the selected count is continually transmitted to the output. ut, with mode pin 0 and after a reset condition the flipflop (see Expanded lock Diagram) resets, counting commences, and after 2 n counts the flipflop sets which causes the output to change state. Hence, after another 2 n counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. DIGITL TIMER PPLICTION t MR INPUT R tc C tc NC R MR MODE Q/Q t + t MR N.C. OUTPUT When Master Reset (MR) receives a positive pulse, the internal counters and latch are reset. The Q output goes high and remains high until the selected (via and ) number of clock pulses are counted, the Q output then goes low and remains low until another input pulse is received. This one shot is fully retriggerable and as accurate as the input frequency. n external clock can be used (pin 3 is the clock input, pins and 2 are outputs) if additional accuracy is needed. Notice that a setup time equal to the desired pulse width output is required immediately following initial power up, during which time Q output will be high. 6

7 PCKGE DIMENSIONS PDIP4 P SUFFIX CSE ISSUE N T N SETING PLNE F C K H G D 4 PL 0.3 (0.005) M J L M NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEDS WHEN FORMED PRLLEL. 4. DIMENSION DOES NOT INCLUDE MOLD FLSH. 5. ROUNDED CORNERS OPTIONL. INCHES MILLIMETERS DIM MIN MX MIN MX C D F G 0.0 SC 2.54 SC H J K L M N SOIC4 D SUFFIX CSE 7503 ISSUE G T SETING PLNE G 4 8 D 4 PL 7 K P 7 PL C 0.25 (0.0) M T S S 0.25 (0.0) M M R X 45 M J F NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS ND DO NOT INCLUDE MOLD PROTRUSION. 4. MXIMUM MOLD PROTRUSION 0. (0.006) PEIDE. 5. DIMENSION D DOES NOT INCLUDE DMR PROTRUSION. LLOWLE DMR PROTRUSION SHLL E 0.27 (0.005) TOTL IN EXCESS OF THE D DIMENSION T MXIMUM MTERIL CONDITION. MILLIMETERS INCHES DIM MIN MX MIN MX C D F G.27 SC 0 SC J K M P R

8 PCKGE DIMENSIONS TSSOP4 DT SUFFIX CSE 948G0 ISSUE O 0. (0.006) T 0. (0.006) T L 0. (0.004) T SETING PLNE U U S 2X L/2 PIN IDENT. S D C 4 4X K REF 0. (0.004) M T U S V S N (0.0) M U 7 V G H N J J F DETIL E K K ÇÇÇ ÉÉÉ SECTION NN DETIL E W NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION DOES NOT INCLUDE MOLD FLSH, PROTRUSIONS OR GTE URRS. MOLD FLSH OR GTE URRS SHLL NOT EXCEED 0. (0.006) PEIDE. 4. DIMENSION DOES NOT INCLUDE INTERLED FLSH OR PROTRUSION. INTERLED FLSH OR PROTRUSION SHLL NOT EXCEED 0.25 (0.0) PEIDE. 5. DIMENSION K DOES NOT INCLUDE DMR PROTRUSION. LLOWLE DMR PROTRUSION SHLL E 0.08 (0.003) TOTL IN EXCESS OF THE K DIMENSION T MXIMUM MTERIL CONDITION. 6. TERMINL NUMERS RE SHOWN FOR REFERENCE ONLY. 7. DIMENSION ND RE TO E DETERMINED T DTUM PLNE W. MILLIMETERS INCHES DIM MIN MX MIN MX C D F G 0.65 SC SC H J J K K L 6.40 SC SC M

9 PCKGE DIMENSIONS SOEIJ4 F SUFFIX CSE 9650 ISSUE O e 4 8 Z D 7 E H E VIEW P M L E Q L DETIL P NOTES: DIMENSIONING ND TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSIONS D ND E DO NOT INCLUDE MOLD FLSH OR PROTRUSIONS ND RE MESURED T THE PRTING LINE. MOLD FLSH OR PROTRUSIONS SHLL NOT EXCEED 0. (0.006) PEIDE. 4 TERMINL NUMERS RE SHOWN FOR REFERENCE ONLY. 5 THE LED WIDTH DIMENSION (b) DOES NOT INCLUDE DMR PROTRUSION. LLOWLE DMR PROTRUSION SHLL E 0.08 (0.003) TOTL IN EXCESS OF THE LED WIDTH DIMENSION T MXIMUM MTERIL CONDITION. DMR CNNOT E LOCTED ON THE LOWER RDIUS OR THE FOOT. MINIMUM SPCE ETWEEN PROTRUSIONS ND DJCENT LED TO E 0.46 ( 0.08). MILLIMETERS INCHES b DIM MIN MX MIN MX 0.3 (0.005) M 0. (0.004) b c D E e.27 SC 0 SC H E L E M 0 0 Q Z.42 6 c 9

10 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should uyer purchase or use SCILLC products for any such unintended or unauthorized application, uyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PULICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. ox 632, Phoenix, rizona US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Japan: ON Semiconductor, Japan Customer Focus Center 29 Kamimeguro, Meguroku, Tokyo, Japan 3005 Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. MC454/D

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