Introduction to Virtuoso & Calibre
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- Leon Reynolds
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1 Introduction to Virtuoso & Calibre Courtesy of Dr. and Dr (479)
2 Process Design Kit (PDK) The manufacturing grid defines the minimum resolution The manufacturing grid is the grid on which all design-rules are based. No shape may exist in the database that is not aligned to this grid. The manufacturing grid is 2.5 nm for FreePDK45 Design Rules: A complete list can be found at: Environmental Variables and Path: $PDK_DIR: /tools/library/freepdk45/ CDS.LIB: SOFTINCLUDE /tools/cadence/ic616/share/cdssetup/cds.lib 2
3 Metal Stack Pitch (nm) Thickness Resistivity Via size via R Name Purpose (Width/Space) (nm) (ohm/sq) (nm) (ohm) V9 ILD M9-10 Global 1600 (800/800) V7-8 ILD M7-8 Thin-Global 800 (400/400) V4-6 ILD M4-6 Semi-global 280 (140/140) V2-3 ILD M2-3 Intermediate 140 (70/70) V1 ILD M1 Local 130 (65/65) Contact Poly-Dielectric Poly Gate 125 (50/75)
4 Design Rules: Poly Rule Value Description POLY.1 50 nm Minimum width of poly POLY nm Minimum spacing of poly AND active POLY.3 55 nm Minimum poly extension beyond active POLY.4 70 nm Minimum enclosure of active around gate POLY.5 50 nm Minimum spacing of field poly to active POLY.6 75 nm Minimum spacing of field poly 4
5 Design Rules: Well Rule Value Description WELL.1 none nwell/pwell must not overlap WELL nm Minimum spacing of nwell/pwell at different potential WELL.3 WELL nm Minimum spacing of nwell/pwell at the same potential 200 nm Minimum width of nwell/pwell 5
6 Design Rules: Implant Rule Value Description IMPLANT.1 70 nm Minimum spacing of nimplant/ pimplant to channel IMPLANT.2 25 nm Minimum spacing of nimplant/ pimplant to contact IMPLANT.3/4 45 nm Minimum width/ spacing of nimplant/ pimplant IMPLANT.5 none Nimplant and pimplant must not overlap 6
7 Design Rules: Active Rule Value Description ACTIVE.1 90 nm Minimum width of active ACTIVE.2 80 nm Minimum spacing of active ACTIVE.3 55 nm Minimum enclosure/spacing of nwell/pwell to active ACTIVE.4 none active must be inside nwell or pwell 7
8 Design Rules: Contact Rule Value Description CONT.1 65 nm Minimum width of contact CONT.2 75 nm Minimum spacing of contact contact must be inside active or poly CONT.3 none and M1 Minimum enclosure of active around CONT.4 5 nm contact Minimum enclosure of poly around CONT.5 5 nm contact Minimum spacing of contact and CONT.6 35 nm gate CONT.7 90 nm Minimum spacing of contact and poly 8
9 Design Rules: M1 Rule Value Description M nm Minimum width of M1 M nm Minimum spacing of M1 M1.3 Minimum enclosure around contact 35 nm on two opposite sides M1.4 Minimum enclosure around via1 on 35 nm two opposite sides M1.5 Minimum spacing of M1 wider than 90 nm 90 nm and longer than 900 nm Minimum spacing of M1 wider than M nm 270 nm and longer than 300 nm Minimum spacing of M1 wider than M nm 500 nm and longer than 1.8um Minimum spacing of M1 wider than M nm 900 nm and longer than 2.7 um M1.9 Minimum spacing of M1 wider than 1.5 um 1500 nm and longer than 4.0 um 9
10 Device Corner NMOS PMOS Nominal Corner VTL VTG VTH VTL VTG VTH Ion (ua/um) Ioff (na/um) Igate (A/cm2) FF Corner VTL VTG VTH VTL VTG VTH Ion (ua/um) Ioff (na/um) Igate (A/cm2) SS Corner VTL VTG VTH VTL VTG VTH Ion (ua/um) Ioff (na/um) Igate (A/cm2)
11 Initiating Environment Initiating Environment in tcsh initrc cni-j initrc FreePDK45 initrc ic616 Modify cds.lib file to reflect the right path Launch Virtuoso in background virtuoso & 11
12 Command Interpreter Window (CIW) CIW The first window that appears is called the CIW Open associated tools with virtuoso You can type skill command there, for automated tasks 12
13 Library Manager Browse all library contents 13
14 New Library File->New->Library You can attach to (reuse) existing technology library Or create from a technology file (.tf) 14
15 New Cell View File->New->Cell View You can create layout or schematic 15
16 Layout Editor Full (F) or Partial (P) select 16
17 Visibility/Selectability V: visible, S: Selectable 17
18 Display Options Options->display Be careful on grid controls And display levels 18
19 First NMOS Transistor Create->Instance w/l: width/length Fingers: Number of folded device 19
20 Multi Finger Transistors Two Fingers 20
21 Add Text Pins Select Metal1 net layer Create->Label Add A, Y, vdd!, gnd!! Denotes global nets in SPICE Attach label to Metal1 21
22 Finish Layout Add pin names on M1 Finish routing cells 22
23 DRC/LVS/PEX Rules Runset file $PDK_DIR/ncsu_basekit/cdssetup/runset.calibre.XXX replace XXX with DRC/LVS/PEX Rule file location $PDK_DIR/ncsu_basekit/techfile/calibre/calibreXXX.rul replace XXX with DRC/LVS/xRC 23
24 Run DRC Make sure DRC is clean Calibre->Run nmdrc Save the design before run 24
25 Calibre DRC RVE Calibre RVE visualizes the DRC/LVS/PEX results If error is found, violation will be reported If no error, result=0 25
26 Run LVS Make sure LVS is clean Calibre->Run nmlvs Put your source netlist in Input/Netlist/Spice Files Then Run LVS 26
27 Calibre LVS RVE Clean LVS (smiling face) 27
28 Run PEX Calibre -> Run PEX Choose HSPICE Format and enter extracted netlist filename The Netlist tab is the same as LVS Choose R+C+CC Then Run PEX 28
29 Extracted Netlist New files created containing parasitics 29
30 Calibre PEX RVE Parasitic report on each net 30
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