Color Plates SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 7

Transcription

1 Color Plates SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 7

2 FIGURE CP.1 Layout and cross section of an N-Well CMOS process using 2D models in SIMPL-2 [rzz.lee.phd]. FIGURE CP.2 Magnified view of a CMOS cross section with doping concentration displayed along a cut-line [rzz.wu.ms] 8 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

3 FIGURE CP.3 Layout and cross section for a N-well CMOS process using vertical extrusion in SIMPL-1 [rzz.grimm.ms]. FIGURE CP.4 Evolution of device topography and doping during a CMOS process flow using SIMPL-1 a) LOCOS stack for well, b) N-well implant and drive, c) LOCOS stack for active area, d) channel-stop implant, e) field oxide, f) gate oxide and polysilicon, g) n + source/drain and well contact implant, h) p + source/drain implant, i) PSG dielectric and contact openings, j) blanket aluminum, and k) patterned aluminum [rzz.grimm.ms]. 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 9

4 FIGURE CP.5 Layout and cross section for a bipolar transistor [rzz.grimm.ms]. FIGURE CP.6 Layout for a logic gate as seen in the MAGIC IC Design System using a standard double level metal CMOS technology as defined in the circuit design textbook by Rabaey [rzz.rabaey]. 10 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

5 FIGURE CP.7 Cross section along a cut-line through the device for the double level metal CMOS logic gate. FIGURE CP.8 Cross section along a cut-line through the interconnect for the double level metal CMOS logic gate. FIGURE CP.9 Cross section with misalignment made with WORST showing that an electrical short does not occur even when the POLY and MET2 masks overlap [rzz.wu.ms]. FIGURE CP.10 HUNCH boolean expressions which determine the location of potential metal topography problems [rzz.wu.ms]. SEE NEXT PAGE 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 11

6 FIGURE CP.11 HUNCH highlight of the location of potential metal topography problem [rzz.wu.ms] 12 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

7 FIGURE CP.12 Cross section with highlighted acute topography feature found by CRITIC [rzz.wu.ms]. FIGURE CP.13 DRAM layout and cross section along the diagonal metal strap [rzz.lee.phd]. 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 13

8 FIGURE CP.14 DRAM layout and cross section along the horizontal wordline [rzz.lee.phd]. FIGURE CP.15 DRAM layout and cross section along the horizontal word line with same process except that the CREEP reflow of the PSG dielectric was omitted leaving cracks which become more severe with additional process steps [rzz.lee.phd]. 14 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

9 FIGURE CP.16 Layout and cross section of a N-well CMOS device integrated with a MEM structure [rzz.lee.ms]. FIGURE CP.17 Layout and cross section of the MEM structure showing that if overetching is not used a polysilicon stringer interconnects the left point and right pointing fingers [rzz.lee.ms] 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 15

10 FIGURE CP.18 Layout and cross section of a BiCMOS process simulated by SIMPL-2 [rzz.cole and logan]. FIGURE CP.19 Example of extraction of parasitic electrical effects of the nonplanar interconnect by determining the curvilinear squares of each face in the cross section [rzz.scheckler.ms]. 16 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

11 Not Available yet. FIGURE CP.20 Cross section of the double level metal CMOS logic when a MET2 to source/drain contact is attempted and a misalignment which is permitted in the current design rules occurs. FIGURE CP.21 Layout and cross section for a BiCMOS technology in which a polysilicon collector plug is used to contact the buried layer and stitch-back between SIMPL and SUPREM4 is utilized [rzz.vlsi.scheck]. FIGURE CP.22 Focused Ion Beam device cross section and its simulation [rzz.tazawa.ntt]. 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 17