ASIC Computer-Aided Design Flow ELEC 5250/6250
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1 ASIC Computer-Aided Design Flow ELEC 5250/6250
2 ASIC Design Flow
3 ASIC Design Flow DFT/BIST & ATPG Synthesis Behavioral Model VHDL/Verilog Gate-Level Netlist Verify Function Verify Function Front-End Design Test vectors Full-custom IC Standard Cell IC & FPGA/CPLD DRC & LVS Verification Transistor-Level Netlist Physical Layout Map/Place/Route Verify Function & Timing Verify Timing Back-End Design IC Mask Data/FPGA Configuration File
4 Front-End Design & Verification VHDL Verilog SystemC QuestaSim (digital) Leonardo Spectrum, Synopsys - Design Compiler, Xilinx ISE (digital) QuestaSim (digital) Tessent DFTAdvisor, Fastscan Technology-specific netlist to back-end tools Create Behavioral/RTL HDL Model(s) Simulate to Verify Functionality Synthesize Circuit Simulate to Verify Function/Timing Design for testability ATPG Simulate to Verify Function/Timing VHDL-AMS Verilog-AMS Questa ADMS (analog/mixed signal) Design Constraints Technology Libraries VITAL Library ATPG Library VITAL Library
5 ASIC back end (physical) design Assume digital blocks/standard cells (can also do full custom layout, IP blocks, mixed-signal blocks, etc.) ASIC Hierarchical Netlist Std. Cell Layouts Libraries Process data, Design rules Floorplan Chip/Blocks Plan Rows, Place & Route Std. Cells Cadence SOC Encounter Virtuoso Generate Mask Data IC Mask Data Design Rule Check (DRC) Extract Parasitics, Backannotate Schematic ADiT Simulation Model Layout vs. Schematic (LVS) Check Calibre Calibre Calibre
6 Cadence SOC Encounter Mod7 Counter Layout
7 SoC Design Flow (Using IP cores) Hardware IP cores Purchase HW cores Purchase SW drivers Software drivers IP Vendors: core design Integrated Hardware SoC Design specifics HW/SW partitioning Integrated Software Functional Simulation Prototype on platforms e.g. FPGA Software Simulation Fabless Vendors: SoC design Physical optimization and fabrication HW/ SW co-verification Application development and test Volume manufacture and ship Foundries: Chip fabrication PCB manufacture and device assembly Device vendors: Final products
8 ASIC CAD tools available in ECE Modeling and Simulation Modelsim, Questa-ADMS, Eldo, ADiT (Mentor Graphics) Verilog-XL, NC_Verilog, Spectre (Cadence) Active-HDL (Aldec) Design Synthesis (digital) Leonardo Spectrum (Mentor Graphics) Design Compiler (Synopsys), RTL Compiler (Cadence) Design for Test and Automatic Test Pattern Generation Tessent DFT Advisor, Fastscan, SoCScan (Mentor Graphics) Schematic Capture & Design Integration Pyxis Design Architect-IC (Mentor Graphics) Design Framework II (DFII) - Composer (Cadence) Physical Layout Pyxis IC Station (Mentor Graphics) SOC Encounter, Virtuoso (Cadence) Design Verification Calibre DRC, LVS, PEX (Mentor Graphics) Diva, Assura (Cadence)
9 IC Process Design Kits (PDKs) Foundry-specific data and models for a specific IC technology Used by the design tools Design components for both front-end & back-end design Design entry/modeling Technology/process data Layer definitions/parameters (Trans, R,C, ) Design rules Standard Cell Library Synthesis library Simulation models (Verilog, transistor) Physical designs (LEF models) Timing models (fast, typical, slow) Verification (DRC,LVS,PEX) DFT/test generation IP and device generators (RAM, etc.)
10 Global Foundries BiCMOS8HP 130nm PDK
11 Global Foundries BiCMOS8HP 130nm PDK Physical Design Cells - FILLx (row fill cells, x=1,2,4,8,,128) - FGTIE (floating-gate tie-down) - NWSX (substrate and n-well taps) I/O
12 Global Foundries PDK Directory Structure IBM_PDK/bicmos8hp/<version>/ Subdirectory Contents doc/ cdslib/bicmos8hp /esd8hp /Skill /examples /doc Assura/DRC /LVS /doc EM/ /doc /EMX /Momentum HSPICE/models /doc Spectre/models /doc utils/ Technology Design Manual Model Reference Guide Layer Mapping File Cadence BiCMOS8HP Device Library (IC61) Cadence BiCMOS8HP ESD Library Context Files (Skill Utilities) Example Setup Files Cadence Library Documentation DRC Files LVS Files Assura Release Notes Electromagnetic Enablement E-M File Release Notes and Guide EMX Proc Files Momentum Layer and Substrate Files HSPICE Device Model Files HSPICE Release Notes Spectre (Direct) Device Model Files Spectre Release Notes Kit Utility Programs
13 FPGA Design Flow Behavioral Design Verify Function Mentor Graphics Front-End Tools (Technology-Independent) Synthesis Gate-Level Schematic Verify Function Xilinx/Altera/Other Back-End Tools (Technology-Specific) Map, Place & Route EDIF Netlist Verify Timing FPGA Configuration File
14 Xilinx/Altera FPGA/CPLD Design Tools Simulate designs in Modelsim (or other simulation tools) Behavioral/RTL models (VHDL,Verilog) Synthesized netlists (VHDL, Verilog) Requires primitives library for the target technology Synthesize netlist from behavioral/rtl model Vendor-provided: Xilinx Vivado (previously ISE), Altera Quartus II Leonardo (Levels 1,2,3) has FPGA & ASIC libraries (ASIC-only version installed at AU) Vendor tools for back-end design Map, place, route, configure device, timing analysis, generate timing models Xilinx Vivado (previously ISE - Integrated Software Environment) Altera Quartus II Higher level tools for system design & management Xilinx Platform Studio : SoC design, IP management, HW/SW codesign Mentor Graphics FPGA Advantage
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