BITSTACKING WITH ONLY A COMPOSER SCHEMATIC EDITOR LICENSE TONY LAUNDRIE IC DESIGN ENGINEER. P.O. BOX 4000 CHIPPEWA FALLS, WI

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1 BITSTACKING WITH ONLY A COMPOSER SCHEMATIC EDITOR LICENSE TONY LAUNDRIE IC DESIGN ENGINEER P.O. BOX 4000 CHIPPEWA FALLS, WI atl@sgi.com INTERNATIONAL CADENCE USER GROUP CONFERENCE SEPTEMBER 10-13, 2000 SAN JOSE, CALIFORNIA

2 1. Introduction The circuit designers for a recent Silicon Graphics project wanted to manually specify the placement of standard cells. Their schematics were created in Cadence using a library of IBM standard cell symbols. The target place-androute tool was IBM s Chipbench/Chipedit, which we had in house. In the past, hand-drawn sketches or Framemaker drawings were given to a Chipbench expert for cell placement. We wanted to give the schematic designers a bitstacking tool, but without forcing them to leave the Cadence framework, and without spending money on additional licenses or new tools. The project had plenty of Cadence schematic editor ( Composer ) licenses, but Cadence layout editor ( Virtuoso ) and IBM Chipbench licenses were scarce. This paper describes how we used a perl script to convert IBM s VIM/PHYSICAL format into Cadence abstract views, then how we wrote Skill code to initialize a floorplan view, display flight lines, and write the final placement in IBM s Chipbench format. This allowed our circuit designers to arrange standard cell abstract views within a floorplan drawing using only a Cadence schematic editor license. The basic concept is that the Cadence design framework, which supports core-level db Skill functions, menus, and GUI options, does not really care whether a cellview s objects are part of an IC mask or a schematic drawing. In a way, this method of bitstacking is like editing a schematic where the symbols are the same shape as the physical layout. Until you require more advanced options like those in Virtuoso or other products, DFII and Composer features are sufficient. 2. Requirements Ideally we would have had a Cadence standard cell library of abstract or layout views already, but all we had to start was an early version of an IBM standard cell design kit. It contained a directory of PHYSICAL files describing each standard cell s size, boundary, pin, and blockage information. After developing a technology file containing the appropriate metal layers, a short perl script was used to convert PHYSICAL files into Skill commands to draw Cadence abstract views. We enhanced our abstract views with labels to show a cell s part name and instance name when it was instantiated. The cell name was drawn in the lower left corner, and the instance name was drawn in the upper right, both on the text.dg layer. This made it easy to see this information without bringing up the object property form. (Note: for instance name, thelabel= [@instancename], labeltype= NLPLabel ) The IBM PHYSICAL format actually defines OPENS instead of obstructions. To create blockage shapes in the abstract views, we used the lelayerandnot() Skill function, which requires a Cadence layout editor license. We could have done without the blockage layers in our abstracts, but it was only a one-time requirement we did have at least one Virtuoso license. After several months IBM gave us a LEF directory of the standard cells. This could have been imported into a Cadence library using standard menus, but it still would have required a license beyond Composer schematic editor. The schematic editor does not require a technology file for normal schematic and symbol editing, but to view and edit floorplan drawings, the parent library needs to have technology information for metal layers. One way to do this is to attach the standard cell abstract library technology file to the working library. A floorplan drawing is stored alongside schematics and symbols in a cellview with viewname= floorplan and cellviewtype= schematicsymbol. This methodology was developed using Cadence version 4.4.x, which makes it easy to create arbitrary cellview names. A floorplan cellviewtype is schematicsymbol instead of schematic because the schematic symbol editor is more generic and flexible for this application. 3. Initializing Skill code is used to define a custom menu and popup form to start the process of converting a schematic into a floorplan drawing. The form prompts for the source schematic s libname,

3 cellname, and viewname; the destination floorplan s libname, cellname, and viewname; and a boolean button to allow the user to keep existing placements or start over from scratch. Below is an example of a schematic view and the resulting initial floorplan view: initialize wrklib / ao22 / schematic wrklib / ao22 / floorplan i/o labels: (origin) + The Skill algorithm for creating the floorplan is: Check-and-save the schematic with schcheck, dbsave. Open the destination cellview with cellviewtype= schematicsymbol Set up to snap objects to half the routing grid: c->xsnapspacing=0.5, c->ysnapspacing=0.5, c->gridspacing=1.0 For each symbol in the schematic: If ipin, opin, or iopin: draw a label below the origin down the Y axis. Otherwise, look for a floorplan or abstract view. If found, instantiate the floorplan or abstract view to the left of the origin along the X axis. During that last step, abstract views must be scaled for the schematic grid. Here is sample Skill code to do it: i = dbopencellview( floorplan or abstract cellview ) mag = 1.0 m = 1.0 (if (i~>cellviewtype == "masklayout") then ; if abstract or layout view m = 1.0/pitch mag = 160.0/1000.0/pitch ) j = ceiling( (xcoord(upperright(i~>bbox)) - xcoord(lowerleft(i~>bbox)))*m) ; place instances along X axis, ; two tracks apart x = x - j j = floor( xcoord(lowerleft(i~>bbox))*m) q = dbcreateinst(c i ii~>name x-j:y0 "R0") ; ii->name is name of ; schematic inst q~>mag = mag Pitch is the track-to-track distance as measured in an abstract view. X is a running x coordinate of where to place the next instance along the X axis. Within a floorplan view, we wanted the user to measure things in routing tracks, so that the distance between two minimum-spaced pins would be 1.0. To allow this, an abstract s instance is scaled (using the mag attribute) by the manufacturing pitch of the abstract view and the ratio of DBUPerUU used in schematics vs. layouts. If a user makes changes to a schematic but already has an existing floorplan view, the above steps can be expanded to add, modify, or delete cell instances that changed, maintaining the locations of unchanged cells. In this incremental mode, we also deleted all of the floorplan cellview s textdisplays, which resets all instance and cell names to their default locations. This is a hack; we found that if a user accidentally moved the cell name or instance label of an instantiated

4 abstract, it could not be selected in the future to move again. 4. Editing Most normal symbol editing GUI functions can be applied in the floorplan drawing: move/flip/rotate cells, draw shapes, etc. A set of Skill routines was developed to show rats-nest connectivity through flight lines. We already had some code to do this for ordinary layout and schematic views, since the Show Direct Connections or Display Nets options from Cadence were not satisfactory. Our rats-nest skill code uses the schematic view as a netlist reference, then draws matching connectivity segments (using a hilite layer) on the floorplan view with a nearest neighbor algorithm. A popup form can be used to select and highlight only a subset of nets. The drawing on the left below shows a floorplan view with the gates moved around and the rats-nest displayed. The rats-nest code assumes that top-level text shapes having a label purpose are for identifying pins. In the drawings below, the labels have been moved from their initial placement along the Y axis to be above one of their connected pin shapes. When this sub-floorplan is instantiated hierarchically, the top-level labels are used by the rats-nest code for pin locations. After a designer has cells roughly arranged in their relative locations, a legalization menu item snaps all the instances to legal placement locations. Every other row is flipped vertically. The drawing on the right above shows the result of this step. A rectangle has also been added around the whole subcell, and another label has been placed in the lower left corner to help identify the cell at higher levels. Manual manipulation of floorplan logic could become tedious for large designs. For more complicated datapath logic, a user could specify placement of bitstack arrays using a variety of Skill procedures. 5. Hierarchy In the schematic below, the subcell above has been instantiated with another standard cell to demonstrate additional layers of hierarchy. The initial floorplan view is shown below. In this case, the sub-floorplan instance is initialized with mag=1. The drawing at the top of the next page shows the completed cell with flight lines visible. The legalization code optionally descends into the hierarchy, so if the subcell had been placed up one row, its cells would have been flipped vertically to snap to the global row pattern. rats nest view after legalization

5 begin_group_list group_name grp_aoi22 I0 XOFFSET=0.0 YOFFSET=0.0 I1 XOFFSET+=0.65 YOFFSET+=0.05 end_group_list If exporting to another place-and-route tool, it should be possible to output the results in standard DEF format as well. 7. Summary This paper explained a way to use the graphical editing capabilities of the Cadence DFII Composer schematic editor to represent standard cell layout information, without requiring a Cadence Virtuoso layout license. 6. Exporting Another Skill code routine, accessible via a custom menu, recursively looks at each instance in a floorplan cellview and generates placement instructions for the target place-and-route tool. In our case, this was IBM s Chipbench. For the example cell above, the resulting group place file looks like this: begin_group_place PLACE grp_ao N 0 end_group_place /* CELL: ao22, 9 tracks wide, 2.0 rows tall */ begin_group_list group_name grp_ao22 I1 XOFFSET=0.0 YOFFSET=0.0 I0 XOFFSET+=0.0 YOFFSET+=2.3 MIRROR=YES ROTATE=0 I2 XOFFSET+=0.5 YOFFSET+=0.0 MIRROR=YES ROTATE=0 end_group_list There are many features available in Virtuoso or floorplanning programs that are missing from this methodology, like rulers, automatic placement, net length estimation, congestion analysis, adding preroute wires, etc. Although more bells and whistles could be added to this flow, at some point it makes more economic sense to simply buy Virtuoso or learn another tool. As it stands, this flow is only intended to be an inexpensive step above a Framemaker drawing. Color PDF versions of this document and presentation slides are available at begin_group_place PLACE grp_aoi N 0 end_group_place /* CELL: aoi22, 9 tracks wide, 2.0 rows tall */