Lecture 23 Encounter in Depth and Conclusion
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1 Lecture 23 Encounter in Depth and Conclusion Xuan Silvia Zhang Washington University in St. Louis
2 Some Final Administrative Stuff 2
3 Class Project Presentation Presentation order Team 1 through 5 16min per team (14min presentation + 2min Q&A) all team members must participate Suggested contents brief intro design approach/debug methods behavioral simulation results design compiler results, post-synthesis simulation physical layout achieved performance (speed, power, area) lesson learned 3
4 Final Project Report Due on 12/12 at noon Single submission as a team Required contents design strategy (techniques applied) achieved performance report where the numbers come from detailed explanation on the simulation results behavioral simulation synthesized simulation digest of the timing, power, and area reports division of work, individual contribution appendix: all source codes, netlist, screen capture, etc (see final project description) 4
5 Course Evaluation Appreciate your feedback Start on today Please complete by December 12 th Will account for 3 points in the final grade 5
6 Encounter in Depth 6
7 Chapter 4: Data Preparation Technology file design rules and physical library:.lef I/O assignment manually create I/O assignment file Timing libraries.lib Timing constraints.sdc (write_sdc) Check designs checkdesign 7
8 Chapter 5: Importing and Exporting Designs Prepare the netlist synthesized netlist with unique cell types (.syn.v) Begin with LEF and Verilog page 123 Load config files loadconfig Save and restore designs Import and export design data floorplan, I/O, etc. Convert to GDSII setstreamoutmode 8
9 Chapter 12: Floorplanning the Design Chapter 13: Power Planning and Routing Utilization Edit Pins use the Pin Editor: spreading pins, spacing Resize and Rotate Add core ring core ring, block ring Add stripes core area, over block area Global net connections globalnetconnect type pgpin pin pin_name all - override 9
10 Chapter 15: Placing the Design Prepare for placement checkdesign, checkplace timedesign preplace createobstruct (no need) plandesign or manual place and fix hard blocks Add well-tap and end-cap cells Place standard cells placedesign setplacemode Check Placement checkplace 10
11 Chapter 16: Synthesizing Clock Trees Clock tree specification file automatic mode Pre-CST and post-cst optimization ckeco preroute ckeco clkrouteonly ckeco postroute reportclocktree -postroute 11
12 Chapter 16: Synthesizing Clock Trees 12
13 Chapter 20: Using the NanoRoute Router Routing Phases global routing detailed routing: switch boxed (SBoxes) Preparation checkplace, verifygeometry (optional) Specify routing layer -routebottomroutinglayer -routetoprouting Layer Routing commands routedesign, setnanoroutemode, setattribute globalroute, detailroute Check congestion 13
14 Monitoring and Verification Utilization (floorplanning) target utilization (TU=%), effective utilization (EU=%) Congestion analysis table Verify violations (Chapter 34) connectivity metal density geometry antennas 14
15 Conclusion 15
16 Topics Covered Technology and Methods digital binary logic, Moore s Law level of abstraction -> design automation principles Design Flow Algorithmic and architecture optimization Synthesis: power, area, timing constraints Static Timing Analysis Physical Design: floorplan, place and route Languages and Tools Verilog, Tcl Synopsys VCS (Verilog Simulation) Synopsys Design Compiler (Netlist Synthesis) Cadence SOC Encounter (Physical Design) 16
17 17
18 The Trend: Follow, Catch, or Create? Intelligent Recognition computer vision, artificial intelligence Internet of Things Sensing (Analog) Computing (Digital) Wireless (RF) Energy harvesting (Power) Software-Hardware Co-design Analog/Digital/Mixed Signal/Radio Interface/Communication/Internet/Cloud Application/Regulation/Resource/Material 18
19 ESE 566A: Modern System-on-Chip Design Advanced topics system-on-chip software/hardware partition high-level synthesis reliability, resilience, security More Project-centric More open-ended and research-oriented 19
20 Research Theme (XZ Group) Problem designing micro-scale autonomous systems with enhanced security and resilience. Approach co-design of algorithm, computer architecture, circuits, and sensing and actuation mechanisms. Projects reconfigurable deep learning hardware energy-efficient software-assisted power delivery verifiable hardware against side-channel attack sensor-fusion chip for vision-based robotic control analog-coprocessor to speed up scientific computing novel devices for non-reciprocal energy transfer 20
21 21 Questions? Comments? Discussion?
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