Advanced Techniques for Using ARM's Power Management Kit

Transcription

1 ARM Connected Community Technical Symposium Advanced Techniques for Using ARM's Power Management Kit Libo Chang( 常骊波 ) ARM China 2006 年 12 月 4/6/8 日, 上海 / 北京 / 深圳

2 Power is Out of Control! Up to 90nm redu ction in voltage co mpen sates for increase in gat es, 65nm voltage id entical to 90n m 180nm 130nm 90nm 65nm 25mm 2 die area per process node 75% standard cells 80% utilization dynamic pow er at 250MHz; 30% activity leakage pow er at 125C, FF, VDD+10% Leakag e po wer for G process can be similar to d ynamic po wer at 65nm 180nm 130nm 90nm 65nm 2

3 Consumer Applications Require Power Control Application Cell phone Smart phone Laptop Handheld computer Portable Media Player Power Requirements Extremely long standby time Long battery life in usage Very long battery life for , browsing Good performance for gaming Very long battery life Good video quality GPS Unit Long battery life in usage 3

4 Power Optimization Technology Architecture Level Intelligent Energy Manager Systems Chip Level Power domains, voltages islands Block Level Power down and sleep mode Logic Level Mixed Vt, clock gating Process Level Low-power processes, Vt options 4

5 Physical IP: Low-Power Design Flexible Use Models of Advance d SoC Designs Flexible Power Optimization Technologies Sleep modes Retention Low-power modes Voltage scaling Back-biasing Physical IP for Power Management 5

6 Power Management with PMK

7 The PMK Complements ARM Standard Cell Libraries High Speed Power Management Kit complements ARM standard cell libraries SAGE-HS PMK Advantage-HS PMK Low Power Small Area Advantage SAGE-X PMK PMK Metro PMK PMK PMK 180nm 130nm 90nm 65nm Process Geometry 7

8 The PMK Optimizes Power at Two Levels Architecture Level Intelligent Energy Management Systems Chip Level Power domains, voltages islands Block Level Power down and sleep mode Enabled by ARM s Power Management Kit Logic Level Mixed Vt, clock gating Process Level Low power processes, Vt options 8

9 SoC Power Optimization Fixed Voltage Block Controller with constant performance requirements Reduc e dynamic and leakage power Flexible Voltage Block Processor with changing performance requirements Opti mize dynamic power for act ual requirements Power-Gated Voltage Block Specialized multimedia functions switched on or off Reduc e l eakage in sleep mode Small latency for wake- up 9

10 SoC Power Optimization Fixed Voltage Block Controller with constant performance requirements Reduc e dynamic and leakage power Flexible Voltage Block Processor with changing performance requirements How to reduce power? t 0 V I DD lkg + t 0 CV 2 DD f c Clock gating for dynamic power reduction Mixed-Vt implementation for leakage optimization Power-Gated Voltage Block Specialized multimedia functions switched on or off What is needed in SoC? Clock gating cells Mixed Vt libraries 10

11 Integrated Clock Gating (ICG) Cell Clock registers only when needed Decreased switching activity reduces dynamic power Typical chip level power savings of >30% ARM libraries have scan and non-scan version of the ICG cell (8-drive sizes each) Inserted automatically by DC / RTL compiler during synthesis Skew < Delay (CLK -> Q) EN A Latch B Gated_CLK CLK ICG_cell 11

12 Benefits of Multi-Vt 1,000,000 ~6x reduction at high leakage corner CL013G SVt vs. HVt 100,000 ~5X to ~10x reduction at typical/fast corner Leakage (pw) 10,000 1,000 NAND RVt NAND HVt 100 FF 1.32V 125C SS 1.08V 125C TT 1.2V 25C FF 1.32V -40C 12

13 SoC Power Optimization Fixed Voltage Block Controller with constant performance requirements Flexible Voltage Block Processor with changing performance requirements Opti mize dynamic power for act ual requirements How to reduce power? t 0 CV 2 DD fc Reducing voltage from 1.2V to 0.8V saves over 50% of dynamic power! Power-Gated Voltage Block Specialized multimedia functions switched on or off What is needed in SoC? Level shifters to ensure correct functionality with other blocks Low voltage characterization to ensure performance at different voltage levels 13

14 Level Shifters Island A Low V olta ge Domai n Island B High Vol ta ge D omain Low V olta ge Signal Down shifte r High Voltage Signal VDDI Low V olta ge Up shifter High Vol ta ge Level Shifters provide shift up, shift down functionality Proper interface between islands of different voltage levels Available with and without enable/clamp signal and with different drive sizes Dual-voltage characterization for all level shifters Separate voltage value for input and output voltage 14

15 Extensive Low Voltage Characterization Example for 1.2V process: Nominal Vdd Best Case P=FF, T = -40C Best Case P=FF, T = 0C Typical Case P=TT, T=25C Worst Case P=SS, T=125C Leakage Worst Case P=FF, T=125C 1.2V 1.32V 1.32V 1.2V 1.08V 1.32V 1.0V 1.1V 1.1V 1.0V 0.9V 1.1V 0.8V Accurately derate an y voltag e b et ween two characterization points 1.08V 0.9V 0.96V Standard Characterization Additional Characterization corners CCS or ECSM models for accurate simulation over continuous voltage range 15

16 SoC Power Optimization Fixed Voltage Block Controller with constant performance requirements Flexible Voltage Block Processor with changing performance requirements How to reduce power? t 0 V I DD lkg Powering down of unused function blocks drastically reduces leakage power Power-Gated Voltage Block Specialized multimedia functions switched on or off What is needed in SoC? Power gates Retention flip-flops Optional back-biasing Reduc e l eakage in sleep mode Small latency for wake- up 16

17 Use Power Gates to Reduce Leakage Control power to a block Shutdown unused circuitry Local rails become switchable Enables power-down/sleep mode Coarse-grain power gates for multiple cells Header Switch VDD VDDG SLEEP Footer Switch SLEEP VSS VSSG 17

18 Power Gates Are Flexible Choose header to switch VDD Choose footer to switch VSS Choose gate with or without buffered control signal Choose from several transistor sizes Place as standard cell Exam ple Footer sw itch same cell height as standard cells 18

19 Retention Flip-Flop Retention st age FF region which can b e po wered down Global po wer and/or ground connected to main supply Local VDD Local VSS Global VSS Global VDD Note: Picture shows a conceptual implementation Maintain FF state after power down Extreme low leakage without loss of flip-flop state Retention flip-flops consists of main stage and storage stage Main stage is connected to switchable (local) power rail, standard or low Vt Storage stage (high Vt) is connected to global power/ground to maintain flip-flop state with minimal leakage current 19

20 Retention Flops Save State With Low Leakage 1. D-flop main stage (SVt or LVt) No leakage when retaining state Connects to switchable (local) power rails 2. D-flop retention stage (HVt) Low leakage when retaining state Connects to global (always-on) power 20

21 Special Fill Cells for Back-Biasing Standard FILL_TIE FILL_TIE_B B VDD Well contacts to VDD/VSS by default VDD VNW Contact w ells through pins VNW and VPW VPW VSS VSS Enables back or forward biasing for performance/leakage optimization N-well voltage different from VDD P-well voltage different from VSS (triple well process) Bias voltage routed as signal pin 21

22 NMOS Example with Well Access Drain Gate VPW ID Gate Source Drain n+ n+ ID p-w ell VPW Source Control voltage on 4 th terminal: VPW Connect to NMOS Bulk through VPW pin in Special Fill Cells When VPW < Source V th increases I D decreases Leakage Decreases 22

23 Level Shifters And Isolation Cells for Power Islands Island A Low V olta ge Domai n ENABLE _B Island B High Vol ta ge D omain Low V olta ge Down shifter High Voltage Signal VDDI Low V olta ge Si gnal Up shifter High Vol ta ge ENABLE _A Enable lower dynamic power consumption Interface between power islands Isolation cells isolate unknown signals Level shifters shift voltages Level shifters can shift and isolate 23

24 But How to Use PMK?

25 The PMK Fits into the Standard EDA Flow System Specification and Architecture Write RTL / Synthesize Formal Verification Verilog Sims Floorplan / Power Grids Place & Route Formal Verification Back-annotated Verilog Sims Timing Closure DRC / LVS New constructs & commands Verify retention Verify retention and isolate Pow er islands & power gates Level shifters & isolation gates Compare pow er intents Simulate pow er down Liberty extensions Verify P/G connections Tapeout! 25

26 Power Gates Are Placed During Power Planning Create physical power domains / assign voltages Create power mesh Global (always-on) Local (switchable) Place power gates > addpowerswitch` Use tap cell insertion commands Domain #2 Default Domain Power Gates Domain #1 `Supported by SoC Encounter Floorplan added columns of power gates in logic block 26

27 Local Power Grid Distributes Local Power Local Power Ring and Stripes 27

28 Power Gates Are Placed Under Global Grid Power Gates Under Global Grid 28

29 Back Bias Cells Are Placed in Fixed Pattern Site Rows Max Distance = a Max Distance = a/2 Implement as well tap cells auto placement Max Distance between well taps: Found in design rules Half the distance when in every second column 29

30 Place Level Shifters In Receiving Domain Auto placement at island interface astinsertlevelshifter* addshifter run gate level_shifter` Short routes for signals between domains Power from receiving domain Secondary power for up shifters (VDDI) Dual-voltage characterization *Supported by Astro Supported by SoC Encounter `Supported by Magma tools Level Shifters Level Shifter Placement Low Voltage Domain 30

31 Place and Route Design Place logic cells Includes retention flops Power route primary and secondary powers Route signals Level Shifters Power Gate Columns Retention Flops Low Voltage Domain 31

32 Analyze Power Network Run dynamic IR drop analysis Analyze in-rush current for powergated blocks Run static IR drop analysis Power grid IR drop for always-on power Power grid and power gate IR drop for switchable power Level Shifters In-rush current analysis Pictures courtes y of Synops ys, PrimeR ail 32

33 The PMK in Use Up-Shifted Signals Route to Higher Voltage Domains Block using Dynamic Voltage Scaling and Power Gates Low Voltage Domain To High Voltage Domains Low Voltage Outputs to Up Shifters Retention Flops in Block Power Gate Columns 33

34 Low Power EDA Design Flow Support Close collaboration between ARM and EDA companies during development of tools and Physical IP Regular technical meetings with EDA companies Optimize IP and tools to ensure compatibility PMK cell development and emerging tools ensure that cells can be used in an all phases of the design flow Reference flow development Wide range of EDA view support Accurate simulation of low voltage operating points Accurate power estimation with support for standard and emerging EDA tools Extensive model support ensures that all power design challenges can be addressed, e.g., state-dependent leakage power 34

35 Comprehensive Power Management Support for broad range of sophisticated power management techniques Active control of dynamic power Active control of static / leakage power Power Management Kit available as add-on for Metro and Advantage ARM standard cell libraries Power management integrated in Metro and Advantage memories Close collaboration with EDA partners Reference methodologies Modeling and automation Used by the ARM Intelligent Energy Manager technology (IEM) ARM Physical IP Enables Comprehensive Power Management! 35

36 Advanced Techniques for Using ARM's Power Management Kit Thank You!