Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
|
|
- Michael Cobb
- 5 years ago
- Views:
Transcription
1 Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC
2 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational Sequential Output = f(in) Output = f(in, Previous In) Digital IC
3 agenda Static CMOS design Ratioed logic design Pseudo NMOS Pass transistor design Dynamic logic Digital IC 3
4 agenda Static CMOS design Ratioed logic design Pseudo NMOS Pass transistor design Dynamic logic What is the difference between inverter and logic? Digital IC 4
5 Static CMOS logic CMOS static characteristic CMOS propagate delay Large fan-in technology Logic effort CMOS power analysis Digital IC 5
6 Static CMOS Circuit Gate output is connected to either V DD or V SS via a low-resistive path * Contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes * except during the switching transients Digital IC 6
7 Construction of PDN NMOS devices in series implement a NND function NMOS devices in parallel implement a NOR function + Digital IC
8 CMOS NND F Digital IC
9 CMOS NOR + F Digital IC
10 Complex CMOS Gate C D D C OUT =!(D + ( + C)) Digital IC
11 Standard Cell Layout Methodology Routing channel V DD signals GND What logic function is this? Digital IC
12 OI1 Logic Graph j C X C PUN X =!(C ( + )) X i V DD C i j C GND PDN Digital IC
13 Two Stick Layouts of!(c ( + )) C C V DD V DD X X GND GND uninterrupted diffusion strip Digital IC
14 Consistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph X C X i V DD j Digital IC GND Euler path: a path through all nodes in the graph such that each edge is visited once and only once C For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)
15 OI Logic Graph C X PUN D D C X =!((+) (C+D)) X V DD C D C D GND PDN Digital IC
16 OI Layout D C V DD X GND Some functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) Digital IC
17 VTC is Data-Dependent V GS = V V DS1 V GS1 = V M 3 M 4 D M S D M 1 F= Cint S weaker PUN /0.5 NMOS 0.5 /0.5 PMOS,: 0 -> 1 =1, :0 -> 1 =1, :0->1 The threshold voltage of M is higher than M 1 due to the body effect ( ) V Tn1 = V Tn0 V Tn = V Tn0 + ( ( F + V int ) - F ) since V S of M is not zero (when V = 0) due to the presence of Cint Digital IC
18 CMOS Properties Full rail-to-rail swing high noise margins not dependent upon device sizes ratioless lways a path to Vdd or Gnd low output impedance zero steady-state input current high input resistance No direct path steady state no static power Propagation delay function of load capacitance and resistance of transistors Digital IC 0
19 Static CMOS logic CMOS static characteristic CMOS propagate delay Large fan-in technology Logic effort CMOS power analysis Digital IC 1
20 Delay Definitions t pdr : t pdf : t pd : t r : t f : fall time Digital IC Slide
21 Delay Definitions t pdr : rising propagation delay From input to rising output crossing V DD / t pdf : falling propagation delay From input to falling output crossing V DD / t pd : average propagation delay(max-time) t pd = (t pdr + t pdf )/ t r : rise time From output crossing 0.1 V DD to 0.9 V DD t f : fall time From output crossing 0.9 V DD to 0.1 V DD Digital IC Slide 3
22 Delay Definitions t cdr : rising contamination delay Minimum time from input to rising output crossing V DD / t cdf : falling contamination delay Minimum time from input to falling output crossing V DD / t cd : average contamination delay(min-time) Minimum time from input crossing 50% to the output crossing 50% t pd = (t cdr + t cdf )/ Digital IC Slide 4
23 Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! ut simulations take time to write (V) 0.5 V in t pd f = 66ps t pd V out r = 83ps p 400p 600p 800p 1n t(s) Digital IC Slide 5
24 Why we need estimation? We have timing analyzer at different levels The architectural/micro-architectual level Logic level Circuit level Layout level GIGO(Garbage In Garbage Out)! Simulation could only tell how fast, it could not tell how to modify the circuit Digital IC Slide 6
25 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation ut easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding their effective R Depends on average current as gate switches Digital IC Slide 7
26 Input Pattern Effects on Delay R p R n R n R p C L C int Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 R p / C L one input goes low delay is 0.69 R p C L High to low transition both inputs go high delay is 0.69 R n C L Digital IC 8
27 Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t R C pd i to source i nodes i R C R R C... R R... R C R 1 R R 3 R N N N C 1 C C 3 C N Digital IC Slide 9
28 RC Delay Models Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance R, capacitance C Capacitance proportional to width Resistance inversely proportional to width g d k s g d R/k kc s kc kc g d k s g s kc R/k kc kc d Digital IC Slide 30
29 Switch Delay Model R p R p R p R eq R p R n C L R n C L R p C int R n NND C int INV R n R n C L NOR Digital IC 31
30 Example: 3-input NND Sketch a 3-input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R) Digital IC Slide 3
31 Example: 3-input NND Sketch a 3-input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R) Digital IC Slide 33
32 Example: 3-input NND Sketch a 3-input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R) Digital IC Slide 34
33 3-input NND Caps nnotate the 3-input NND gate with gate and diffusion capacitance. C C C C C C C C C 3C 3C 3C C 3C 3C 3C Digital IC Slide 35
34 3-input NND Caps nnotate the 3-input NND gate with gate and diffusion capacitance. 5C 5C 5C C 3C 3C Digital IC Slide 36
35 Example: -input NND Estimate worst-case rising and falling delay of - input NND driving h identical gates. x Y h copies Digital IC Slide 37
36 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies Digital IC Slide 38
37 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R Y (6+4h)C tpdr Digital IC Slide 39
38 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R Y (6+4h)C t pdr ln (6 4h) RC Digital IC Slide 40
39 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies Digital IC Slide 41
40 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C tpdf Digital IC Slide 4
41 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C t pdf R ln C ln (7 4h) RC [(6 R 4h) C ]( R ) Digital IC Slide 43
42 Delay Components Delay has two parts Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance Digital IC Slide 44
43 Contamination Delay est-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously x 6C C Y 4hC R R Y (6+4h)C tcdr 3 h RC Digital IC Slide 45
44 Layout Comparison Which layout is better? V DD V DD Y Y GND GND Digital IC Slide 46
45 Diffusion Capacitance assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NND3 layout shares one diffusion contact Reduces output capacitance by C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion C C Isolated Contacted Diffusion 3 3 7C 3C 3C 3C 3C 3 3C Digital IC Slide 47
46 Transistor Sizing R p R p 4 R p R n C L 4 R p C int R n Cint 1 R n R n 1 C L Digital IC 48
47 Transistor Sizing a Complex CMOS Gate 4 3 C D 4 6 OUT = D + ( + C) D 1 C Digital IC 49
48 Fan-In Considerations C D C D C 3 C C 1 C L Distributed RC model (Elmore delay) t phl = 0.69 R eqn (C 1 +C +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in quadratically in the worst case Digital IC 50
49 t p (psec) t p (NND)as a function of fan-in quadratic t phl t p 50 0 t pl H linear fan-in Gates with a fan-in greater than 4 should be avoided Digital IC 51
50 t p (psec) t p as a function of fan-out t p NOR t p NND ll gates have the same drive current t p INV Slope is a function of driving strength eff. fan-out Digital IC 5
51 t p as a function of fan-in and fan-out Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to C L t p = a 1 F I + a F I + a 3 F O Digital IC 53
52 Voltage [V] Delay Dependence on Input Patterns 共享电容放电 ==1 0 =1 0, =1 =1, =1 0 Input Data Pattern Delay (psec) ==0 1 69(max) =1, =0 1 6 = 0 1, =1 50 ==1 0 35(min) =1, = time [ps] 共享电容充电 = 1 0, =1 57 NMOS = 0.5 m/0.5 m PMOS = 0.75 m/0.5 m C L = 100 ff Digital IC 54
53 Static CMOS logic CMOS static characteristic CMOS propagate delay Large fan-in technology Logic effort CMOS power analysis Digital IC 55
54 How to choose design techniques for large fan-in Larger parasitic capacitor, larger load to the preceding gate Load is dominated by fan-out, the design technique makes sense Solution Progressive transistor sizing Transistor ordering lternative logic structures Isolating fan-in from fan-out using buffer insertion Digital IC 56
55 Transistor ordering critical path critical path In 3 1 In 1 In M3 C L M3 In 1 M C charged M C In M1 charged 3 1 M1 C 1 C 1 charged 0 1 In 1 charged C L discharged discharged delay determined by time to discharge C L, C 1 and C delay determined by time to discharge C L Digital IC 57
56 Progressive sizing Distributed RC line M1 > M > M3 > > MN the closest to the output is the smallest Can reduce delay by more than 0%; decreasing gains as technology shrinks Digital IC 58
57 lternative logic structures F = CDEFGH Digital IC 59
58 Isolating fan-in from fan-out using buffer insertion Large fan-in Large fan-out isolating C L C L Digital IC 60
Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit
More information5. CMOS Gates: DC and Transient Behavior
5. CMOS Gates: DC and Transient Behavior Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 September 18, 2017 ECE Department, University
More informationDigital Microelectronic Circuits ( ) CMOS Digital Logic. Lecture 6: Presented by: Adam Teman
Digital Microelectronic Circuits (361-1-3021 ) Presented by: Adam Teman Lecture 6: CMOS Digital Logic 1 Last Lectures The CMOS Inverter CMOS Capacitance Driving a Load 2 This Lecture Now that we know all
More informationEEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families
EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Homework 5 this week Lab
More informationCombinational Logic Gates in CMOS
Combinational Logic Gates in CMOS References: dapted from: Digital Integrated Circuits: Design Perspective, J. Rabaey UC Principles of CMOS VLSI Design: Systems Perspective, 2nd Ed., N. H. E. Weste and
More informationVLSI Design. Static CMOS Logic
VLSI esign Static MOS Logic [dapted from Rabaey s igital Integrated ircuits, 2002, J. Rabaey et al.] EE4121 Static MOS Logic.1 ZLM Review: MOS Process at a Glance efine active areas Etch and fill trenches
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Ratioed Logic Introduction Digital IC EE141 2 Ratioed Logic design Basic concept Resistive load Depletion
More informationLecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1
Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation
More informationEE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits
EE 330 Lecture 43 Digital Circuits Other Logic Styles Dynamic Logic Circuits Review from Last Time Elmore Delay Calculations W M 5 V OUT x 20C RE V IN 0 L R L 1 L R R 6 W 1 C C 3 D R t 1 R R t 2 R R t
More informationModule 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits
Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits Objectives In this lecture you will learn the following Ratioed Logic Pass Transistor Logic Dynamic Logic Circuits
More informationWritten Examination on. Wednesday October 17, 2007,
Written Examination on Wednesday October 17, 2007, 08.00-12.00 The textbook and a calculator are allowed on the examination 1. The following logical function is given Q= AB( CD+ CE) + F a. Draw the schematic
More informationEE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits
EE 330 Lecture 43 Digital Circuits Other Logic Styles Dynamic Logic Circuits Review from Last Time Elmore Delay Calculations W M 5 V OUT x 20C RE V IN 0 L R L 1 L R RW 6 W 1 C C 3 D R t 1 R R t 2 R R t
More informationIntegrated Circuits & Systems
Federal University of Santa atarina enter for Technology omputer Science & Electronics Engineering Integrated ircuits & Systems INE 5442 Lecture 16 MOS ombinational ircuits - 2 guntzel@inf.ufsc.br Pass
More informationPractice 6: CMOS Digital Logic
Practice 6: CMOS Digital Logic Digital Electronic Circuits Semester A 2012 The MOSFET as a Switch The MOSFET as a Switch We can look at the MOSFET as a Switch, passing the data between the diffusions when
More informationLecture 4. The CMOS Inverter. DC Transfer Curve: Load line. DC Operation: Voltage Transfer Characteristic. Noise in Digital Integrated Circuits
Noise in Digital Integrated Circuits Lecture 4 The CMOS Inverter i(t) v(t) V DD Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail:
More informationDigital Microelectronic Circuits ( ) Pass Transistor Logic. Lecture 9: Presented by: Adam Teman
Digital Microelectronic Circuits (361-1-3021 ) Presented by: Adam Teman Lecture 9: Pass Transistor Logic 1 Motivation In the previous lectures, we learned about Standard CMOS Digital Logic design. CMOS
More informationCPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look
CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic CMOS Inverter: A First Look C L 9/11/26 VLSI
More informationTopic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection
NMOS Transistors in Series/Parallel Connection Topic 6 CMOS Static & Dynamic Logic Gates Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Transistors can be thought
More informationI. Digital Integrated Circuits - Logic Concepts
I. Digital Integrated Circuits - Logic Concepts. Logic Fundamentals: binary mathematics: only operate on and (oolean algebra) simplest function -- inversion = symbol for the inverter INPUT OUTPUT EECS
More informationECE 471/571 The CMOS Inverter Lecture-6. Gurjeet Singh
ECE 471/571 The CMOS Inverter Lecture-6 Gurjeet Singh NMOS-to-PMOS ratio,pmos are made β times larger than NMOS Sizing Inverters for Performance Conclusions: Intrinsic delay tp0 is independent of sizing
More informationCPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4
CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals
More informationELEC451 Integrated Circuit Engineering Fall 2009 Solution to CAD Assignment 2 Inverter Voltage Transfer Characteristic (VTC)
ELEC451 Integrated Circuit Engineering Fall 2009 Solution to CAD Assignment 2 Inverter Voltage Transfer Characteristic (VTC) The plot below shows how the inverter's threshold voltage changes with the relative
More informationEE434 ASIC & Digital Systems
EE434 ASIC & Digital Systems Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Spring 2015 Dae Hyun Kim daehyun@eecs.wsu.edu 1 Lecture 4 More on CMOS Gates Ref: Textbook chapter
More informationEE241 - Spring 2002 Advanced Digital Integrated Circuits
EE241 - Spring 2002 dvanced Digital Integrated Circuits Lecture 7 MOS Logic Styles nnouncements Homework #1 due 2/19 1 Reading Chapter 7 in the text by K. ernstein ackground material from Rabaey References»
More informationEMT 251 Introduction to IC Design. Combinational Logic Design Part IV (Design Considerations)
EMT 251 Introduction to IC Design (Pengantar Rekabentuk Litar Terkamir) Semester II 2011/2012 Combinational Logic Design Part IV (Design Considerations) Review : CMOS Inverter V DD tphl = f(rn, CL) V out
More informationECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits
Faculty of Engineering ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits CMOS Technology Complementary MOS, or CMOS, needs both PMOS and NMOS FET devices for their logic gates to be realized
More informationECE520 VLSI Design. Lecture 11: Combinational Static Logic. Prof. Payman Zarkesh-Ha
EE520 VLSI esign Lecture 11: ombinational Static Logic Prof. Payman Zarkesh-Ha Office: EE ldg. 230 Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 eview of Last
More informationThe CMOS Inverter. Lecture 3a Static properties (VTC and noise margins)
The CMOS Inverter Lecture 3a Static properties (VTC and noise margins) Why so much about inverters? The current that any CMOS logic gate can deliver or sink can be calculated from equivalent inverter!
More informationCMOS Circuits CONCORDIA VLSI DESIGN LAB
CMOS Circuits 1 Combination and Sequential 2 Static Combinational Network CMOS Circuits Pull-up network-pmos Pull-down network-nmos Networks are complementary to each other When the circuit is dormant,
More informationChapter 6 DIFFERENT TYPES OF LOGIC GATES
Chapter 6 DIFFERENT TYPES OF LOGIC GATES Lesson 9 CMOS gates Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline CMOS (n-channel based MOSFETs based circuit) CMOS Features
More informationEE 330 Lecture 44. Digital Circuits. Other Logic Styles Dynamic Logic Circuits
EE 330 Lecture 44 Digital Circuits Other Logic Styles Dynamic Logic Circuits Course Evaluation Reminder - ll Electronic http://bit.ly/isustudentevals Review from Last Time Power Dissipation in Logic Circuits
More informationECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 5: Basic CMOS Inverter Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture
More informationLayout - Line of Diffusion. Where are we? Line of Diffusion in General. Line of Diffusion in General. Stick Diagrams. Line of Diffusion in General
Where are we? Lots of Layout issues Line of diffusion style Power pitch it-slice pitch Routing strategies Transistor sizing Wire sizing Layout - Line of Diffusion Very common layout method Start with a
More informationLecture 11 Circuits numériques (I) L'inverseur
Lecture 11 Circuits numériques (I) L'inverseur Outline Introduction to digital circuits The inverter NMOS inverter with resistor pull-up 6.12 Spring 24 Lecture 11 1 1. Introduction to digital circuits:
More informationUNIT-III GATE LEVEL DESIGN
UNIT-III GATE LEVEL DESIGN LOGIC GATES AND OTHER COMPLEX GATES: Invert(nmos, cmos, Bicmos) NAND Gate(nmos, cmos, Bicmos) NOR Gate(nmos, cmos, Bicmos) The module (integrated circuit) is implemented in terms
More informationIn this experiment you will study the characteristics of a CMOS NAND gate.
Introduction Be sure to print a copy of Experiment #12 and bring it with you to lab. There will not be any experiment copies available in the lab. Also bring graph paper (cm cm is best). Purpose In this
More information3.CMOS Inverter-homework
3.CMOS Inverter-homework 1. for a CMOS inverter, when the pmos and nmos are long-channel devices,or when the supply voltage is low, velocity does not occur, under these circumstances,vm(vin=vout)=? 2.
More informationENG2410 Digital Design CMOS Technology. Fall 2017 S. Areibi School of Engineering University of Guelph
ENG2410 Digital Design CMOS Technology Fall 2017 S. reibi School of Engineering University of Guelph The Transistor Revolution First transistor Bell Labs, 1948 Bipolar logic 1960 s Intel 4004 processor
More informationLecture 11 Digital Circuits (I) THE INVERTER
Lecture 11 Digital Circuits (I) THE INVERTER Outline Introduction to digital circuits The inverter NMOS inverter with resistor pull-up Reading Assignment: Howe and Sodini; Chapter 5, Sections 5.1-5.3 6.12
More informationZero Steady State Current Power-on-Reset Circuit with Brown-Out Detector
Zero Steady State Current Power-on-Reset Circuit with Brown-Out Detector Sanjay Kumar Wadhwa 1, G.K. Siddhartha 2, Anand Gaurav 3 Freescale Semiconductor India Pvt. Ltd. 1 sanjay.wadhwa@freescale.com,
More informationCombinational Logic. Prof. MacDonald
Combinational Logic Prof. MacDonald 2 Input NOR depletion NFET load l Pull Down Network can pull OUT down if either or both inputs are above Vih consequently the NOR function. l Depletion NFET could really
More informationDigital Microelectronic Circuits ( ) Terminology and Design Metrics. Lecture 2: Presented by: Adam Teman
Digital Microelectronic Circuits (361-1-3021 ) Presented by: Adam Teman Lecture 2: Terminology and Design Metrics 1 Last Week Introduction» Moore s Law» History of Computers Circuit analysis review» Thevenin,
More informationEE 330 Lecture 42. Other Logic Styles Digital Building Blocks
EE 330 Lecture 42 Other Logic Styles Digital Building Blocks Logic Styles Static CMOS Complex Logic Gates Pass Transistor Logic (PTL) Pseudo NMOS Dynamic Logic Domino Zipper Static CMOS Widely used Attractive
More informationChapter 4. Problems. 1 Chapter 4 Problem Set
1 Chapter 4 Problem Set Chapter 4 Problems 1. [M, None, 4.x] Figure 0.1 shows a clock-distribution network. Each segment of the clock network (between the nodes) is 5 mm long, 3 µm wide, and is implemented
More informationDigital Electronics Part II - Circuits
Digital Electronics Part II - Circuits Dr. I. J. Wassell Gates from Transistors 1 Introduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits
More informationDigital Integrated CircuitDesign
Digital Integrated CircuitDesign Lecture 11 BiCMOS PMOS rray Q1 NMOS rray Y NMOS rray Q2 dib brishamifar EE Department IUST Contents Introduction BiCMOS Devices BiCMOS Inverters BiCMOS Gates BiCMOS Drivers
More informationPreface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate
Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation
More informationEE241 - Spring 2006 Advanced Digital Integrated Circuits. Notes. Lecture 7: Logic Families for Performance
EE241 - Spring 2006 dvanced Digital Integrated Circuits Lecture 7: Logic Families for Performance Notes Hw 1 due tomorrow Feedback on projects will be sent out by the end of the weekend Some thoughts on
More informationEE 330 Lecture 5. Basic Logic Circuits Complete Logic Family Other Logic Styles. Improved Device Models. complex logic gates pass transistor logic
EE 330 Lecture 5 asic Logic Circuits Complete Logic Family Other Logic Styles complex logic gates pass transistor logic Improved Device Models Review from Last Time The key patents that revolutionized
More informationPower-Area trade-off for Different CMOS Design Technologies
Power-Area trade-off for Different CMOS Design Technologies Priyadarshini.V Department of ECE Sri Vishnu Engineering College for Women, Bhimavaram dpriya69@gmail.com Prof.G.R.L.V.N.Srinivasa Raju Head
More informationd. Can you find intrinsic gain more easily by examining the equation for current? Explain.
EECS140 Final Spring 2017 Name SID 1. [8] In a vacuum tube, the plate (or anode) current is a function of the plate voltage (output) and the grid voltage (input). I P = k(v P + µv G ) 3/2 where µ is a
More informationCHAPTER 3 PERFORMANCE OF A TWO INPUT NAND GATE USING SUBTHRESHOLD LEAKAGE CONTROL TECHNIQUES
CHAPTER 3 PERFORMANCE OF A TWO INPUT NAND GATE USING SUBTHRESHOLD LEAKAGE CONTROL TECHNIQUES 41 In this chapter, performance characteristics of a two input NAND gate using existing subthreshold leakage
More informationPHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag
PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Integrated Circuit Layers MOSFETs CMOS Layers Designing FET Arrays EE 432 VLSI Modeling and Design 2 Integrated Circuit Layers
More informationSynthesis of Combinational Logic
Synthesis of ombinational Logic 6.4 Gates F = xor Handouts: Lecture Slides, PS3, Lab2 6.4 - Spring 2 2/2/ L5 Logic Synthesis Review: K-map Minimization ) opy truth table into K-Map 2) Identify subcubes,
More informationReading. Lecture 17: MOS transistors digital. Context. Digital techniques:
Reading Lecture 17: MOS transistors digital Today we are going to look at the analog characteristics of simple digital devices, 5. 5.4 And following the midterm, we will cover PN diodes again in forward
More informationVLSI Logic Structures
VLSI Logic Structures Ratioed Logic Pass-Transistor Logic Dynamic CMOS Domino Logic Zipper CMOS Spring 25 John. Chandy inary Multiplication + x Multiplicand Multiplier Partial products Result Spring 25
More informationECE380 Digital Logic. Logic values as voltage levels
ECE380 Digital Logic Implementation Technology: NMOS and PMOS Transistors, CMOS logic gates Dr. D. J. Jackson Lecture 13-1 Logic values as voltage levels V ss is the minimum voltage that can exist in the
More information1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)
CSE 493/593 Test 2 Fall 2011 Solution 1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) Decreasing of W to make the gate slower,
More information2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)
1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic
More informationCMOS VLSI Design (A3425)
CMOS VLSI Design (A3425) Unit V Dynamic Logic Concept Circuits Contents Charge Leakage Charge Sharing The Dynamic RAM Cell Clocks and Synchronization Clocked-CMOS Clock Generation Circuits Communication
More informationChapter 2 Combinational Circuits
Chapter 2 Combinational Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 23, 26 Why CMOS? Most logic design today is done on CMOS circuits
More informationELEC Digital Logic Circuits Fall 2015 Delay and Power
ELEC - Digital Logic Circuits Fall 5 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal
More informationCMOS VLSI Design (A3425)
CMOS VLSI Design (A3425) Unit III Static Logic Gates Introduction A static logic gate is one that has a well defined output once the inputs are stabilized and the switching transients have decayed away.
More informationEE 330 Lecture 5. Basic Logic Circuits Complete Logic Family Other Logic Styles. complex logic gates
EE 330 Lecture 5 asic Logic Circuits Complete Logic Family Other Logic Styles complex logic gates Review from Last Time The key patents that revolutionized the electronics field: Jack Kilby (34 years old
More informationDigital Integrated CircuitDesign
Digital Integrated CircuitDesign Lecture 9 MOS Logic and Gate Circuits B B Y Wired OR dib brishamifar EE Department IUST Contents Introduction NMOS Logic Resistive Load Saturated Enhancement Load Linear
More informationEECS 141: FALL 98 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh9:30-11am ee141@eecs EECS 141: FALL 98 FINAL For all problems, you
More informationElectronics Basic CMOS digital circuits
Electronics Basic CMOS digital circuits Prof. Márta Rencz, Gábor Takács, Dr. György Bognár, Dr. Péter G. Szabó BME DED October 21, 2014 1 / 30 Introduction The topics covered today: The inverter: the simplest
More informationDesigning Information Devices and Systems II Fall 2017 Note 1
EECS 16B Designing Information Devices and Systems II Fall 2017 Note 1 1 Digital Information Processing Electrical circuits manipulate voltages (V ) and currents (I) in order to: 1. Process information
More informationSwitching (AC) Characteristics of MOS Inverters. Prof. MacDonald
Switching (AC) Characteristics of MOS Inverters Prof. MacDonald 1 MOS Inverters l Performance is inversely proportional to delay l Delay is time to raise (lower) voltage at nodes node voltage is changed
More informationMicroelectronics, BSc course
Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT
More informationCHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS
70 CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS A novel approach of full adder and multipliers circuits using Complementary Pass Transistor
More informationEE141-Spring 2007 Digital Integrated Circuits
EE141-Spring 2007 Digital Integrated Circuits Lecture 22 I/O, Power Distribution dders 1 nnouncements Homework 9 has been posted Due Tu. pr. 24, 5pm Project Phase 4 (Final) Report due Mo. pr. 30, noon
More informationMicroelectronics, BSc course
Microelectronics, BSc course MOS inverters http://www.eet.bme.hu/~poppe/miel/en/13-mosfet2.pptx http://www.eet.bme.hu Overview of MSOFET types 13-11-2014 Microelectronics BSc course, MOS inverters András
More informationLecture 13 - Digital Circuits (II) MOS Inverter Circuits. October 25, 2005
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-1 Lecture 13 - Digital Circuits (II) MOS Inverter Circuits October 25, 25 Contents: 1. NMOS inverter with resistor pull-up (cont.) 2. NMOS
More informationECE 471/571 Combinatorial Circuits Lecture-7. Gurjeet Singh
ECE 471/571 Combinatorial Circuits Lecture-7 Gurjeet Singh Propagation Delay of CMOS Gates Propagation delay of Four input NAND Gate Disadvantages of Complementary CMOS Design Increase in complexity Larger
More informationECE/CoE 0132: FETs and Gates
ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will
More informationCMOS Transistor and Circuits. Jan 2015 CMOS Transistor 1
CMOS Transistor and Circuits Jan 2015 CMOS Transistor 1 Latchup in CMOS Circuits Jan 2015 CMOS Transistor 2 Parasitic bipolar transistors are formed by substrate and source / drain devices Latchup occurs
More informationEEC 118 Lecture #12: Dynamic Logic
EEC 118 Lecture #12: Dynamic Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Today: Alternative MOS Logic Styles Dynamic MOS Logic Circuits: Rabaey
More informationCHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC
138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit
More informationInterconnect. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
Interconnect Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Introduction Chips are mostly made of wires called
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php
More information! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! Standard Cells. ! CMOS Process Enhancements
EE 570: igital Integrated Circuits and VLI Fundamentals Lec 3: January 18, 2018 MO Fabrication pt. 2: esign Rules and Layout Lecture Outline! MO evice Layout! Inverter Layout! Gate Layout and tick iagrams!
More informationC H A P T E R 5. Amplifier Design
C H A P T E 5 Amplifier Design The Common-Source Amplifier v 0 = r ( g mvgs )( D 0 ) A v0 = g m r ( D 0 ) Performing the analysis directly on the circuit diagram with the MOSFET model used implicitly.
More informationLecture 13: Interconnects in CMOS Technology
Lecture 13: Interconnects in CMOS Technology Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 10/18/18 VLSI-1 Class Notes Introduction Chips are mostly made of wires
More informationBASIC PHYSICAL DESIGN AN OVERVIEW The VLSI design flow for any IC design is as follows
Unit 3 BASIC PHYSICAL DESIGN AN OVERVIEW The VLSI design flow for any IC design is as follows 1.Specification (problem definition) 2.Schematic(gate level design) (equivalence check) 3.Layout (equivalence
More informationECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
More information! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!
More informationECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics
ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.
More information2-Bit Magnitude Comparator Design Using Different Logic Styles
International Journal of Engineering Science Invention ISSN (Online): 2319 6734, ISSN (Print): 2319 6726 Volume 2 Issue 1 ǁ January. 2013 ǁ PP.13-24 2-Bit Magnitude Comparator Design Using Different Logic
More informationPower dissipation in CMOS
DC Current in For V IN < V TN, N O is cut off and I DD = 0. For V TN < V IN < V DD /2, N O is saturated. For V DD /2 < V IN < V DD +V TP, P O is saturated. For V IN > V DD + V TP, P O is cut off and I
More informationJack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Previously: Two XOR Gates. Pass Transistor Logic. Cascaded Pass Gates
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lecture Outline! Pass Transistor Logic! Performance Lec 15: March 2, 2017 Combination Logic: Pass Transistor Logic, and Performance 2 Previously:
More informationUltra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology
Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology Kyung Ki Kim a) and Yong-Bin Kim b) Department of Electrical and Computer Engineering, Northeastern University, Boston, MA
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Teaser. Pass Transistor Logic. Identify Function.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lecture Outline! Pass Transistor Logic! Performance Lec 15: March 1, 2018 Combination Logic: Pass Transistor Logic, and Performance 2 Pass Transistor
More informationEE 330 Lecture 44. Digital Circuits. Ring Oscillators Sequential Logic Array Logic Memory Arrays. Final: Tuesday May 2 7:30-9:30
EE 330 Lecture 44 igital Circuits Ring Oscillators Sequential Logic Array Logic Memory Arrays Final: Tuesday May 2 7:30-9:30 Review from Last Time ynamic Logic Basic ynamic Logic Gate V F A n PN Any of
More informationENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits
ENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits In this lab, we will be looking at ac signals with MOSFET circuits and digital electronics. The experiments will be performed
More informationSwitching threshold. Switch delay model. Input pattern effects on delay
Switching threshold Low Power VLSI System Design Lecture 8 & 9: Transistor Sizing and Low Power Memory Design Prof. R. Iris ahar October & 4, 017 Define V M to be the oint where V in = V out (both PMOS
More informationBasic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair,
Basic Circuits Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, CCS - Basic Circuits P. Fischer, ZITI, Uni Heidelberg, Seite 1 Reminder: Effect of Transistor Sizes Very crude classification:
More informationAnalysis of Different Topologies of Inverter in 0.18µm CMOS Technology and its Comparision
Analysis of Different Topologies of Inverter in 0.18µm CMOS Technology and its Comparision Ashish Panchal (Senior Lecturer) Electronics & Instrumentation Engg. Department, Shri G.S.Institute of Technology
More informationChapter 6 DIFFERENT TYPES OF LOGIC GATES
Chapter 6 DIFFERENT TYPES OF LOGIC GATES Lesson 8 NMOS gates Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline NMOS (n-channel based MOSFETs based circuit) NMOS Features
More information