write-nanocircuits Direct-write Jaebum Joo and Joseph M. Jacobson Molecular Machines, Media Lab Massachusetts Institute of Technology, Cambridge, MA

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1 Fab-in in-a-box: Direct-write write-nanocircuits Jaebum Joo and Joseph M. Jacobson Massachusetts Institute of Technology, Cambridge, MA April 17, 2008 Avogadro Scale Computing / 1

2 Avogadro number s? Intel produces ~1200 wafers/day (Each wafer contains ~10 11 s) s / yr Entire world may be able to fabricate ~10 18 s /yr << Moore s 2 nd law Chip density doubles, cost to set up manufacturing doubles. Difficult challenges: 1. How to increase the fabrication speed? 2. How to increase the complexity/cost? What is the method to approach this Avogadro limit in fabrication? / 2

3 Complexity comparison (Biology vs. current Fab) Simple molecules <1nm DNA proteins nm red blood cell ~5 μm (SEM) diatom 30 μm bacteria 1 μm m SOI width 0.12μm Semiconductor Nanocrystal ~1 nm Nanotube, nanowire Transistor (Dekker) Circuit design Copper wiring width 0.1μm IBM PowerPC 750 TM Microprocessor 7.56mm 8.799mm s / 3

4 DNA Synthesis Chemical Synthesis (Solid Phase Synthesis) Biological Synthesis (Error Correcting Polymerase) Error Rate: 1: Seconds Per step Error Rate: 1: Steps per second 3'-5' proofreading exonuclease Beese et al. (1993), Science, 260, / 4

5 Threshold Theorem ε ε 3ε 2 ε 3(3ε 2 ) 2 = 1/3(3ε) n 1/3(3ε) 2n / 5

6 Conventional Fabrication (Optical Lithography) - No error correction in individual basis (> 40 mask steps) - Complexity: Numerical aperture limits the structure size and density / 6

7 Fab-in in-a-box: Direct Write Nanocircuits - Error correction at each level - Complexity: nanometer scale (above the conventional fab) / 7

8 What are the methods? Electron Beam lithography Dip-Pen Nanolithography Self Assembly Nanoimprint lithography Focused Ion Beam Direct imaging possible in each level Error correction And others.. / 8

9 Focused Ion Beam () functions 1. Milling materials from a local area (~several nm) 2. Deposition of materials including Pt, SiO 2,etc. General Applications 1. Device modification ( mask, pad, etc.) 2. TEM sample preparation 3. Section analysis 4. Direct write / 9

10 Prototype of error correction fabrication by Extreme errors by random arrangement of nanowires Transistor fabrication by error correction tool / 10

11 Schematic of direct write Nanocircuits Randomly distributed semi-conducting Nanowire CVD Pt (source & drain) CVD SiO 2 (gate oxide) FET electrical Characterization Large scale integration CVD Pt (gate electrode) / 11

12 Detail: Nanowire Synthesis Gas phase Nanowire synthesis: Vapor-Liquid-Solid Mechanism (Si, GaN, etc.) Liquid phase Nanowire synthesis: Supersaturation & heterogeneous growth (ZnO, Cd(OH) 2, ZnS, etc.) / 12

13 Detail: Nanowire FET fabrication Au contact pad Selected Si nanowire Si nanowire / 13

14 Detail: Nanowire FET fabrication CVD Gate oxide Si nanowire SiO 2 / 14

15 Detail: Nanowire FET fabrication Gate Source S Source Electrode Drain mismatch errors Si corrected!!! NW Pt CVD Pt wiring to each electrode Pt SiO 2 G D Pt 6.0x Vg 0 Vg 2 Vg Gate electrode 5.0x x10-7 Drain electrode 3.0x10-7 Id 2.0x x Vd Depletion mode GaN FET / 15

16 How to increase the speed of the fabrication? Ion beam deposition < 20 nm Resolution Novel 3 Dimensional Computer Architectures Devices in << 24 hrs Parallel beam Prototype circuit fabrication with error correction Parallel Error Correcting Feedback Fabrication / 16

17 Parallel Focused Ion Beam () Micro column array Parallel ion beams Magnetic lens Scan coil Gas source, or cluster source Unique Features Ultrafast Highly Parallel Direct Fabrication On-The-Fly Molecular Scale Error Correction nm Inorganic Semiconductor Building Blocks substrate Gas beam Schematic of Moleographic Systems Showing Multiple Beam Fabrication with Feedback / 17

18 Other fabrication methods 2D Whole device fabrication by 1D assisted random nanowire circuit 1D assisted DNA tile circuit 0D assisted Nanowire synthesis and circuit fab Pre process None VLS, solution nanowire synthesis DNA tile synthesis None process Whole parts (Metal, Oxide, SC) volume (um^3) / time(s)/ time(s) /10^14 Cost($)/ Cost($) /400million s Cost($)/ Avogadro number s 9.01E E E E E E+15 Interconnect oxides 1.50E E E E E E+15 Interconnect 1.50E E E E E E+15 Catalysts (metal) 1.25E E E E E E+12 Assumption: 1. One 1000 x 1000 multiple beam 2. Design: simple MOSFET with 50nm gate / 18

19 1. Whole device fabrication by (2D) CVD parts metal (source, drain, gate electrode) oxide (gate) Semiconductor (functioning part) directly patterning organometallic nanoparticles Wilhelm et al., 2004 Requirement and issues time(s)/ time(s) /10^14 Cost($)/ Cost($)/ Avogadro number s 5.41E E E E All metal CVD should be done in chamber 2. As number increases, time for fabrication increase linearly 3. Too slow process / 19

20 2. assisted nanowire circuit (1D) CVD parts metal (electrode wiring) oxide (gate) Parallel nanowire growth and random distribution of nanowires Requirement and issues time(s)/ time(s) /10^14 Cost($)/ Cost($)/ Avogadro number s 9.00E E E E Once distributed nanowires are imaged, computer generates the mapping of each individual FET and fabricate multiple s / 20

21 3. assisted DNA tile circuit (1D) CVD parts Metal wiring (to metal electrode) Folding DNA to create nanoscale shapes and patterns Paul Rothemund, Nature 2006 time(s)/ time(s) /10^14 Cost($)/ Cost($)/ Avogadro number s 9.00E E E E+15 Requirement and issues 1. Would be preferable if DNA molecules are selectively assembled at desired location. (functionalization of surface, or stamping) / 21

22 4. assisted Nanowire synthesis and circuit fab (0D) CVD parts metal catalyst Oxide can be formed by heat treatment Kimin et al., unpublished time(s)/ time(s) /10^14 Cost($)/ Cost($)/ Avogadro number s 7.50E E E E+12 Requirement and issues 1. Planar nanowire synthesis required 2. Nanowire synthesis system should be compatible with Beam optics / 22

23 4. assisted Nanowire synthesis and circuit fab (0D) Catalyst deposition Parallel VLS nanowire growth in Fab-in-a-Box Other catalyst deposition Parallel VLS Nanowire growth Overall circuit Oxide by heat treatment, and catalyst driven nanowire wiring Large scale integration / 23

24 Evaluation of methods 2D Whole device fabrication by 1D assisted Random nanowire circuit 1D assisted DNA tile circuit 0D assisted Nanowire synthesis and circuit fabrication Pre process None VLS, solution nanowire synthesis DNA tile synthesis None process Whole parts (Metal, Oxide, SC) volume (um^3) / time(s)/ time(s) /10 14 Cost($)/ Cost($) /400million s Cost($)/ Avogadro number s 9.01E E E E E E+15 Interconnect oxides 1.50E E E E E E+15 Interconnect 1.50E E E E E E+15 Catalysts (metal) 1.25E E E E E E+12 ~20.8 hrs using single multiple with error correction Assumption: 1. One 1000 x 1000 multiple beam 2. Design: simple MOSFET with 50nm gate Complexity within 24hr with high precision (brain: ~10 11 neurons,~10 14 synapses) / 24

25 Error correction, and what else for the future Fab? Another aspect of biology Self replicating fabrication Small scale machines Scaling down the structure by making small scale three dimensional machines that can manipulate smaller scale objects. / 25

26 Conclusion Prototype Fab-in-a-Box Direct write nanowire circuit has been demonstrated with error correcting fabrication process. S mismatch errors Si corrected!!! NW G D We are currently working on more complex circuit to boolean CA level. Wire Cell Inverter Cell Wire Cell 0 Wire A0 B0 0 Wire MA0 CA0 MC0 CC0 MB0 CB0? 1 Wire A1 A0 A1 -V0 V0 B0 B1 B1 1 Wire MA1 CA1 MC1 CC1 MB1 CB1 A0 B0 A1 B1 -V0 V0 Any questions? / 26