Selected Topics in Nanoelectronics. Danny Porath 2002
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1 Selected Topics in Nanoelectronics Danny Porath 2002
2 Links to NST
3 Based on Works of. 1. Cees Dekker Delft 2. Jim Heath - UCLA 3. Jim Hutchbi - SRC 4. Yosi Shacam TAU 5. Joshua Jortner TAU 6. K. Likharev SUSB 7. Lectures at UCSB site 8. Scientific American September 2001
4 Outline: 1. Introduction 2. Devices 3. Nanoelectronics Carbon Nanotubes
5 Homework Read the paper: The incredible shrinking circuit, By: C.M. Lieber Scientific American, September 2001 pp Read the paper: Little Big Science, By: G. Stix Scientific American, September 2001 pp Read the paper: Nano Nonsense and Cryonics, By: M. Shermer Scientific American, September 2001 pp. 29.
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7 Motivation 1. Technological ability 2. Moore s law (micro)electronics miniaturization 3. Paradigm shift from top down to bottom up approach (or combined) 4. High manufacturing costs
8 Impact
9 Current and Future Directions 1. Wires 2. Switches 3. Memories 4. Computing 5. Molecular synthesis 6. Networks 7. SAM 8.
10 Some of the Open Questions and Issues Electrical properties and conduction mechanisms of molecules, wires and various nanostructures Synthesis of Complex structures Complex assembly of networks New materials (including defect free ) New principles of operation Systems of a chip Heat dissipation Speed of computing (qubits, DNA) New Architectures and logics
11 First Transistor and First Integrated Circuit Bardeen, Shockley and Brattain invented the transistor in This transistor was a point-contact transistor made out of Germanium. The idea of an integrated circuit was conceived at the same time by kilby of Texas Instruments and Noyce of Fairchild semiconductor.
12 Lithography-Based Device
13 Current Intel 130 nm Technology CMOS transistor MOS transistor Gate and metal 1 connections 60 nm gate length transistor
14 Pitch, Thickness and Aspect Ratio Pitch 1200 nm Pitch 350 nm
15 The Amount of Memory in a cm 2 Microelectronics: 0.18 µm technology: transistor diode Microelectronics: Cell size: 5.2x10-9 cm 2 ~200 million cells in 1 cm 2 Nanoelectronics: 10 nm technology Cell size: 1.6x10-11 cm billion cells in 1 cm 2
16 Dimensions Evolution Moore s Law
17 There are two ways to build a house... Top- down Bottom -up
18 The Top-down Approach
19 The Bottom-up Approach
20 ENIAC ENIAC, the first stored-program electronic computer, circa The computer, a small section of which is shown here, contained approximately 18,000 vacuum tubes and required 174 kilowatts of power to operate.
21 Teramac The Teramac experimental computer with one of its developers, Philip Kuekes. "Tera" denotes the fact that the machine performs one trillion gate operations per second (one million gates operating simultaneously at 1 megahertz); "mac" stands for "multiarchitecture computer." Teramac, built at HP Laboratories in 1995, contains over 220,000 known manufacturing defects, yet operates perfectly.
22 Von Neumann Architecture P performance P=knf n number of elements in the system F operation frequency Therefore: The larger the better The faster the better
23 Shrinking Rate in Si ULSI Transistor size by 0.7 every 3 years Integration quadrupled every 3 years The downscale limit of Si paradigm is foreseen at nm Nanoelectronics
24 However not so cheap!!! the cost of fabrication facilities (fabs) for manufacturing integrated circuits has been increasing by a factor of two every three years.
25 SIA Roadmap 1997 (Semiconductor Industry Association)
26 SIA Roadmap 1997 (Semiconductor Industry Association)
27 Observations for Si ULSI Devices The current semiconductor fabrication technology is now in the nanometer-controlled region. The nanotechnology should learn the current ULSI technology more but should not mimic it. The functional blocks in the nanoelectronics will be built up by using both the top-down and the bottom-up technologies complementarily and cooperatively. It will be important how to harmonize the functional blocks in the nanoelectronics with the current semiconductor devices. The application filed of nanoelectronics will be tremendously big in the ubiquitous IT society, as versatile human friendly hardware. Both R&D of top-down and bottom-up nanotechnologies will be needed to build up a big market and scientific field. The nanometer/sub-nanometer scale metrology is fundamentally useful for characterizing the ULSI technology standards.
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29 Comparison of Nanotransistor Technologies
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Progress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity in implementing functions.
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