A walk in the NanoPark - Practical Paths to Molecular Computers

Transcription

1 A walk in the NanoPark - Practical Paths to Molecular Computers Paul D. Franzon, with many others (acknowledged within, especially David Nackashi and Christian Amsink) North Carolina State University Department of Electrical and Computer Engineering paul_franzon@ncsu.edu

2 Outline > The End Of The Silicon Roadmap > The Nanotechnology Promise > Molecular Circuit Elements > The Challenges Integration Signal Integrity > Integration Alternatives The Tour-Reed Nanocell The NRL Cow Pea virus > Circuit Design for Robustness Tour-Reed molecules as circuit elements Closing the model loop Circuit Design Examples > Looking Forward 2

3 The End of the Silicon Roadmap > The 35nm Technology Node Around 2014, we are expected to reach the 35nm Technology Node Gate oxide tunnelling limit This Technology Node includes 20-22nm transistor gate lengths Current state-of-the-art fabrication facility costs are approaching $2 billion per plant! From the 1999 International Technology Roadmap for Semiconductors: with the 1999 edition, we are reaching the point where the horizon of the Roadmap approximately coincides with the most optimistic projections for continued scaling of CMOS (for example, MOSFET channel lengths of 20nm). Sources : ITRS, Proc. IEEE 3/2001 3

4 The Nanotechnology Promise A set of patterning and characterization technologies on the nanometer scale 1. Chemical Synthesis OMe NC SAc X AcS OMe NC AcS Relatively Easy Y SAc AcS NC OMe NC OMe Courtesy of J. C. Ellenbogen SAc Difficult 4

5 Nanotechnologies (2) 2. Nano-structured biological Materials Viruses, DNA, etc. 31 nm 314 Å Cow Pea Mosaic Virus Courtesy : Shashidar and Ratner, NRL 5

6 Nanotechnologies (3) 3. Random and directed self-assembly Gold nanoparticles randomly assembled on oxide surface Selective attachment based on chemistry Chemical crystals 6

7 Nanotechnologies (4) 4. Inorganic nanostructures CD = 100 nm Pitch = 360 nm From: Sone et.al., Nanofabrication toward sub-10nmand its application to novel nanodevices, Nanotechnology v10 (1999). From: Chen et.al., Two-dimensional arrangement of octadecylaminefunctionalized gold nanoparticles using the LB technique, Nanotechnology v11 (2000). 7

8 Nanotechnologies (5) 5. Carbon Nanotubes Possibility as nano interconnect 6. AFM and STM characterization Courtesy of Schönenberger and Forró Å Å Å Å Å Å Å Å Courtesy of Paul Weiss Courtesy of Shashidar and Ratner 8

9 Molecular Circuit Elements > Two Terminal Devices Rectifying diodes Diodes exhibiting Negative Differential Resistance (NDR) Wires Resistors Settable / Re-settable Devices > Three terminal devices Chemical synthesis possible Electrical testing is quite difficult Courtesy of Veena Misra 9

10 Mol Devices > Origins: Basic molecular device & self-assembly concepts (US ( 95), US ( 96)) Single molecule transport ( 96) First molecular devices ( 97) 1997 Courtesy : Mark Reed 1.2n 800.0p I (A) 400.0p 0.0 Summer 1999 J = 53 A/cm 2 NDR = -380 µω-cm 2 T= 60 K J ~ 50 A/cm 2 NDR ~ -380 µω-cm 2 I peak = 1.03 na V Current (A) Fall 1n p 500p 250p I valley = 1 pa Temperature RT Voltage (V) 10

11 Planar devices, ambient NDR & memory Current (A) 800.0µ 600.0µ 400.0µ 200.0µ µ µ Winter 2000 Current (A) 800.0µ first trace T = 300K 700.0µ second trace 600.0µ 500.0µ 400.0µ 300.0µ 200.0µ 100.0µ µ Voltage (V) µ Voltage (V) Courtesy : Mark Reed 11

12 Principles of Operation > n-channel vs. p-channel Most organics tend to be p-channel devices It tends to be easier to oxidize organic molecules than to reduce them C 60 is an exception and can be easily reduced, therefore functioning as an n-channel device > Metal terminal attachment Proper matching of work functions is critical when choosing an attachment chemistry The common thiol-gold attachment has been shown to be quite resistive > Matching of Fermi and Homo/Lumo levels 12

13 The Challenges > Have some switches but also need > Integration Technology Orderable Interconnect To create custom logic To create regular arrays (memory) Low-resistance interconnect > Robustness Signal Integrity Restoring Logic Circuit Structures Input/Output Isolation Parasitic Control 13

14 Integration-Scale Issues > Must avoid Using regular lithography Using MOSFET gates Chip level Cell level 2.2nm X AcS SAc Y Gate width is 0.18µm (180nm) Small array (Only M1 and M2 shown) Single transistor Cluster of transistors (Only M1 and M2 shown) 14

15 Scale end of roadmap 22 nm 2.2 nm 120 nm 15

16 Not just wires > Ideal circuit Transistor = switch Wire = invisible O.1-10 Ω Gate O Ω (off) 500-5,000 Ω (on) > 1,000 : 1 Rdevice : Rwire ratio O.1-10 Ω 16

17 Robustness Signal Integrity > Explicit design and modeling so as to withstand Modeled noise sources Parametric variations CMOS +/- 20% Temperature -55 C to C > Introduction of design margin so as to withstand Unmodeled noise sources Unmodeled parametric variations 17

18 Robustness. Signal Integrity > Unlike Analog circuits, digital circuits reject noise Logic restoration

19 How Digital Ckts reject noise 1. Non-linear gain in the logic device Vin Vout Vout > Noise Margin provided Vin V IL V OL Noise Margin 20

20 How to achieve circuit gain. > Easiest to achieve with (non-linear) transistor gain: CMOS : Iout = g m Vin Bipolar : Iout = β Iin β, g m >> 1 Vin Iout Iin Iout > Can also achieve with Goto pairs (back to back NDRs) > Can also achieve with clocks and proper use of non-linear non-gain devices 21

21 How Digital Ckts reject noise? (2) > High Transimpedance and Impedance isolation Vin, Iin Z12 Vout, Iout > Desire Zin Z12 as high as possible Zin/Zout as high as possible Zout δvin Zin = δiin δvout Zout = δiout δvout Z12 = δiin 22

22 Why? Need to be able to connect gates together! > Unloaded Gate: > Loaded Gate: V OL V IL 0? 1?? V OL V IL 23

23 How? > In conventional circuits, associated with gain and isolation 1,000 Ω Iin=10µA Iin=10µA Vout is independent of Iin Vout=1 V Z12 = infinity! Z12=100,000 Ω 24

24 How? > With two terminal devices more difficult Rely on rectifying diodes I V I V Not the preferred choice 25

25 Other Robustness Issues > Power/ground integrity Device : Wire resistance ratio > 1,000 : 1 Interaction between stray inductance and non-linear devices can lead to oscillations > Device parametric variation Often +/- 20% in CMOS;?? in Nano > Parasitics Speed limited by Device Resistance * inter-device capacitance Capacitance vs. # of Neighbors 3.00E E E E E E E

26 Outline > The End Of The Silicon Roadmap > The Nanotechnology Promise > Molecular Circuit Elements > The Challenges Integration Signal Integrity > Integration Alternatives The Tour-Reed Nanocell The NRL Cow Pea virus > Circuit Design for Robustness Tour-Reed molecules as circuit elements Closing the model loop Circuit Design Examples > Looking Forward 27

27 VanZandt-Tour Tour-Reed Nanocell > Random self-assembly Input terminals Output terminals Self-assembling molecular switches (two types) Nanoparticle Work originated by B. Van Zandt, J.M. Tour, Rice University. Courtesy of David Allera and Philipp Harder, PSU 28

28 VanZandt-Tour Tour-Reed Nanocell Order from Disorder > Construction concept Randomly constructed > Program through exploration Program to achieve complex logic function Reprogram device states from edge Measure response at edge Program Measure Cycle 29

29 NRL Cowpea Mosaic Virus > CPMV functions as scaffold u attach metal balls to functionalized faces u assemble molecules between balls u work with symmetries forced by virus structure > Symmetric properties suggest memory structures 30

30 Outline > The End Of The Silicon Roadmap > The Nanotechnology Promise > Molecular Circuit Elements > The Challenges Integration Signal Integrity > Integration Alternatives The Tour-Reed Nanocell The NRL Cow Pea virus > Circuit Design for Robustness Tour-Reed molecules as circuit elements Closing the model loop Circuit Design Examples > Looking Forward 31

31 Role as Circuit Designer > The middleman Physical Architectures Circuit Topologies Logical Architectures Molecular Devices Au (2) (2) Spice Modeling NO2 S Au 32

32 NDR Device Model > I-V data points provided by Jia Chen / Mark Reed - Yale University > Model was created using a piecewise linear (PWL) function in HSPICE (G element) > Transient responses not included in this model 33

33 Device Characterization > Designed characterization structures specifically designed to support circuit design Single sample IV sweeps insufficient for full design > In fabrication now 34

34 Bistable Device Design Adapted from J.Huber et al., IEEE Trans. Electron. Devices 44, 2149 (1997) Strategy > Utilize the negative resistance to locate two stable points of operation > Results in Memory Element Design > Load the molecular diode with a voltage source and current-limiting resistor (R0, D0) 35

35 NAND Gate Design NAND truth table A B F I bridge Rectifying diode for isolation * I out > 2-Input Current-mode NAND gate > Gate is first reset to place the NDR diodes in the low impedance state At this state, I out is 500pA and I bridge is 0pA > If both input currents reach threshold, the output transitions from a low impedance state to a high impedance state At this state, I out is 1-2 pa > Output capacitance/resistance are used to simulate loading conditions * Circuit adapted from Chow, Principles of Tunnel Diode Circuits, (1964) Output Load Rectifying diode from C.Zhou, M.R.Deshpande, M.A.Reed, J.M.Tour, Nanoscale metal/self-assembled monolayer/metal heterostructures, Appl. Phys. Lett., vol.71,pp ,

36 NAND Gate Design > Gate is reset before each evaluation period > An input/output 1 is equivalent to a 500pA current > An input/output 0 is equivalent to a 1-2pA current > The gate evaluates the currents at both inputs. If both inputs are at or beyond threshold at any time, a transition is made to the low current state. > These waveforms were extracted through simulation without rectifying diodes 37

37 NOR Gate Design > Transition from high to low occurs abruptly at an input current of 300pA > Even as input current ramps up, the output current does not appreciatively increase > Helps to minimize noise from propagating through the gate 38

38 Memory Arrays Memory Cell > A memory cell is constructed from a bistable latch > State 0 : Low Voltage/ High Current > State 1 : High Voltage / Low Current > Data to be written is placed on horizontal write lines (W0, W1) > Data read is taken from the lower read lines (RD0,RD1) > Cells are written in multi-bit words using the vertical readwrite lines (RW0,RW1) Adapted from Chang, Parametric and Tunnel Diodes, (1964) 39

39 Memory Arrays > A reset signal is sent by lowering the RW line to 2.0V > A write signal is sent by raising the RW line to 2.6V > Data words to be written into memory are placed on the RW bus > The internal nodes of the bistable latch hold the values > Data is read by lowering the RW line to 2.2V and reading the RD bus 40

40 Circuits Discussion > Have simulated fan-out; oscillation-free > Tight margins < 5% Wiring resistance could easily dominate Unclear if these resistors are buildable > Difficult CMOS interface > Margins improved by Bistable devices (e.g DiNitro) Margin approaches Bistability Spread Increased current density (e.g. DiNitro) More device types with isolation E.g. Gain devices > C.f. CMOS end game : ~ 50 transistors/µm2 43

41 Memory Discussion > Silicon DRAM density Today : 8 bits / µm 2 >200 bits / µm 2 at end of road map > SRAM built using Cow Pea Virus >4,000 bits / µm 2 / layer > Integration Problem Requires interface wires at < 10 nm pitch 30 nm pitch wires still gives 1,000 bits / µm 2 Common problem across many proposed structures Nano Lithographic 44

42 Memory (2) > Signal Integrity Issues 0.1 V noise margin in structure above Improved to 1.6 V with bistable dinitro circuit > Scaling Limits Wiring resistance : device resistance On : off ratio for bistable devices Exploring ways around these limits > Memory Circuit Requirements ~60 fc charge per bit About 35,000 electronics 50 mv swing required for sensing 45

43 Looking Forward > My wish list Designable nano-interconnect technology that can pitch match to CMOS and have low resistance 3-terminal devices with gain and/or isolation Greater current densities Lower contact resistance Higher on-off ratios for bistable devices Better rectifiers Greater range to breakdown > Major issues Characterization Robust circuit design 46

44 Conclusions > Devices = Computers > Need to expand nanotechnology integration toolkit > Need to expand molecular switch capabilities > Need to develop robust circuit topologies > Aim beyond the end of the CMOS roadmap Peak Densitiesi: 2 x logic transistors / cm 2 81 x dram cells / cm 2 > Too many compromises in most of today s molecular computing proposals Lead to lower equivalent densities than above 47

45 Scaling Issues > Don t give ground easily As Fabricated >10 12 devices Defects Defect Tolerance Simple Architecture 10 9 No wires MHz