SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638 HIGH-SPEED DIFFERENTIAL LINE DRIVERS

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1 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 Meets or Exceeds the Requirements of ANSI TIA/EIA-44 Standard Low-Voltage Differential Signaling With Typical Output Voltage of 0 mv and a 00-Ω Load Typical Output Voltage Rise and Fall Times of 00 ps (400 Mbps) Typical Propagation Delay Times of. ns Operates From a Single.-V Supply Power Dissipation 2 mw Typical per Driver at 200 MHz Driver at High Impedance When Disabled or With V CC = 0 Bus-Terminal ESD Protection Exceeds kv Low-Voltage TTL (LVTTL) Logic Input Levels Pin-Compatible With the AM2LS, MC4, and µa9 description The SNLVDS, SNLVDS, SNLVDS4, and SNLVDS9 are differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow operation with a.-v supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 24 mv into a 00-Ω load when enabled. The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 00 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SNLVDS, SNLVDS4, and SNLVDS9 are characterized for operation from 40 C to C. The SNLVDS is characterized for operation from C to 2 C. Z NC 2Z 2Y SNLVDS... J OR W SNLVDSD (Marked as LVDS or LVDS) (TOP VIEW) A Y Z 2Z 2Y 2A ND 4 2 A Y Z,2EN 2Z 2Y 2A ND Y A NC V CC 4A V CC 4A 4Y 4Z Z Y A SNLVDS4D (Marked as LVDS4 or LVDS4) (TOP VIEW) V CC A 2A ND 9 0 2A SNLVDSFK (TOP VIEW) ND NC A Y 4 V CC 4A 4Y 4Z,4EN Z Y A SNLVDS9D (Marked as DK or LVDS) SNLVDS9DN (Marked as L) (TOP VIEW) Y Z 2Y 2Z 4Y 4Z NC Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2000, Texas Instruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS 2

2 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 TA SMALL OUTLINE (D) AVAILABLE OPTIONS PACKAE MSOP (DN) CHIP CARRIER (FK) CERAMIC DIP (J) FLAT PACK (W) SNLVDSD 40 C to C SNLVDS4D SNLVDS9D SNLVDS9DN C to 2 C SNLVDSFK SNLVDSJ SNLVDSW logic symbol LVDS logic diagram (positive logic) 4 2 SNLVDS, SNLVDS EN A Y Z A 2 Y Z 2A 2Y 2Z 2A A 4A Y 2Z Y Z 4Y 4Z A 4A Y Z 4Y 4Z This symbol is in accordance with ANSI/IEEE Std 9-94 and IEC Publication POST OFFICE BOX 0 DALLAS, TEXAS 2

3 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 logic symbol LVDS4 logic diagram (positive logic),2en A 2A,4EN A 4A SNLVDS4 EN EN Y Z 2Y 2Z Y Z 4Y 4Z A,2EN 2A A,4EN 4A Y Z 2Y 2Z Y Z 4Y 4Z This symbol is in accordance with ANSI/IEEE Std 9-94 and IEC Publication -2. logic symbol LVDS9 logic diagram (positive logic) A 2A 2 SNLVDS9 Y Z 2Y 2Z A 2A 2 Y Z 2Y 2Z This symbol is in accordance with ANSI/IEEE Std 9-94 and IEC Publication -2. POST OFFICE BOX 0 DALLAS, TEXAS 2

4 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 Function Tables SNLVDS, SNLVDS INPUT ENABLES OUTPUTS A Y Z H H X H L L H X L H H X L H L L X L L H X L H Z Z Open H X L H Open X L L H H = high level, L = low level, X = irrelevant, Z = high impedance (off) SNLVDS4 INPUT ENABLE OUTPUTS A EN Y Z H H H L L H L H X L Z Z OPEN H L H H = high level, L = low level, X = irrelevant, Z = high impedance (off) SNLVDS9 INPUT OUTPUTS A Y Z H H L L L H OPEN L H H = high level, L = low level 4 POST OFFICE BOX 0 DALLAS, TEXAS 2

5 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 equivalent input and output schematic diagrams SLLS2 JULY 99 REVISED JUNE 2000 EQUIVALENT OF EACH A INPUT VCC EQUIVALENT OF,,,2EN OR,4EN INPUTS VCC TYPICAL OF ALL OUTPUTS VCC Input V 0 Ω Input V 0 Ω 0 kω Ω Y or Z Output 00 kω V absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC (see Note ) V to 4 V Input voltage range, V I V to V CC + 0. V Continuous total power dissipation See Dissipation Rating Table Storage temperature range, T stg C to 0 C Lead temperature, mm (/ inch) from case for 0 seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : All voltages, except differential I/O bus voltages, are with respect to the network ground terminal. PACKAE TA 2 C POWER RATIN DISSIPATION RATIN TABLE DERATIN FACTOR ABOVE TA = 2 C TA = 0 C POWER RATIN TA = C POWER RATIN TA = 2 C POWER RATIN D () 2 mw. mw/ C 44 mw mw D () 90 mw. mw/ C 0 mw 494 mw DN 2.4 W. mw/ C. W. W FK mw.0 mw/ C 0 mw mw 2 mw J mw.0 mw/ C 0 mw mw 2 mw W 000 mw.0 mw/ C 40 mw 20 mw 200 mw This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC.. V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0. V Operating free-air temperature, TA SN prefix 40 SN prefix 2 C POST OFFICE BOX 0 DALLAS, TEXAS 2

6 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 SNLVDSxxxx electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS SNLVDS, 4, 9 UNIT MIN TYP MAX mv VOD Change in differential output voltage magnitude RL = 00 Ω, See Figure 2 between logic states 0 0 mv VOC(SS) Steady-state common-mode output voltage See Figure.2.2. V VOC(SS) VOC(PP) Change in steady-state common-mode output voltage between logic states See Figure Peak-to-peak common-mode output voltage ICC Supply current SNLVDS, 4 SNLVDS9 VI = 0. V or 2 V, No load VI = 0. or 2 V, Enabled Enabled, RL = 00 Ω, 0 0 mv 0 0 mv 9 20 ma 2 ma VI = 0 or VCC, Disabled 0.2 ma VI = 0. V or 2 V No load 4. ma RL = 00 Ω 9 ma IIH High-level input current VIH = µa IIL Low-level input current VIL = 0. V 0. 0 µa IOS Short-circuit output current VO(Y) or VO(Z) = ma VOD = 0 ±2 ma IOZ High-impedance output current VO = 0 or 2.4 V ± µa IO(OFF) Power-off output current VCC = 0, VO = 2.4 V ± µa CI Input capacitance pf All typical values are at TA = 2 C and with VCC =. V. SNLVDSxxxx switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS SNLVDS, 4, 9 UNIT MIN TYP MAX tplh Propagation delay time, low-to-high-level output ns tphl Propagation delay time, high-to-low-level output. 2. ns tr Differential output signal rise time (20% to 0%) RL = 00 Ω,, CL = 0 pf, ns tf Differential output signal fall time (0% to 20%) See Figure ns tsk(p) Pulse skew ( tphl tplh ) ns tsk(o) Channel-to-channel output skew 0 0. ns tsk(pp) Part-to-part skew 00 ps tpzh Propagation delay time, high-impedance-to-high-level output.4 ns tpzl tphz Propagation delay time, high-impedance-to-low-level output Propagation delay time, high-level-to-high-impedance output See Figure 4 2. ns. ns tplz Propagation delay time, low-level-to-high-impedance output. ns All typical values are at TA = 2 C and with VCC =. V. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. tsk(pp) is the magnitude of the different in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, same temperature, and have identical packages and test circuits. POST OFFICE BOX 0 DALLAS, TEXAS 2

7 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 SNLVDS electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS SNLVDS MIN TYP MAX UNIT mv VOD Change in differential output voltage magnitude RL = 00 Ω, See Figure 2 between logic states 0 0 mv VOC(SS) Steady-state common-mode output voltage.2.2. V VOC(SS) Change in steady-state common-mode output voltage between logic states See Figure 0 0 mv VOC(PP) Peak-to-peak common-mode output voltage 0 0 mv VI = 0. V or 2 V, No load ICC Supply current VI = 0. or 2 V, Enabled Enabled, RL = 00 Ω, 9 20 ma 2 ma VI = 0 or VCC, Disabled 0.2 ma IIH High-level input current VIH = µa IIL Low-level input current VIL = 0. V 0. 0 µa IOS Short-circuit output current VO(Y) or VO(Z) = ma VOD = 0 ±2 ma IOZ High-impedance output current VO = 0 or 2.4 V ± µa IO(OFF) Power-off output current VCC = 0, VO = 2.4 V ±4 µa CI Input capacitance pf All typical values are at TA = 2 C and with VCC =. V. SNLVDS switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS SNLVDS MIN TYP MAX UNIT tplh Propagation delay time, low-to-high-level output ns tphl Propagation delay time, high-to-low-level output. 4. ns tr Differential output signal rise time (20% to 0%) RL L = 00 Ω,, CL L = 0 pf, ns tf Differential output signal fall time (0% to 20%) See Figure ns tsk(p) Pulse skew ( tphl tplh ) ns tsk(o) Channel-to-channel output skew ns tpzh Propagation delay time, high-impedance-to-high-level output.4 ns tpzl tphz Propagation delay time, high-impedance-to-low-level output Propagation delay time, high-level-to-high-impedance output See Figure 4 2. ns. ns tplz Propagation delay time, low-level-to-high-impedance output. ns All typical values are at TA = 2 C and with VCC =. V. tsk(o) is the maximum delay time difference between drivers on the same device. POST OFFICE BOX 0 DALLAS, TEXAS 2

8 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 PARAMETER MEASUREMENT INFORMATION II VI A Y Z IOY IOZ VOD VOZ VOY VOC (VOY + VOZ)/2 Figure. Voltage and Current Definitions Y Input tplh tphl 2 V.4 V 0. V Input (see Note A) Z VOD 00 ± % CL = 0 pf (2 Places) (see Note B) VOD 0 00% 0% 20% 0% tf tr NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ns, pulse repetition rate (PRR) = 0 Mpps, pulse width = 0 ± 0.2 ns. B. CL includes instrumentation and fixture capacitance within mm of the D.U.T. Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal Input (see Note A) A Y Z 49.9 Ω ± % (2 Places) CL = 0 pf (2 Places) (see Note B) VOC VOC A VOC(PP) (see Note C) V 0 VOC(SS) NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ns, pulse repetition rate (PRR) = 0 Mpps, pulse width = 0 ± 0.2 ns. B. C. CL includes instrumentation and fixture capacitance within mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a db bandwidth of at least 00 MHz. Figure. Test Circuit and Definitions for the Driver Common-Mode Output Voltage POST OFFICE BOX 0 DALLAS, TEXAS 2

9 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 PARAMETER MEASUREMENT INFORMATION SLLS2 JULY 99 REVISED JUNE 2000 Y 49.9 Ω ± % (2 Places) Inputs (see Note A) 0. V or 2 V,2EN or,4en Z CL = 0 pf (2 Places) (see Note B) VOY VOZ.2 V,,2EN, OR,4EN 2 V.4 V 0. V 2 V.4 V 0. V VOY or VOZ tpzh tphz 00%,.4 V 0% 0%,.2 V A at 2 V, at VCC and Input to or at ND and Input to for LVDS only VOZ or VOY tpzl tplz 00%,.2 V 0% 0%, V A at 0. V, at VCC and Input to or at ND and Input to for LVDS only NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < ns, pulse repetition rate (PRR) = 0. Mpps, pulse width = 00 ± 0 ns. B. CL includes instrumentation and fixture capacitance within mm of the D.U.T. Figure 4. Enable and Disable Time Circuit and Definitions POST OFFICE BOX 0 DALLAS, TEXAS 2 9

10 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 TYPICAL CHARACTERISTICS Supply Current ma I CC Four Drivers Loaded Per Figure and Switching Simultaneously SNLVDS, SNLVDS SUPPLY CURRENT vs FREQUENCY f Frequency MHz Figure VCC =. V VCC =. V VCC = V tplh Low-To-High Propagation Delay Time ns LOW-TO-HIH PROPAATION DELAY TIME vs FREE-AIR TEMPERATURE VCC = V VCC =. V TA Free-Air Temperature C Figure VCC =. V tphl High-To-Low Propagation Delay Time ns HIH-TO-LOW PROPAATION DELAY TIME vs FREE-AIR TEMPERATURE VCC = V TA Free-Air Temperature C Figure VCC =. V VCC =. V 0 POST OFFICE BOX 0 DALLAS, TEXAS 2

11 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 APPLICATIONS INFORMATION SLLS2 JULY 99 REVISED JUNE 2000 The devices are generally used as building blocks for high-speed point-to-point data transmission where ground differences are less than V. Devices can interoperate with RS-422, PECL, and IEEE-P9. Drivers/receivers approach ECL speeds without the power and dual supply requirements. 00 TRANSMISSION DISTANCE vs SINALIN RATE Transmission Distance m 0 % Jitter (see Note A) 0% Jitter (see Note A) 24 AW UTP 9 Ω (PVC Dielectric) Signaling Rate Mbps NOTE A: This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern. Figure. Typical Transmission Distance Versus Signaling Rate ZO = 00 Ω VCC 2 4 A Y Z VCC 4A 4Y 4Z 4. V 0. µf (see Note A) ZO = 00 Ω 0.00 µf (see Note A) ZO = 00 Ω 2Z 2Y 2A Z Y 2 0 See Note B ZO = 00 Ω ND A 9 NOTES: A. Place a 0. µf and a 0.00 µf ZU ceramic, mica or polystyrene dielectric, 00 size, chip capacitor between VCC and the ground plane. The capacitors should be located as close as possible to the device terminals. B. Unused enable inputs should be tied to VCC or ND as appropriate. Figure 9. Typical Application Circuit Schematic POST OFFICE BOX 0 DALLAS, TEXAS 2

12 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 APPLICATIONS INFORMATION /4 LVDS TpBias on Twisted-Pair A Strb/Data_TX Strb/Data_Enable TP Ω kω LVDS2 Data/Strobe TP Ω V on Twisted-Pair B 00 Ω. V 20 kω Arb_RX 00 Ω 20 kω. V 00 Ω 20 kω 2 Arb_RX 00 Ω 20 kω kω kω. V 0 kω Twisted-Pair B Only Port_Status. kω NOTES: A. Resistors are leadless thick-film (00) % tolerance. B. Decoupling capacitance is not shown but recommended. C. VCC is V to. V. D. The differential output voltage of the LVDS can exceed that specified by IEEE94. Figure Mbps IEEE94 Transceiver 2 POST OFFICE BOX 0 DALLAS, TEXAS 2

13 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 APPLICATIONS INFORMATION SLLS2 JULY 99 REVISED JUNE µf A VCC. V V 0. µf (see Note A) N4 (2 places) ZO = 00 Ω VCC 2 4 Y Z 4A 4Y 4Z 4 ZO = 00 Ω ZO = 00 Ω 2Z 2Y 2A Z Y 2 0 See Note B ZO = 00 Ω ND A 9 NOTE A: Place a 0. µf ZU ceramic, mica or polystyrene dielectric, 00 size, chip capacitor between VCC and the ground plane. The capacitor should be located as close as possible to the device terminals. Figure. Operation with a -V Supply related information IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at for more information. For more application guidelines, please see the following documents: Low-Voltage Differential Signalling Design Notes (TI literature number SLLA04) Interface Circuits for TIA/EIA-44 (LVDS) (SLLA0) Reducing EMI with LVDS (SLLA00) Slew Rate Control of LVDS Circuits (SLLA04) Using an LVDS Receiver with RS-422 Data (SLLA0) Evaluating the LVDS EVM (SLLA0) POST OFFICE BOX 0 DALLAS, TEXAS 2

14 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 D (R-PDSO-**) 4 PIN SHOWN MECHANICAL INFORMATION PLASTIC SMALL-OUTLINE PACKAE 0.00 (,2) (0,) 0.04 (0,) 0.00 (0,2) M 4 0. (4,00) 0.0 (,) (,20) 0.22 (,0) 0.00 (0,20) NOM age Plane A (0,2) (,2) 0.0 (0,40) 0.09 (,) MAX 0.00 (0,2) (0,0) Seating Plane (0,0) DIM PINS ** 4 A MAX 0.9 (,00) 0.44 (,) 0.94 (0,00) A MIN 0.9 (4,0) 0. (,) 0. (9,0) / D 0/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.00 (0,). D. Falls within JEDEC MS-02 4 POST OFFICE BOX 0 DALLAS, TEXAS 2

15 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 DN (S-PDSO-) MECHANICAL INFORMATION PowerPAD PLASTIC SMALL-OUTLINE PACKAE 0, 0, 0,2 M 0,2 Thermal Pad (See Note D),0 2,9 4,9 4, 0, NOM age Plane 0,2,0 2, ,9 0,4,0 MAX 0, 0,0 Seating Plane 0,0 402/A 0/9 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions include mold flash or protrusions. D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO- PowerPAD is a trademark of Texas Instruments Incorporated. POST OFFICE BOX 0 DALLAS, TEXAS 2

16 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 FK (S-CQCC-N**) 2 TERMINAL SHOWN MECHANICAL INFORMATION LEADLESS CERAMIC CHIP CARRIER 4 2 NO. OF TERMINALS ** MIN A MAX MIN B MAX (,9) 0. (9,09) 0.0 (,0) 0. (9,09) A SQ B SQ (,2) 0.40 (,2) 0.9 (,) 0.9 (2,).4 (2,99) 0.4 (,) 0.0 (,) 0. (9,2) 0.92 (24,4). (29,9) 0.40 (0,) 0.49 (2,) 0.49 (2,) 0.0 (2,).04 (2,) 0.4 (,) 0.0 (4,22) 0.0 (4,22) 0. (2,).0 (2,0) (0,) 0.00 (0,2) 0.00 (2,0) 0.04 (,) (0,) 0.00 (0,2) 0.0 (,40) 0.04 (,4) 0.04 (,4) 0.0 (0,9) 0.02 (0,) (0,4) 0.00 (,2) 0.04 (,4) 0.0 (0,9) / D 0/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004 POST OFFICE BOX 0 DALLAS, TEXAS 2

17 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 J (R-DIP-T**) 4 PIN SHOWN MECHANICAL INFORMATION CERAMIC DUAL-IN-LINE PACKAE DIM PINS ** 4 20 B A MAX 0.0 (,) 0.0 (,) 0.0 (,) 0.0 (,) 4 A MIN (,) (,) (,) (,) C B MAX B MIN 0. (9,94) 0. (9,) 0. (9,94) 0. (9,) 0.90 (2,0) 0.9 (24,) 0.90 (2,2) 0.0 (,) 0.04 (,4) C MAX C MIN 0.00 (,2) 0.24 (,22) 0.00 (,2) 0.24 (,22) 0.00 (,2) 0.24 (,22) 0.00 (,2) 0.24 (,22) 0.00 (2,4) 0.00 (,) (0,) MIN A (,0) MAX 0.0 (,0) MIN Seating Plane 0.00 (2,4) 0.02 (0,) 0.0 (0,) 0.04 (0,) 0.00 (0,20) /D 0/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. E. Falls within MIL STD DIP-T4, DIP-T, DIP-T, DIP-T20, and DIP-T22. POST OFFICE BOX 0 DALLAS, TEXAS 2

18 SNLVDS, SNLVDS, SNLVDS4, SNLVDS9 SLLS2 JULY 99 REVISED JUNE 2000 W (R-DFP-F) MECHANICAL INFORMATION CERAMIC DUAL FLATPACK 0.2 (,24) 0.24 (,22) Base and Seating Plane 0.0 (2,) 0.04 (,4) 0.0 (,) 0. (9,02) 0.2 (,99) 0. (9,02) 0.2 (,9) 0.2 (,9) 0.00 (0,) (0,0) 0.04 (,4) 0.02 (0,) 0.09 (0,4) 0.0 (0,) 0.00 (,2) (,) 0. (9,42) 0.02 (0,4) 0.0 (0,) 9.02 (2,04) 0.4 (,92) / B 0/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only. E. Falls within MIL-STD- DFP-F and JEDEC MO-092AC POST OFFICE BOX 0 DALLAS, TEXAS 2

19 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated

20 of Products Development Tools Applications Search PRODUCT FOLDER PRODUCT INFO: FEATURES DESCRIPTION DATASHEETS PRICIN/AVAILABILITY SAMPLES APPLICATION NOTES USER MANUALS BLOCK DIARAMS MODELS PRODUCT SUPPORT: DEVELOPMENT TOOLS APPLICATIONS SNLVDS, Quad High-Speed Differential Drivers DEVICE STATUS: ACTIVE PARAMETER NAME SNLVDS Drivers Per Package 4 Driver tpd (ns).4 Driver (RL) (Ohms) 00 Supply Voltage(s) (V). ICC (max) (ma) Footprint AM2LS FEATURES Meets or Exceeds the Requirements of ANSI TIA/EIA-44 Standard Low-Voltage Differential Signaling With Typical Output Voltage of 0 mv and a 00- Load Typical Output Voltage Rise and Fall Times of 00 ps (400 Mbps) Typical Propagation Delay Times of. ns Operates From a Single.-V Supply Power Dissipation 2 mw Typical per Driver at 200 MHz Driver at High Impedance When Disabled or With V CC = 0 Bus-Terminal ESD Protection Exceeds kv Low-Voltage TTL (LVTTL) Logic Input Levels Pin-Compatible With the AM2LS, MC4, and ua9 DESCRIPTION The SNLVDS, SNLVDS, SNLVDS4, and SNLVDS9 are differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow operation with a.-v supply rail. Any of the four current-mode drivers will deliver a minimum

21 2 of differential output voltage magnitude of 24 mv into a 00- load when enabled. The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 00. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SNLVDS, SNLVDS4, and SNLVDS9 are characterized for operation from - 40 C to C. The SNLVDS is characterized for operation from - C to 2 C. TECHNICAL DOCUMENTS To view the following documents, Acrobat Reader.x is required. To download a document to your hard drive, right-click on the link and choose 'Save'. DATASHEET Full datasheet in Acrobat PDF: slls2g.pdf (20 KB) (Updated: 0//2000) Full datasheet in Zipped PostScript: slls2g.psz (22 KB) APPLICATION NOTES View Application Reports for LVDS and LVDM eneral Purpose Analog Applications Journal, February 2000 (SLYT02A - Updated: 0//2000) USER MANUALS Low Voltage Differential Signaling (LVDS) EVM User's uide (SLLU0, KB - Updated: 0/02/2000) BLOCK DIARAMS Color Laser Plotter (eneric) Monitoring and Control with RF Point of Sale System with Card Reader Point of Sale System with Image Recognition RF-Metering SAMPLES ORDERABLE DEVICE PACKAE PINS TEMP (ºC) STATUS SAMPLES SNLVDS/2A 0-40 TO ACTIVE Request Samples SNLVDSD D -40 TO ACTIVE Request Samples PRICIN/AVAILABILITY ORDERABLE DEVICE PACKAE PINS TEMP (ºC) STATUS BUDETARY PRICE US$/UNIT QTY=000+ PACK QTY PRICIN/AVAILABILITY SNLVDS/ TO OBSOLETE

22 of SNLVDS/2A 0 SNLVDSD D SNLVDSDR D SNLVDSNS NS SNLVDSNSR NS -40 TO -40 TO -40 TO -40 TO -40 TO ACTIVE. Check stock or order ACTIVE Check stock or order ACTIVE Check stock or order ACTIVE 2. 0 Check stock or order ACTIVE Check stock or order DEVELOPMENT TOOLS Tool Part Number Tool Title Tool Type SNLVDS-2A SNLVDS/2A LVDS Evaluation Module Evaluation Modules (EVM) MODELS SNLVDS IBIS Model (SLLC02A, 29 KB - Updated: 0/2/99) SNLVDS IBIS Model (SLLC02A, 4 KB, ZIP - Updated: 0/2/99) Table Data Updated on: /4/2000 Copyright 2000 Texas Instruments Incorporated. All rights reserved. Trademarks Privacy Policy Important Notice

23 of 2 Products Development Tools Applications Search PRODUCT FOLDER PRODUCT INFO: FEATURES DESCRIPTION DATASHEETS PRICIN/AVAILABILITY APPLICATION NOTES USER MANUALS BLOCK DIARAMS PRODUCT SUPPORT: APPLICATIONS SNLVDS, DEVICE STATUS: ACTIVE FEATURES Meets or Exceeds the Requirements of ANSI TIA/EIA-44 Standard Low-Voltage Differential Signaling With Typical Output Voltage of 0 mv and a 00- Load Typical Output Voltage Rise and Fall Times of 00 ps (400 Mbps) Typical Propagation Delay Times of. ns Operates From a Single.-V Supply Power Dissipation 2 mw Typical per Driver at 200 MHz Driver at High Impedance When Disabled or With V CC = 0 Bus-Terminal ESD Protection Exceeds kv Low-Voltage TTL (LVTTL) Logic Input Levels Pin-Compatible With the AM2LS, MC4, and ua9 DESCRIPTION The SNLVDS, SNLVDS, SNLVDS4, and SNLVDS9 are differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow operation with a.-v supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 24 mv into a 00- load when enabled. The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 00. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SNLVDS, SNLVDS4, and SNLVDS9 are characterized for operation from - 40 C to C. The SNLVDS is characterized for operation from - C to 2 C.

24 2 of 2 TECHNICAL DOCUMENTS To view the following documents, Acrobat Reader.x is required. To download a document to your hard drive, right-click on the link and choose 'Save'. DATASHEET Full datasheet in Acrobat PDF: slls2g.pdf (20 KB) (Updated: 0//2000) Full datasheet in Zipped PostScript: slls2g.psz (22 KB) APPLICATION NOTES View Application Reports for LVDS and LVDM eneral Purpose USER MANUALS Low Voltage Differential Signaling (LVDS) EVM User's uide (SLLU0, KB - Updated: 0/02/2000) BLOCK DIARAMS Electro-Optics Radar Second eneration Base Transceiver Station (BTS) Functionality (TDMA) (IS, SM900, SM00, SM900) Second/Third eneration Base Transceiver Station (BTS) Functionality (CDMA) (IS9, UMTS, WBCDMA) Target Detection Recognition PRICIN/AVAILABILITY ORDERABLE DEVICE PACKAE PINS TEMP (ºC) SNJLVDSFK FK 20 SNJLVDSJ J SNJLVDSW W - TO 2 - TO 2 - TO 2 STATUS BUDETARY PRICE US$/UNIT QTY=000+ PACK QTY ACTIVE.0 ACTIVE.02 ACTIVE. DSCC NUMBER Q2A QEA QFA PRICIN/AVAILABILITY Check stock or order Check stock or order Check stock or order Table Data Updated on: /2/2000 Copyright 2000 Texas Instruments Incorporated. All rights reserved. Trademarks Privacy Policy Important Notice