Current mode pulse width modulation/pulse position modulation based on phase lock loop

Transcription

1 Journal of ELECTRICAL ENGINEERING, VOL 68 (217), NO3, Current mode pule width modulation/pule poition modulation baed on phae lock loop Pichet Wiartpong, Vorapong Silaphan, Sunee Kurutach, Paramote Wardkein In thi paper, the fully integrated CMOS current mode PLL with current input inject at the place of input or output of the loop filter without umming amplifier circuit. It function a PPM and PWM circuit i preent. In addition, it frequency repone i an analyi which electronic tuning BPF and LPF are obtained. The propoed circuit ha been deigned with.18 µm CMOS technology. The imulation reult of thi circuit can be operated at 2.5 V upply voltage, at center frequency 1 MHz. The linear range of input current can be adjuted from 43 µa to 19 µa, and the correponding duty cycle of pule width output i from 93% to 16% and the normalized pule poition i from.93 to.16. The power diipation of thi circuit i 4.68 mw with the total chip area i 28 µm 6 µm. Keyword: pule width modulation, pule poition modulation, phae lock loop, current mode 1 Introduction Modulation i a proce of varying ome property of periodic ignal(or carrier ignal) uch a amplitude, phae or frequency. In general, the carrier ignal can be ued coine wave ignal for analog communication ytem or quare wave ignal for digital communication ytem. For digital modulation, if the carrier wave i a quare wave ignal, probably called a pule modulation, which ha three propertie to generate the modulating ignal. Pule width modulation (PWM) or pule duration modulation(pdm) i one of pule modulation technique, uing amplitude of the analog input ignal to control a width of the poitive pule or duty cycle of the pule period. The PWM technique i frequently utilized in many application uch a witching converter or motor control in control ytem or power electronic, modulation/demodulation or power amplifier in communication ytem etc. The other property of pule modulation technique ue modulating an input ignal to vary the poition of the poitive pule within the pule period. In general, it can be called Pule Poition Modulation (PPM). In PPM technique, the modulated ignal i tranmitted with hort poitive pule and all pule have both the ame poitive pule width and amplitude. The PPM ignal ha been utilized to improve efficiency of PWM, it fixe a width of the pule and decreae to mall a poible. The PPM technique ha an advantage in power output ignal i le than the PWM technique. Finally, pule amplitude modulation (PPM) which i to be convey information with varying magnitude of poitive pule of quare wave carrier proportion directly to information ignal. In general, to generate the PWM ignal, we can compare between the modulating ignal with a reference ignal which i imple to make a circuit. However, it ha a problem about the drift of the carrier frequency. Due to thi problem, many reearche are propoed to improve thi problem byuing the phae lockloop(pll) to generatethepwmignal.becauetheplliawell-knownina negative feedback ytem and give a high tability. Thu, it i an important in many area uch a controlling motor peed, modulate/demodulate, frequency yntheizer, phae hifter, carrier recovery and etc. Many year ago, the reearcher propoed a pule width modulation or pule poition modulation baed on phae lock loop [1-9]. They claified it into 2 operation type, which conited of operating in voltage mode [1-4] and current mode [5-7]. The advantage of current mode i better than voltage mode uch a larger dynamic range, high ignal bandwidth, high linearity and low power etc. From review the current mode PLL [5] and PWM baed on PLL [6-7] which propoed to apply the current mode into certain part uch a a loop filter, while other part are operated in voltage mode uch a VCO or phae detector. Therefore, in thi paper propoed a fully current mode PLL with RS F/F phae detector for imultaneou PWM/PPM ignal generation by uing CMOS Technology. For avoiding ome of the limitation or diadvantage of voltage mode uch a high voltage upply etc. The propoed model and circuit decription are hown at firt, next the imulation and the reult of thi propoed circuit by teting the characteritic of individual part and then, combined them to full current mode PWM/PPM are preented. Faculty of Engineering, Department of Telecommunication, Mahanakorn Univerity of Technology, Nong Chok, Bangkok 153, Thailand, ** Faculty of Engineering, Department of Telecommunication, King Mongkut intitute of Technology Ladkrabang, Ladkrabang, Bangkok 152, Thailand, wpichet@mut.ac.th DOI: /jee , Print (till 215) ISSN , On-line ISSN X c 217FEI STU

2 Journal of ELECTRICAL ENGINEERING 68 (217), NO The propoed Current Mode PWM/PPM and Circuit Decription 2.1 Sytem Decription and Analyi In thi article, pule width and pule poition modulator by uing current mode phae lock loop i propoed. It compot of current phae detector, current loop filter, and current control ocillator, which the reference ignal and the output ignal of current control ocillator are converted to be mono pule ignal and they arefed to be the input of RS F/F to detect the phae difference between each other. The high frequency component of the output pule ignal of RS F/F i eliminated by uing a current loop filter and then it output i ued to control the output frequency of the current control ocillator. The block diagram of phae lock loop can be hown a Fig. 1 i ( ) o ( ) I C1 PD + LPF + CCO ie( ) ii( ) il( ) i( ) k I I C2 o () Fig. 1. Block diagram of Current Mode pwm / ppm Baed on pll invere Laplace tranform of in order to get their relation in time domain G 2 φ ()+φ ()+Kφ () = Kφ i ()+ K k d I C1 ()+ + K (1+G)I C2 ()+ k Iω r +k I Gω r () (3) Ak d G d2 φ (t) dt 2 + dφ (t) dt + K k d I C1 (t)+ K Ak d +k I ω r u(t)+k I Gω r δ(t) +Kφ (t) = Kφ i (t)+ ( I C2 (t)+g di C2(t) dt ) + (4) Auming Φ i (t) = ωi(t)+θ i and input ignal I C2 (t) = when t u(t) = 1; δ(t) =, therefore G d2 φ (t) dt 2 + dφ (t) dt +Kφ (t) = Kω i t+kφ i + + K k d I C1 (t)+k I ω r (5) From Fig. 1, the meaning of the ymbolic i decribed by the following, Φ i () i a Laplace tranform of an input phae function φi(t)), Φ () i a Laplace tranform of an output phae function φ (t), Φ() i a Laplace tranform of a phae difference δφ(t), i L () i a Laplace tranform of an output loop filter i L (t), Ω L () i a Laplace tranform of an output frequency function of CCO, F() i a tranfer function of a loop filter, Ω r () i a Laplace tranform of an output frequency function of CCO when i L (t) =, k d i a gain of a phae detector, k L i a gain of a loop filter, and k I i a gain of an integrator. From ymbolic meaning above, when we find relation all of them, which φ i () and φ () relationhip F()k d k k I φ () + F()k k I I C1 () +φ () = F()k dk k I φ i () + + k k I I C2 () + k Iω r 2 (1) To obtain a econd order phae lock loop. Loop filter i aumed to be firt order LPF and it tranfer function i F() = A/(1+G ) when it i ubtituted into (1), we will derive a relation a At teady tate φ (t) = ω i t+θ i + I C1(t) k + ω rk I K ω ik I K (6) So, the phae difference between the reference ignal and the output of CCO i obtained a follow φ D (t) = φ i (t) φ (t) = ω ik I K I C1(t) ω rk I k K (7) From(7), it howthat, when thephaelockloopiin the lock tate, the difference phae i directly proportional to the frequency ofreference input ignal ω i. In addition, it i directly varied to current control of the current control ocillator (CCO) i e (t) = ω ik d K ω rk d K I C1(t) k K (8) In practice, a block diagram of PLL may be written a Fig. 2 Ak d k k I φ () (1+G) + Ak k I I C1 () (1+G) +φ () = Ak dk k I φ i () + (1+G) + k k I I C2 () + k Iω r 2 (2) i ( ) o ( ) I C1 PD + LPF + CCO ie( ) ii( ) il( ) i( ) I C2 o () whereitiaumedthat K = Ak d k k I anditiintituted into (2) we will get their relation in -domain followed by Fig. 2. Block diagram of pll in practical

3 182 P. Wiartpong, V.Silaphan, S. Kurutach, P. Wardkein: CURRENT MODE PULSE WIDTH MODULATION/PULSE POSITION... (AVG) i o Mono Stable F/F S Q R Mono Stable Phae Detector 2 Fig. 3. Block diagram and characteritic of the RS F/F phae detector Input Output +V cc M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 8 M 9 M 1 M 11 I in I out M 12 M 13 M 14 M 15 M 16 M 17 M 18 M 19 M 2 M 21 Fig. 4. Monotable Multivibrator When P(φ D (t)) i a PWM ignal if P(.) i a phae function. For frequency repone from (3) under linearity property if we intereted a relation between I C1 () and i L () In cae 1, we inert input current (I C1 ()) between phae detector and low pa filter, and give input current I C2 =. We can find a tranfer function between i L () with I C1 () i L () = F()I i () (9) i L () I C1 () = A [G 2 ++Ak d k k I ] (13) i L () = k d F()φ i () k dk k I F()(i L ()+ +I C2 ()) k dk I ω r F() 2 +I C1 ()F() (1) [ i L () 1+ F() ] k dk k I = k d F()φ i () k dk k I F()I C2 () k dk I ω r F() (11) 2 +I C1 ()F() i L () [ G 2 ++Ak d k k I ] Ak d k k I I C2 () (1+G) (1+G) = Ak dφ i () (1+G) Ak dk I ω r 2 (1+G) + AI C1() (1+G) (12) From (12) we have relationhip of one output current (i L ()) andtwoinput current (I C1 () and I C2 ()). Thu, we obtain from two poition to feed current input. Incae2,weinertinput current (I C2 ()) betweenlow pa filter and CCO, and et current input I C1 =. The tranfer function between i L () with I C2 () i obtained i L () I C2 () = Ak d k k I [G 2 ++Ak d k k I ] (14) Whichbandpafilterandlowpafilteridetermined from (13) and (14) repectively. 2.2 Phae Detector (PD) For the phae lock loop, the phae detector i needed to determine the phae difference between the reference ignal and the output ignal of current control ocillator and feedback to be input for the current control ocillator until feedback loop quiecent and approach to teady tate. For phae detector circuit, it can be catalogued to two type uch a digital phae detector and analog phae detector. For thi here, the digital phae detector i only conidered. For XOR gate PD, it achieve - π radian

4 Journal of ELECTRICAL ENGINEERING 68 (217), NO V cc M 44 M 45 M 46 I in1 M 47 M 48 M 49 M 5 M 51 M 52 M 53 I in1 I in2 M 55 M 56 M 57 I in2 Fig. 5. R-S Flip Flop Circuit difference phae and it frequency output i equal a two time of reference ignal. While the RS F/F PD give to 2π radian difference phae and it frequency output i identical to the reference ignal and the lat one, phae/frequency detector can obtain -2π to 2π radian difference phae. To detect phae in to 2π radian range, the RS F/F i ued. Before the input ignal and the reference ignal are gotten for finding phae difference, the poitive pule width of both ignal are adjuted with monotable multivibrator, then fed a the input of RS F/F which it block diagram i hown in Fig. 3, and thi phae detector ha a gain k d k d = 2π Monotable Multivibrator Circuit (15) In order to narrow poitive pule width, monotable multivibrator are employed; each individual compoe of input current ource (M 1 M 3,M 12, and M 13 ). The input current i copied to two ignal, the firt one i delivered from the M 2 and the econd one i delivered from M 3, which ued the delay of inverter to delay the input ignal, then it i fed to cacade three inverter (M 4 M 6 and M 15 M 17 ) and both ignal are fed to the input of AND gate (M 7 M 11 and M 18 M 21 ) to generate narrow poitive pule width RS Flip Flop In thi paper, RS flip flop i contructed by uing 2 NOR gate to connect a hown in Fig. 5 and Fig. 5 hown the circuit diagram. The firt one of NOR gate i compoed of tranitor M 44 M 49 and the econd one i compoed of tranitor M 5 M 57 and deliver the output ignal at drain of M Loop filter or Low Pa Filter C F I BF +V cc I BF M 64 M 65 I OF Fig. 6. Current mode firt order low pa filter The loop filter i the one of the important part of phae lock loop. It hould filter a high frequency term, and pa the output ignal that vary directly with phae difference, which thi output ignal i ued to control the output frequency of the current control ocillator and feedback to the phae detector. In thi paper, the current mode firt order low pa filter a hown in Fig. 6, it compoe of capacitor C F and current mirror which it tranfer function a follow F() = I OF = 2.4 Current Control Ocillator (CCO) 1 C FS gm +1 (16) Generally, the almot PLL are contructed to operate in voltage mode. So, it ue voltage control ocillator a a one component of PLL. Neverthele, in thi reearch, the PLL operating in current mode i propoed. Therefore, it ha to modify VCO to a CCO. Which relaxation CMOS ocillator voltage mode modifie the input ignal

5 184 P. Wiartpong, V.Silaphan, S. Kurutach, P. Wardkein: CURRENT MODE PULSE WIDTH MODULATION/PULSE POSITION... M 66 +V cc M 67 M 68 M 69 M 7 M 2 Output frequency (MHz) C =.3 pf IX = Ictrl + IOF 16.4 pf I OC.5 pf M 74 M 72 M 73 M 75 RL pf C O 8.7 pf M 76 M 77 M I X ( A) Fig. 7. Source Coupled Current Control Ocillator Fig. 8. Characteritic of CCO aacurrentwithcurrentmirror,foroutputtagev/iconverter by M71 i obtained and it circuit can be hown in Fig.6, which I X i a umming current between the output current of LPF (I OF ) and external current control input (I Ctrl ). From Fig. 6, the relationhip between frequency output of CCO (f OSC ) and I X i demontrated a follow f OSC = 1 2 t = I X/2 4C V TH (17) k = 2π 4C V TH (18) 3 Simulation and Reult To obtain current mode PLL, the phae detector circuit, loop filter or low pa filter, and current control current ocillator are deigned and layout chip by the Microwind program and rule file for CMOS.18µm with level-3 proce parameter and extract file to imulate by PSPICE program. Table 1. Proce parameter of CMOS.18 µm Parameter Typical parameter value NMOS PMOS Unit Threhold voltage (VT) V Tranconductance (K) µa/v2 3.1 Simulation reult of the CCO For CCO imulation, the CMOS circuit a hown in Fig. 7 i imulated with upply voltage VCC = 2.5 V, adjut C O from.3 pf to.7 pf with tep.1 pf and I X i adjuted from 75 µa to 17 µa, which C O =.3 pf i given 14 MHz to 21 MHz frequency range, C O =.4 pf i given 15 MHz to 165 MHz frequency range, and finally, C O =.7 pf i given a 65 MHz to 1 MHz frequency range a hown in Fig Simulation reult of loop filter Here, the current mode low pa filter i imulated by uing the circuit in Fig. 6. Firtly, we ue C F = 1 pf, H()/dB I BF =1 A A 1-2 H()/dB 1 pf 1 pf C F =1 pf k 1 M 1 M 1 G Frequency (Hz) k 1. M 1 M 1 G Frequency (Hz) Fig. 9. Frequency repone of LPF when varie I BF Fig. 1. Frequency repone of LPF when varie C F

6 Journal of ELECTRICAL ENGINEERING 68 (217), NO3 185 Table 2. Tranitor apect ratio Tranitor W/L (µm) M 1,M 5,M 6,M 9 M 11,M 13,M 16,M 17,M 2 M 22,M 26,M 27,M 3 M 33,M 35,M 38 M 39,M 42 M 45,M 49 M 51,M 54,M 56,M 57,M 59 M 61,M 63 M 71,M 74,M 75.4/.2 M 58,M 72,M 73.8/.2 M 15,M 18,M 37,M 4,M 47,M 55 1./1. M 4,M 19,M 25,M 41.5/1. M 46,M 52,M 53.4/.4 M 2,M 3,M 7,M 12,M 23,M 24,M 28,M 34.4/1. M 8,M 29,M 77,M 78 1./.5 M 76 2./.5 M 14,M 36 3./3. M 62 2./2. I IN 1 I IN 1 I mono 1 I mono 1 I IN 2 (c) I IN 2 (c) I mono 2 (d) I mono 2 (d) (e) Time (n) (e) Time (n) Fig. 11. Reult of monotable multivibrator and pd at low phae difference Fig. 12. Reult of monotable multivibrator and pd at high phae difference Duty cycle (%) 1 8 Normalized pule poition Duty cycle error (%) I X ( A) V CC (V) 2.7 Fig. 13. DC characteritic of PWM/PPM Fig. 14. Effect of power upply to duty cycle of PWM output ignal V CC = 2.5 V and their current control (I BF ) are 1 µa to 5 µa with tep 1 µa, the reult a hown in Fig. 9. The frequency repone hown the cutoff frequency i equal to 2.46 MHz, 3.37 MHz, 4.6 MHz, 5.7 MHz, and 7 MHz repectively. Secondly, the imulation i et by fixing control current (I BF ) at 1 µa and tep change C F = 1 pf, 1 pf, 1 pf. The imulation reult a illutrated in Fig. 1. In pa band, the current gain of them i equal to 1.24 db. For the cutoff frequency are MHz, 2.42 MHz, and khz repectively.

7 186 P. Wiartpong, V.Silaphan, S. Kurutach, P. Wardkein: CURRENT MODE PULSE WIDTH MODULATION/PULSE POSITION Duty cycle error (%) Temperature ( C) Fig. 15. Effect of temperature to duty cycle of PWM output ignal ( A) I LIN I PWM I PPM I RFil Time ( ) Fig. 16. Simulation reult of PWM/PPM ignal in time domain 3.3 Simulation reult of phae detector To tet characteritic of the phae detector, the circuit fromfig.4andfig.5areetupandimulated.thereult i hown in Fig. 11 for low phae different and Fig. 12 for highphae different,in ignal and (c) areinput ignal of multivibrator 1 and 2, repectively, ignal and (d) are the output of monotable 1 and 2, repectively, It hould be noted that, monotable output i triggered with negative rie edge of the input ignal and the poitive pule width i 53 p and ignal (e) i an output ignal of RS F/F or PD. 3.4 Simulation reult of PWM/PPM In thi ection, it how the imulation reult of the PWM/PPM baed on PLL ytem by uing each part on above (PD, loop filter, CCO) and combined them to PWM/PPM circuit in Fig. 13. Next, it et all tranitor by follow a Tab. 2 with DC upply voltage (V cc ) = 2.5 V, running frequency and reference frequency i 1 MHz. From the reult of CCO in Fig. 8. It i aigned CO =.6 pf for 1 MHz center frequency. In the part of ignal input (I Ctrl ) i a ine wave at frequency 5 MHz. Thu, (c) (d) the loop filter will be aigned C F = 1 pf at I BF = 1 µa from the reult of loop filter in Fig. 9 and Fig. 1. Figure 13 how the DC characteritic of the PWM/ PPM circuit between the input ignal (I Ctrl ) in x-axi with a duty cycle of the pule or pule poition on the y-axi. The repone i a linear negative lope, which can be adjuted the duty cycle from 16% to 93% or hifted the normalized poition of narrow pule from.16 to.93. Figure 14 how the effect of power upply variation wa alo carried out. The upply voltage wa varied between 2.2 V and 2.8 V in tep.1 V. Simulation reult hown in Fig. 13 indicate that the duty cycle error of PWM output ignal i between ±.6%. Figure 15 how the Simulation of temperature effect wa carried out. The temperature wa wept from 1 C to 7 C in tep of 1 C. The imulation reult hown in Fig. 14 the error of the duty cycle of PWM output ignal i increaed from -6% to 1%. It confirm that the propoe circuit i enitive to temperature variation. Figure 16 ha hown the reult of PWM/PPM circuit in time domain. The trace of ignal from top to bottom. The top trace i a ine wave ignal input (I Ctrl ) at frequency 5 MHz, current amplitude = 28 µa ppeak-topeak and offet current = 78 µa. The econd trace i a PWM output ignal it ha a variation of duty cycle between 95% to 1.64%. The third trace i a PPM output ignal. The narrow pule can be hifted between 9.5 to 1.64 n from the poition of a reference ignal. The lat ignal i a demodulate PWM ignal or ignal from the output of the loop filter. 3.5 Simulation reult of frequency repone of PWM/ PPM ytem From the ection 2.1, we analyzed a tranfer function of the propoe ytem. It i capable to feed into 2 poition. Figure 17 illutrate the comparion reult of the frequency repone of thi ytem between theory and imulation. In cae 1, we feed an external ignal between the output of PD and input of the loop filter. Reult from (13) and imulation reult how the frequency repone i a band pa filter. In cae 2, we feed an external ignal between the loop filter with CCO. Reult from (14) and imulation reult how the frequency repone i a low pa filter. Note that another advantage of thi current mode PWM/PPM baed on PLL. It doent have an offet current input in cae 1 and able to ue ignal input ame cae 2. The difference in voltage mode, if you feed current input in cae 1, you need to decreae the ummary of voltage between the voltage output P D and voltage input ignal to le than V CC or logic high. The analyi frequency repone how that i a BPF or LPF for feeding input at the input and output of the loop filter, repectively, and agree with imulation reult.

8 Journal of ELECTRICAL ENGINEERING 68 (217), NO H()/dB Theory Cae 1 Cae 2 Simulation Theory Simulation Frequency (Hz) Fig. 17. Frequency repone of the PWM/PPM ytem 4 Concluion The fully current mode PWM/PPM baed on PLL have been preented in.18 µm CMOS technology. The imulation reult of current mode PWM/PPM how that it can be operated by uing a 2.5 V power upply. The carrier frequency or center frequency can be operated at 1 MHz or more than if change the running frequency of CCO. The repone of the PWM ignal in cae of DC characteritic, it can be adjuted from 16% to 93% by varying the input control current from 93 µa to 43 µa. In cae of AC and DC characteritic, it can be adjuted duty cycle of a PWM ignal from 1.64% to 95%. The narrowpule of PPM ignal i equal to 53 p. The power diipation of thi circuit i 4.68 mw with the total chip area i 28 µ 6µm. In addition, the PPM and PWM from the propoe circuit i not yet depend on the upply voltage. Acknowledgement TheauthorwouldliketothanktheMICROWINDwho upport the Microwind licene for our layout thi ytem. Reference [1] M. J. Naila, Phae-Locked Loop Pule Width Modulation Sytem, US Patent US628216B1, 21. [2] Y. Zheng and C. E. Saavedra, Pule width modulator uing a phae-locked loop variable phae hifter, Proc. ISCAS25, 25, pp [3] P. Wiartpong, J. Koeeyaporn and P. Wardkein, Pule Width Modulation Baed on Phae Locked Loop, Proc. ECTI-CON 28, 28, pp [4] P. Wiartpong, R. Punchalard, J. Koeeyaporn and P. Wardkein, New Modified PLL Application Communication and It Output Frequency Repone Analyi, Far Eat Journal of Electronic and Communication, 212, vol. 9, no. 1, p [5] D., DiClemente, and Fei and Yuan, Current-Mode Phae Locked Loop A New Architecture, IEEE Tranaction on Circuit and Sytem-II: Expre Brief, vol. 54, no. 4, pp , April 27. [6] Jiann-Jong, Chen, Juing-Huei, Su, Yuh-Shyan, Hwang, Chwan -Lu, Teng, and Hung-Yih Lin, Wide-range high-linearity current-controlled pule-width/delay circuit, IEICE Electronic Expre, vol. 2, no. 7, pp , April 1, 25. [7] Yeong-Tair, Lin, Chi-Cheng, Wu, Jia-Long, Wu, Mei-Chu, Jen, Dong-Shiuh, Wu and Huan-Ren Cheng, A PLL-Baed Current-Mode PWM Circuit Suitable for Current-mode Control Technique, 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), October 2-23, 28, pp [8] Jingxue, Lu, Hyejeong, Song and Ranjit Gharpurey, A CMOS Cla-D line driver employing a phae-locked loop baed PWM generator, IEEE J. Solid-State Circuit, vol. 49, no. 3, pp , March 214. [9] Kunhee, Chu and Ranjit Gharpurey, A 4-17 MHz PLL-Baed PWM Driver Uing 2-/3-/5-Level Cla-D PA 13 nm CMOS, IEEE J. Solid-State Circuit, vol. 51, no. 11, pp , November 216. [1] R. J. Baker, H. W. Li and D. E. Boyce, CMOS Circuit Deign, Layout, and Simulation, IEEE Pre Serie on microelectronic ytem, [11] Arah, Ghorbannia, Delavar, Keivan, Navi and Omid Hahemi -pour, High peed Full Swing Current Mode BiCMOS Logical Operator, IJE Tranaction A: Baic, October 27, vol. 2, no. 3, p Received 18 March 217 Pichet Wiartpong wa born in Thailand, in He received hi BEng and MEng from the Faculty of Engineering in Mahanakorn Univerity of Technology in 1997 and 23, repectively. He i a lecturer in Telecommunication Engineering Department at Mahanakorn Univerity of Technology. Hi reearch interet include analog and digital communication, communication ytem model. Vorapong Silaphan wa born in Thailand. He received hi BInd Tech and MEng from the Faculty of Engineering in Mahanakorn Univerity of Technology in 1993 and 23, repectively. He i a lecturer in Telecommunication Engineering Department at Mahanakorn Univerity of Technology. Hi reearch interet include analog and digital communication. Sunee Kurutach wa born in Thailand. She received her BEng from the Telecommunication Engineering Department at King Mongkut intitute of Technology Ladkrabang, in 1987 and her MEngSc (Communication) Univerity of New South Wale, Autralia, in 199. Now, he i a lecturer in Telecommunication Engineering Department at Mahanakorn Univerity of Technology. Her reearch interet include analog and digital communication. Paramote Wardkein wa born in Thailand. He received hi MEng and DEng degree from the Telecommunication Engineering Department at King Mongkut intitute of Technology Ladkrabang (KMITL), in 199 and 1997, repectively. He i an Aociate Profeor of Telecommunication Engineering Department at KMITL. Hi reearch interet are in analog and digital communication, digital ignal proceing, and integrated circuit deign.