IEEE PEDS 2017, Honolulu, USA December 2017 Design of High-Voltage and High-Speed Driver

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1 IEEE PEDS 217, Honolulu, USA December 217 Design of High-Voltage and High-Speed Driver Wen Li, Masami Makuuchi, and Norio Chujo Center for Technology Innovation-Production Engineering, Hitachi, Ltd., Research & Development Group 292 Yoshida-cho, Totsuka-ku, Yokohama , Japan Abstract - A high-speed, high-voltage hybrid driver circuit has been designed and tested with.25-um silicon-on-insulator (SOI) laterally double-diffused metal oxide semiconductor (LDMOS) technology. The maximum output voltage of the designed driver is over 4 Vpp, and the withstand voltage is no more than 24 V. A novel circuit topology is used by dividing the driver circuit into three chips and applying different voltages to the substrates of the three chips so that the driver s maximum output voltage can achieve almost twice the withstand voltage. The bandwidth of the prototype driver is over 2 MHz. The hybrid driver is expected to be used for many industrial apparatuses. I. INTRODUCTION There are a lot of needs for high-voltage and high-speed driver circuits, such as in industrial equipment, semiconductor measuring equipment, and medical equipment. Bianchi et al. used a 9 Vpp 72 MHz GBW power amplifier for ultrasound imaging transmitters [1]. Its output voltage swing is limited by the maximum Vds of the technology which they used. For our application, a driver with an output voltage of over 4 Vpp and a bandwidth of over 1 MHz is required, but the maximum withstand voltage of the currently used technology (.25-um SOI-LDMOS) is only about 24 V. However, circuit topology that uses discrete transistors and passive elements is difficult to achieve high-speed performance [2]. A novel hybrid linear amplifier topology has been designed to resolve the trade-off of high-voltage and high-speed. II. HIGH VOLTAGE DESIGN Table 1 shows the target specifications for the designed driver. The required power supply voltage and output are about double the withstand voltage of the technology currently used. The following three design philosophies were studied to resolve the over voltage problem: (1)Voltage division by cascade connection configuration As shown in Fig. 1, a cascade connection configuration is used to divide the voltage difference, Vdd_H Vss_L, between the positive and negative power supplies applied to the driver. The input signal is amplified by the first stage amplifier. A level shifter block shifts the amplified voltage signal to the gate input on the H and L level sides separately. The final output stage block, which is composed of four transistors (P1, P2, N1, N2) and four resistors (two of and Table 1 Design Specifications Item s Target specs C ondition Pow er supply ±25 V Tem perature -15 M ax output am plitude 21 V M ax output current 15 m A O utput load 15 pf O pen-loop G ain >8 db Bandwidth >1 M H z G ain =1 Phase M argin >45 G ain =1 two of ), amplifies and outputs the expected high voltage signal. Input Amp Fig. 1 Target high voltage driver circuit PMOS (P1, P2) and NMOS(N1, N2) are cascade-connected in the final stage, and the gate voltages V3 of N2 and of P2 are as follows: R V = 2 1 ( Vdd H ) (1) + _ V 3 = ( Vss _ L) + The source voltages of P2 and N2 are as follows: V 2 = ( Vdd _ H ) Vgs _ p + V 4 = ( -Vss _ L) Vgs _ n + V3 Vdd_H P1 P2 N2 N1 Vss_L V2 V4 (2). (3) (4), /17/$ IEEE 448

2 where Vgs_p is the gate-source voltage of P2 and Vgs_n is the gate-source voltage of N2. From Equations (1) (4), if and are set as: -Vss _ L + 2Vgs _ n (5), = -Vss _ L 2Vgs _ n the drain-source voltage of NMOS and PMOS are equally divided and barely withstand half of the maximum output swing voltage. (2) Multi-substrate voltage conversion by chip division For the currently used SOI-LDMOS technology process, the transistor and the substrate are separated. The maximum drain voltage is different depending on the substrate voltage, Vsub. Fig. 2 and Fig. 3 show the withstand voltage of the drain voltage Vd when the substrate voltage is swept from - 26 V to 26 V with the conditions: the gate voltage of the NMOS (Fig. 2) is 5 V, the gate voltage of the PMOS (Fig. 3) is -5 V, and the source voltage is Vs = V. The diamonds in these figures indicate the off-state breakdown voltage, the squares indicate the on-state breakdown voltage, the solid line indicates the actual measurement results, and the dotted line indicates the device simulation results. As shown in Fig. 2, the lower the Vsub-Vs of the NMOS, the lower the on/off breakdown voltage. On the other hand, as shown in Fig. 3, the higher the Vsub-Vs of the PMOS, the lower the breakdown voltage. The off-state breakdown voltage suddenly deteriorates at a state where the Vsub-Vs of the NMOS is about 1 V or more and the Vsub of the PMOS is about -15 V or less. Furthermore, in the on-state device breakdown occurs when the Vsub-Vs of the NMOS is 15 V or more and the Vsub-Vs of the PMOS is -15 V or less. Therefore, for the ± 25 V power supply, it is necessary to divide the circuit into three or more chips in order to keep the absolute value of Vsub-Vs at15 V or less. Withstand voltage@vd sweep [V] Vsub [V] Fig. 3 PMOS withstand voltage of Vd with sweeping Vsub-vs (3) Current density reduction by limiting the voltage between gate and source. Because the withstand voltage between the drain and the source is also related to the drain current density, the withstand voltage can be increased by lowering the gatesource voltage and lowering the drain current density. Fig. 4 shows the relationship between the gate-source voltage and the drain-source breakdown voltage characteristics. By lowering the gate-source voltage from 5 V to 3 or 2 V, the withstand voltage between the drain and the source can be improved by 7 V for NMOS and 4 V for PMOS. However, if the voltage between the gate and the source is lowered, in order to allow the same amount of current to flow, it is necessary to increase the size of the transistor, which will cause the large parasitic capacitance and bandwidth deterioration. Therefore, Philosophy 3 is mainly used to supplement the shortfall of Philosophies 1 and 2. Withstand voltage@vd sweep[v] Vsub [V] Fig. 2 NMOS withstand voltage of Vd with sweeping Vsub-Vs Withstand Voltage [V] Gate-Source Voltage [V] Fig. 4 On-state withstand voltage between drain-source with gate-source voltage Circuit design was carried out by using the above three high-voltage withstanding methods. Fig. 5 shows the proposed circuit topology. In the circuit of Fig. 5, the input 449

3 amplifier, level shift and output stage, such as P1, P2, N2, and N1, are separated into three chips and different Vsub voltages are applied to each chip. The HV chip has the highest off-state withstand voltage of Vsub = 15 V. Similarly, the LV chip has the highest off-state withstand voltage when Vsub = -15 V. The MV chip is set to Vsub = - 3 V, because the breakdown voltage of the PMOS is slightly lower than that of the NMOS. MV Chip Input Amp HV Chip V3 Vdd_H P1 P2 N2 V2 V4 +15V -3V gate and source of each transistor element to protect the gatesource withstand voltage. In accordance with the above set-up, each element satisfies the withstand voltage requirement in all states. Vds [V] Vsuv-Vs [V] Time[s] Fig. 6 (a) Transient simulation result of transistor N2 N1-15V LV Chip Vss_L Fig. 5 Proposed high voltage driver circuit topology Vds [V] Because the source voltages of N2 and P2 depend on the output voltage and the voltage difference Vsub-Vs between the substrate and source voltage influences the withstand voltage performance, the simulation was used to confirm whether the withstand voltage condition is satisfied in the transient state. The substrate-source voltage and Vds of N2 and P2 are shown in Fig. 6. When Vsub-Vs 15 V, the drain-source and source-substrate voltages are less than the breakdown voltages of N2 and P2 in Fig. 2, Fig. 3, and Fig. 6. On the condition of Vsub-Vs >15 V, Vds decreases with the increase of Vsub-Vs. When Vs-Vsub =15 V, Vds is maximum and it is about 12V which is less than withstand voltage, thereby avoiding any problems. The breakdown voltage of the gate-source voltage is also important. The rated voltage between the gate and the source is 7 V. However; there is a possibility that the rated voltage between the gate and the source may exceed this in unexpected circumstances because of the circuit setup, noise, or an electric charge. A Zener diode is connected between the Vsuv-Vs [V] Time[s] Fig. 6 (b) Transient simulation result of transistor P2 III. DESIGN FOR BANDWIDTH AND STABILITY The driver circuit is used as an inverting amplifier with an outside feedback resistor, as shown in Fig. 7. The stability of such a feedback system is as important as having a bandwidth of 1 MHz or more. The open-loop transfer function of the driver circuit is designed to include two main poles. Fig. 8 shows the relationship between the open-loop gain and the phase of the driver circuit. In order to ensure stability, it is important that the first pole and the second pole are separated 45

4 enough. Target specifications of each circuit are stated in Table 2. current and the gain is small. Because the loop gain is about 4 db and the gain attenuates at 2 db/oct, the ratio of the second pole and the first pole must be larger than 1 in order to ensure a phase margin of 45 degrees or more. Cf Table 2 Specifications of Circuit Blocks I1 Rf 1 Rf2 A CL Circuit blocks Gain Bandwidth First stage amplifier 3 db >1 MHz shift -1 db >2 MHz Output stage driver 6 db >1 khz Fig. 7 Hybrid driver used as inverter amplifier Gain [db] Phase Margin [Degree] the 1st pole 2dB/oct 135 frequency frequency Fig. 8 Open-loop gain and phase margin of target driver inverter amplifier the 2nd pole 45 4dB/oct First, from the main three circuit blocks: the first stage amplifier, the level shifter, and the final output stage, the final output stage is selected as the first pole. The reasons for this are as follows. First, the output stage has a larger parasitic capacitance because the element size of the transistor in the final output stage should be large enough to satisfy the output current specification of 15 ma, and to drive the 15 pf load of the coaxial cable. Second, the output resistance of the final output stage is determined by the parallel combination of the resistance ladder and the drain resistance of the transistor. Since the transistor is used in the saturation region, the drain resistance and the resistance ladder are large. Next, the second pole is designed from the first stage amplifier. This is because the level shifter is driven by a The simulated design results of the final output stage indicate that the DC gain is 63 db and the bandwidth is 195 khz, meaning that the target specifications are satisfied. The level shifter has a diode load and a current mirror configuration with the input stage transistor of the final stage driver, as shown in Fig. 9. Therefore, no problem occurs because the transistor size of the level shifter is uniformly determined by the current mirror ratio in order to satisfy the output current specification of 15 ma. The first-stage amplifier employs a differential amplifier that uses current mirrors and resistors as output loads. By inserting resistors in parallel, DC gain is reduced to extend the bandwidth. Since the output amplitude of the first-stage amplifier needs to be smaller than 7 V because of the gatesource breakdown voltage requirements, the output amplitude of the first stage is limited by inserting an Mg transistor with a bias voltage,. The result is that the DC gain is 27 db and the bandwidth is 7.8 MHz. The un-enough 3dB of DC gain can be compensated by the final output stage. Stability is ensured by the extent phase compensation capacitor, Cf. Vb1 Vb2 Vb3 Mip1-3V MV_ チップ LV_ チップ Vb4 Mln Mcp1 Mcp2 Mmp1-25V Mip2 Mmp2 Mmp3 _L (a) shift circuit block between HV and MV chips Min1 Vb6 Vb7 Fig. 9 shift stage circuit block Vb5 15V 25V Mlp Mmn1 Mcn2 Mcn1 Min2 _H HV_ チップ MV_ チップ (b) shift circuit block between MV and LV chips 451

Mcp1 Mcp3 15V Mg Mcp2 Mcp4 Table 3 Design Results Items Target specs Design results Condition Power supply ±25 V ±25 V Max output amplitude 21 V 22 V Max output current 15 ma 15 ma Output load 15 pf

RESULTS The design results of the driver circuit are shown in Table 3. The simulation indicates that the maximum amplitude is 244 V, the -3 db band is 4.56 MHz, and the phase margin is 73 degrees.

The DC output evaluation results of the IC in Fig. 12 show an output amplitude of 212 V, which is over the target output amplitude of 21 V.

Output Voltage[V] 3 2 1-1 -2-3 -3-213V 425Vpp 212V -2-1 1 2 3 Input Voltage[V] Fig. 12 DC output characteristic of the trialed IC Tr:15ns Fc:2.3MHz Fig. 13 Rise time of the trialed IC with approx.

5 Mcp1 Mcp3 15V Mg Mcp2 Mcp4 Table 3 Design Results Items Target specs Design results Condition Power supply ±25 V ±25 V Max output amplitude 21 V 22 V Max output current 15 ma 15 ma Output load 15 pf 15 pf Open-Loop Gain >8 db >83 db Bandwidth >1 MHz 4M Hz Gain =1 Phase Margin >45 73 Gain =1 Vip Min1-3V Mcn2 Mcn1 Min2 Fig. 1 Differential first stage amplifier circuit block IV. RESULTS The design results of the driver circuit are shown in Table 3. The simulation indicates that the maximum amplitude is 244 V, the -3 db band is 4.56 MHz, and the phase margin is 73 degrees. One trial production of the IC has be carried out. Fig. 11 shows the layout image of the IC, including three chips: the HV chip, the MV chip, and the LV chip. The DC output evaluation results of the IC in Fig. 12 show an output amplitude of 212 V, which is over the target output amplitude of 21 V. The bandwidth is calculated from the rise time (1 to 9%) of 15 ns in Fig. 13, and the result is about 2.3 MHz bigger than the target of 1 MHz. Output Voltage[V] V 425Vpp 212V Input Voltage[V] Fig. 12 DC output characteristic of the trialed IC Tr:15ns Fc:2.3MHz Fig. 13 Rise time of the trialed IC with approx. 21 V amplitude HV Chip MV Chip LV Chip Fig. 11 Layout of the three trialed IC chips REFERENCES [1] Dario Bianchi, Fabio Qualia, Andrea Mazzanti, & Francesco Svelto, A 9Vpp 72MHz GBW Linear Amplifier for Ultrasound Imaging Transmitters in BCD6-SOIO, Proc. ISSCC, pp , Feb. 212 [2] J. W. Ting, W. -P. Peng, & H. -C. Chang, High voltage amplifier, Nuclear Science Symposium Conference Record, IEEE, pp Vol. 2,

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic