EM78P159N Errata document Specification Revision History

Transcription

1 8- Microprocessor with OTP ROM EM78P159N Errata document Specification Revision History Doc. Version Revision Description Date 1.0 Initial Release Version 2006/05/ Modified the Reliability Test and green product 2007/01/ Added EM78P155N package type 2007/03/ Added 14-pin and 16-pin types into the series 2007/06/ Added Appendix D 2007/07/ modify EM78P155NKM to EM78P132SS10J 2.add the characteristic at 125 o C 3.modify the table of characteristic at 25 o C 4.modify code option 5. modified Figure /11/21 Version1.4 to Version1.5 A. attached items 1 Page 39 Section 7.1 add the characteristic at 125 o C Ta=125 C, VDD=5V ± 5%, VSS=0V Symbol Parameter Condition Min. Typ. Max. Unit FXT Crystal: VDD to 3V Two cycles with two clocks DC 8.0 MHz Crystal: VDD to 5V Two cycles with two clocks DC 20.0 MHz ERC ERC: VDD to 5V R: 5.1KΩ, C: 100 pf F±30% 940 F±30% khz IIL Input Leakage Current for input pins VIN = VDD, VSS ±1 µa VIH1 Input High Voltage (VDD=5V) Ports 5, Vdd - V VIL1 Input Low Voltage (VDD=5V) Ports 5, 6-0.3Vdd - V VIHT1 VILT1 Input High Threshold Voltage (VDD=5V) Input Low Threshold Voltage (VDD=5V) (Schmitt trigger) V V VIHX1 Clock Input High Voltage (VDD=5V) OSCI Vdd - V VILX1 Clock Input Low Voltage (VDD=5V) OSCI - 0.3Vdd - V VIH2 Input High Voltage Ports 5, Vdd - V VIL2 Input Low Voltage Ports 5, 6-0.3Vdd - V VIHT2 VILT2 Input High Threshold Voltage Input Low Threshold Voltage V V VIHX2 Clock Input High Voltage OSCI Vdd - V VILX2 Clock Input Low Voltage OSCI - 0.3Vdd - V VOH1 Output High Voltage (Port 5) IOH = -4.8 ma 4.5 V VOH1 Output High Voltage (Port 6) IOH = -4.8 ma 4.5 V VOL1 Output Low Voltage(Port 5) IOL = 10.3 ma 0.5 刪除 : 4 V 刪除 : Errata Document (V1.5)

2 8- Microprocessor with OTP ROM VOL1 IPH IPD ISB1 ISB2 ICC1 ICC2 ICC3 ICC4 Output Low Voltage (Port 6) Pull-high current Pull-down current Power down current Power down current at two cycles/two clocks IOL = 10.3 ma 0.5 V Pull-high active, Input pin at VSS Pull-down active, Input pin at VDD All input and I/O pins at VDD, output pin floating, WDT disabled All input and I/O pins at VDD, output pin floating, WDT enabled Fosc=32kHz (Crystal type, floating, WDT disabled Fosc=32kHz (Crystal type, Fosc=4MHz (Crystal type, Fosc=10MHz (Crystal type, µa µa µa 10 µa 30 µa 32 µa 2.5 ma 3.5 ma Note: These parameters are theoretical values and have not been tested. Internal RC Electrical Characteristics (Ta=-40 ~125 C, VDD=2.2~5.5 V, VSS=0V) Internal RC Drift Rate Temperature Voltage Min. Typ. Max. 4MHz -40 ~125 C 2.2~5.5 V 3.3MHZ 4MHz 4.56MHz 8MHz -40 ~125 C 2.2~5.5 V 6.6MHz 8MHz 9.12MHz 1MHz -40 ~125 C 2.2~5.5 V 0.825MHz 1MHz 1.14MHz 455kHz -40 ~125 C 2.2~5.5 V 375kHz 455kHz 519kHz B. modified items 1 Page 2 Section 3 modify EM78P155NKM to EM78P132SS10J 2 Etarra Document (V1.4)

3 8- Microprocessor with OTP ROM. Figure 3-1a EM78P132SS10 Pin Assignment 2 Page 6 Section 5 Modify Figure5-1 格式化 : 字型 : 12 點, 非粗體 格式化 : 字型 : 12 點, 非粗體 3 Page 38 Section 7.1.modify the table of characteristic at 25 o C 刪除 : 2 Ta=25 C, VDD=5V ± 5%, VSS=0V Symbol Parameter Condition Min. Typ. Max. Unit Crystal: VDD to 3V Two cycles with two clocks DC 8.0 MHz FXT Crystal: VDD to 5V Two cycles with two clocks DC 20.0 MHz ERC ERC: VDD to 5V R: 5.1KΩ, C: 100 pf F±30% 940 F±30% khz IIL Input Leakage Current for input pins VIN = VDD, VSS ±1 µa 刪除 : 4 VIH1 Input High Voltage (VDD=5V) Ports 5, Vdd - V 刪除 : Errata Document (V1.5)

4 8- Microprocessor with OTP ROM VIL1 Input Low Voltage (VDD=5V) Ports 5, 6-0.3Vdd - V VIHT1 VILT1 Input High Threshold Voltage (VDD=5V) Input Low Threshold Voltage (VDD=5V) (Schmitt trigger) V V VIHX1 Clock Input High Voltage (VDD=5V) OSCI Vdd - V VILX1 Clock Input Low Voltage (VDD=5V) OSCI - 0.3Vdd - V VIH2 Input High Voltage Ports 5, Vdd - V VIL2 Input Low Voltage Ports 5, 6-0.3Vdd - V VIHT2 VILT2 Input High Threshold Voltage Input Low Threshold Voltage V V VIHX2 Clock Input High Voltage OSCI Vdd - V VILX2 Clock Input Low Voltage OSCI - 0.3Vdd - V VOH1 Output High Voltage (Port 5) IOH = -6 ma 4.5 V VOH1 Output High Voltage (Port 6) IOH = -6 ma 4.5 V VOL1 Output Low Voltage(Port 5) IOL = 16.5 ma 0.5 V VOL1 IPH IPD ISB1 ISB2 ICC1 ICC2 ICC3 ICC4 Output Low Voltage (Port 6) Pull-high current Pull-down current Power down current Power down current at two cycles/two clocks IOL = 16.5 ma 0.5 V Pull-high active, Input pin at VSS Pull-down active, Input pin at VDD All input and I/O pins at VDD, output pin floating, WDT disabled All input and I/O pins at VDD, output pin floating, WDT enabled Fosc=32kHz (Crystal type, floating, WDT disabled Fosc=32kHz (Crystal type, Fosc=4MHz (Crystal type, Fosc=10MHz (Crystal type, µa µa 1 2 µa 6 10 µa µa µa ma ma 4 Etarra Document (V1.4)

5 8- Microprocessor with OTP ROM 4 Page 30 Section 5.8 modify code option 刪除 : Code Option Register (Word 0) Word Mnemonic CLKS ENWDTB OSC2 OSC1 OSC0 HLP Protect2~Protect0 1 4clocks Disable High High High High Disable 0-2clocks Enable Low Low Low Low Enable 0 ~ 2 (protect0 ~ protect2): Protect bits Protect0 ~ Protect2 are protect bits. Protect types are as follows: protect2 protect1 protect0 Protect Enable Disable 3 (HLP): Power selection 0 = Low power 1 = High power 4 ~ 6 (OSC0 ~ OSC2): Oscillator Modes Selection bits Mode OSC2 OSC1 OSC0 ERC (External RC oscillator mode); P55/OSCO act as P ERC (External RC oscillator mode); P55/OSCO act as OSCO IRC (Internal RC oscillator mode) ; P55/OSCO act as P IRC (Internal RC oscillator mode); P55/OSCO act as OSCO MCIRC (Manual calibration IRC mode); P55/OSCO act as P55 With ICE only MCIRC (Manual calibration IRC mode); P55/OSCO act as OSCO LXT (Low Crystal oscillator mode) HXT (High Crystal oscillator mode) (default) Note: The transient point of system frequency between HXT and LXY is 400kHz. 7 (ENWDTB): 8 (CLKS): Watchdog timer enable bit 0 = Enable 1 = Disable Instruction period option bit Word 0 CLK0 Four oscillator time periods (default) 1 Two oscillator time periods 0 Errata Document (V1.5) 刪除 : 4 刪除 :

6 8- Microprocessor with OTP ROM Refer to Section 5.12 Instruction Set for further details. 9: 10: 11 ~ 12: Not used, but need to be set to 1 all the time to avoid possible error. Not used, but need to be set to 0 all the time to avoid possible error. Not used, but need to be set to 1 all the time to avoid possible error Customer ID Register (Word 1) Word Mnemonic RCOUT CYES C3 C2 C1 C0 RCM1 RCM0 1 System_clk 2cycles High High High High High High 0 Open_drain 1cycle Low Low Low Low Low Low 0 ~ 1 (RCM0 ~ RCM1): IRC mode selection bits RCM 1 RCM 0 Frequency (MHz) kHz s 5, 4, 3 & 2 ( C3, C2, C1, & C0 ): Calibration bits of internal RC mode. These bits must always be set to 1 only (auto calibration) 6 (CYES): 7 ~ 10: s 11 (RCOUT): 12: Instruction cycle selection bit 0 = one instruction cycle 1 = two instruction cycles (default) Not used System clock output enable bit in IRC or ERC mode 0 = OSCO pin is open drain 1 = OSCO output system clock Not used C. deleted items N.A Customer ID Register (Word 2) Word ~ 12: User s ID code 6 Etarra Document (V1.4)

7 8- Microprocessor with OTP ROM Version1.3 to Version1.4 D. attached items 1 Page 51 Appendix D Add appendix D D interface of ICE159N JP JP3 20 NC P52 P53 P54 RES ET GND P60 P61 P62 P63 NC P51 P50 P56 1 P55 VDD P67 P66 P65 P64 19 刪除 : 4 Errata Document (V1.5) 刪除 :

8 8- Microprocessor with OTP ROM DIP IDC PLUG 1 NC NC 20 P52 P51 P53 P50 P54 P56 DIP IDC PLUG RES ET P55 GND VDD P60 P67 P61 P66 P62 P65 10 P63 P64 11 E. modified items N.A. F. deleted items N.A. 8 Etarra Document (V1.4)