Abstract. Functional Overview TC35894FG. CMOS Digital Integrated Circuit Silicon Monolithic TC35894FG. I 2 C Slave for host interface

Transcription

1 CMOS Digital Integrated Circuit Silicon Monolithic TC35894FG Abstract The TC35894FG is IO Expander LSI which has I 2 C-bus slave for host interface, PWM/Timer control, GPIO control, and key matrix control. Those features is set and selected at the TC35894FG resisters. Functional Overview I 2 C Slave for host interface P-LQFP Weight : 0.35g(Typ.) GPIO Functions - Maximum 24 general purpose input/output ports - Selectable input or output port - Selectable pull-up or pull-down / connecting or non-connecting resistor - Selectable drive current (3 types) - Supporting pseudo open drain output buffer - Selectable interrupt detecting by level / edge / both edges and active low / high - Automatic escape from sleep mode by signal input Key Board - Key Matrix (Max 12 x 8 = 96 keys) - Support special function keys and dedicated keys - Key de-bouncing function PWM / Timer - 3 timer module for LED back light control - LED switching control by PWM sequencer Internal oscillator for system clock Sleep mode for reducing of power consumption Operating voltage 1.62V-3.6V 10mm x 10mm QFP package (44 pins, 0.8mm pin pitch, maximum 1.7mm height) 1 / /03/16

2 - Table of Contents 1 System Summary..3 2 TC35894FG Block Diagram Pin Description Pin Layout (44pin, QFP Package, Top View) TC35894FG Pin Function..7 4 Functional I/O Multiplex I/O Multiplex for KPX[7:0] I/O Multiplex for KPY[10:0] I/O Multiplex for KPY[11] I/O Multiplex for PWM[2:0] I/O Multiplexing for DIR Electrical Parameter Absolute Maximum Ratings Recommended Operating Conditions Electronic Characteristics DC Electronic Characteristics Consumption Current Characteristics (Measured by Toshiba domestic tester) AC Electrical Characteristics I 2 C AC Timing (Operation Mode) Clock Timing Internal RC-OSC Clock Power Supply Timing Application Circuit Example System diagram of using external CMOS clock oscillator System diagram of using internal RC oscillator 19 - List of Figures - Figure1-1 System Block Diagram...3 Figure2-1 TC35894FG Block Diagram..4 Figure3-1 Pin Layout (Top View)...7 Figure4-1 I/O Multiplexing for KPX [7:0].9 Figure4-2 I/O Multiplexing for KPY [10:0]... 9 Figure4-3 I/O Multiplexing for KPY [11] Figure4-4 I/O Multiplexing for PWM [2:0]...11 Figure4-5 I/O Multiplexing for DIR FIgure5-4-1 I 2 C Timing Chart Figure5-4-2 Clock Input Timing Chart..16 Figure5-4-4 Power up and Supply watchdog control 17 Figure6-1 System Integration Example with external CMOS clock.18 Figure6-2 System Integration Example with Internal RC oscillator.19 - List of Tables - Table3-2 Functional Description of the Pins....8 Table5-1 Absolute Maximum Ratings (VSS(GND)=0V) Table5-2 Recommended Operating Conditions (GND=0V).12 Table5-3-1 DC Electronic Characteristics (GND=0V)...13 Table5-3-2 Consumption Current Characteristics (GND=0V)...14 Table5-4-1 I 2 C AC Timing 15 Table5-4-2 Clock Timing (External Clock Input) Table5-4-3 Internal Clock Characteristics Table5-4-4 AC-parameters for power up and power watchdog Table6-1 Recommended Values Table6-2 Recommended Values / /03/16

3 1. System Summary TC35894FG The Figure 1-1 is the system block diagram. The TC35894FG has GPIO expanded function, key control function, and LED control function. Each function is switched by resister setting. The interface which is connected with host processor, is I 2 C-bus. The data from host processor is sent to each function block via internal bus line which is output from I 2 C-bus control block. Host Host SCL SDA VCC GND DIR24 I 2 C I2C Power Control System Control PVCI Bus (I 2 C CLK) Bus if PVCI Bus (SYSCLK) Timer2 Timer1 Timer0 Key Control GPIO IO Multiplexer PWM2 PWM1 PWM0 KPY[11:0] KPX[7:0] LED LED SW Dial SW LED LED IRQN Interrupt Control Figure1-1 : System Block Diagram 3 / /03/16

4 GND TC35894FG 2. TC35894FG Block Diagram Figure 2-1 is the TC35894FG block diagram. IRQN VCC RESETN TC35894XBG IRQ PWR SYS IOM SCL SDA I2C PVCI Bus (I2C I 2 C CLK) BIU PVCI Bus (SYSCLK) BUFFER (3*32 patterns) TIM2 TIM1 TIM0 KBD PWM1 KPY[10:0] KPX[7:0] CLK OUT CLK IN TC35894FG I 2 C GPIO[23:0] DIR KEY BUFFER GPIO DIR KEY[25:0] KBD BUFFER (8 events) PWM2 PWM0 Figure2-1 : TC35894FG Block Diagram 4 / /03/16

5 Power Supply Control (PWR) This block controls regulator, internal power supply core, and reset timing. Power supply voltage : 1.62V to 3.6V Power On Reset function System Control (SYS) This block controls clock and operating mode. Selectable clock system : Internal RC oscillator clock, or external clock Two operating modes : SLEEP and OPERATION SLEEP which doesn t supply clock on internal circuits, is low power consumption mode. OPERATION is normal operating mode. Three reset methods : Power On Reset, External Reset, and Software Reset Automatic SLEEP mode for power consumption saving Functinal I/O Multiplex (IOM) This block set each pin function. Pull-up or pull-down resistor setting and resistor connecting or non-resistor setting for each pin which is set for input terminal. Selected drive current strengths out of three different types for output terminal I 2 C Bus Control (I 2 C) This block supplies host controller data into each block. 400 khz fast mode operation 7 bit slave address recognition Default slave address is Full reprogramming feature for 7-bit slave address General call issues global reset and supports reprogramming of slave address. Read and write bursts access for consecutive register addresses Bus Interface Unit (BIU) This block converts I 2 C-bus data which is sent from host processor, into internal bus data. Timer Module (TIM0-2) This block controls PWM. PWM output signal resolution setting by programmable pre-scaler. PWM output signal duty setting by programmable pre-scaler. Automatic PWM output signal duty changing by internal sequencer. Start and stop generating control by internal sequencer. One shot operating mode and continuous operating mode controlled by internal sequencer. The timer output trigger for interrupt 5 / /03/16

6 GPIO This block sets general-purpose input and output port function. Maximal 24 general purpose input and output ports setting Input or output port setting by register. Pseudo open drain output setting is also available. Setting as input terminal for interrupt. All interrupt ports can be masked individually. Interrupt port is selectable between level sensitivity (between high level and low level active) and edge sensitivity (between positive, negative and both edges). Wake-up setting for sleep mode cancel by input signal from ports Maximal 26 direct key input ports setting Keyboard (KBD) This block controls keyboard matrix and special function keys. Maximal 96 keys setting (KPX 0-7, KPY 0-11) Keyboard detecting in hardware Keyboard scanning time set by register Output interrupt signal for host processor Supporting of key de-bouncing function Selectable between key matrix, special function key, and GPIO by register Interrupt Controller (IRQ) This block detects interrupt signal as below, and outputs it to host processor. Any GPIO logic level or edge for wake-up signal Any direct key press Any key press in the keyboard module Any Timer expiry Power watchdog failure 6 / /03/16

7 3. Pin Description 3-1. Pin Layout (44 Pins, QFP Package, Top View) KPY5 GND VSS 1 KPY11 KPX4 2 2 KPY10 KPY6 3 EXITIO0 KPY4 4 KPY9 KPX5 5 5 RESETN 6 GND VSS 6 KPY0 KPY7 7 7 KPY1 VSS 8 KPY3 DIR24 9 KPY2 DIR KPX1 SCL SDA KPY SCL KPY DIR25 KPY DIR24 KPY VSS GND 28 KPY7 KPY RESETN EXITIO KPX5 KPY KPY4 KPY KPY6 VSS 23 KPX4 VCC KPX0 SDA GND VSS 13 VDD 14 VCC 14 KPX7 15 KPX2 15 VDD 16 KPX3 16 KPY8 GND VSS 17 KPX6 IRQN 18 PWM0 VDD 19 VCC NC PWM1 GND VSS PWM2 KPY VDD VSS 43 PWM2 VCC 42 NC PWM1 41 KPX6 VDD 40 PWM0 VSS 39 IRQN VCC 38 KPY8 KPX7 37 KPX3 VCC 36 KPX2 VSS 35 VDD KPX0 34 GND KPX1 VSS Figure3-1 : Pin Layout (Top View) 3-2. TC35894FG Pin Function Each pin function is shown on Table 3-2.All inputs have CMOS Schmitt characteristics. Pins configured as inputs shall never be left floating. Those inputs should be either driven by an external source, or internally terminated by a software configurable pull-up or pull-down resistor. In additional to the normal CMOS buffer output, the port can also operate in pseudo open drain mode. Pseudo open drain output buffer uses three state output buffer and outputs only L and Z. In case of using three state output buffer for pseudo open drain output, don t apply a voltage higher than VCC. I/O Section I/O section shows I/O port situation. I means an input port. O means an output port. I/O means an input port and an output port. OD means open drain port. P means the port to be able to connect with pull-up or pull-down resistor. Default Section Default section shows a default situation of each port. I means input port without pull-up resistor or pull-down resistor. I, PU means input port with pullup resistor. I, PD means input port with pull-down resistor. Hi-Z means a high impedance port. 7 / /03/16

8 Table3-2 : Functional Description of the Pins Name I/O Default Pin Description VDD VCC - GND GND - 14, 16, 19, 35, 41, 44 1, 6, 13, 17, 21, 29, 34 LSI supply voltage Common ground SCL I I 32 I 2 C clock, up to 400kHz (fail safe a ) SDA I/OD Hi-Z 33 I 2 C data (fail safe a ) IRQN OD Hi-Z 39 Interrupt to host processor Low active. (fail safe a ) RESETN I I 27 reset line, low active (fail safe a ) KPX0 KPX1 KPX2 KPX3 KPX4 KPX5 KPX6 KPX7 KPY0 KPY1 KPY2 KPY3 KPY4 KPY5 KPY6 KPY7 KPY8 KPY9 KPY10 I/O, P I/O, P I, PU I, PU General purpose I/O, keyboard or direct key General purpose I/O, keyboard or direct Key KPY11 I/O, P I, PU 2 General purpose I/O, direct key, keyboard or clock output PWM0 PWM1 PWM2 I/O, P I, PU General purpose I/O, direct key or PWM0 General purpose I/O, direct key or PWM1 General purpose I/O, direct key or PWM2 EXTIO0 I/O, P I, PU 4 General purpose I/O or direct key DIR24 I, P I, PU 30 DIR25 I, P I, PU 31 Direct key TC35894FG Clock input, direct key or I 2 C address control DIR24 can be used as clock input when the internal RC-oscillator is not used. The re-programming of I 2 C slave address is also controlled by DIR24: Pull-down: I 2 C slave address is fixed Pull-up or external clock connected: Re-programming of I 2 C address is enabled Table 3-2 Explanation I/O can be one of: I for Input, O for output, I/O for bidirectional, OD for open drain output, P for configurable pull-up/pull down, PU for pull up, PD for pull down. a. The term fail safe means that the TC35894FG can be powered down without harming the functionality of a wire attached to this pad or without causing current flow through the pad. 8 / /03/16

9 4. Functional I/O Multiplex 4-1. I/O Multiplex for KPX[7:0] IOMUX GPIO GPOE[7:0] GPO[7:0] GPI[7:0] KPX[7:0] KBD ROW Decode KBDSIZE. ROWSIZE KBDDEDCFG. ROW[7:2] Figure4-1 : I/O Multiplexing for KPX [7:0] IOGFC.IG 4-2. I/O Multiplex for KPY[10:0] KBDSIZE. COLSIZE KBDDEDCFG. COL[10:2] IOMUX Decode GPO[18:8] GPIO GPI[18:8] KPY[10:0] COLO[10:0] KBD COLI[10:0] IOGFC.IG Figure4-2 : I/O Multiplexing for KPY [10:0] 9 / /03/16

10 4-3. I/O Multiplex for KPY[11] KBDSIZE. COLSIZE KBDDEDCFG. COL[11] IOCFG. BALLCFG IOMUX Decode Decode GPIO GPO[19] GPI[19] KBD COLO[11] COLI[11] KPY[11:8] SYS CLKOUT IOPC. KPY11PR1 IOGFC.IG Figure4-3 : I/O Multiplexing for KPY [11] 10 / /03/16

11 4-4. I/O Multiplex for PWM[2:0] IOCFG. BALLCFG IOCFG. GPIOSEL IOMUX Decode GPO[22:20] GPIO GPI[22:20] PWM[2:0] TIM PWM[2:0] IOGFC.IG 4-5. I/O Multiplexing for DIR24 Figure4-4 : I/O Multiplexing for PWM [2:0] IOCFG. BALLCFG IOCFG. GPIOSEL IOMUX Decode GPIO GPI[24] 0" DIR24 SYS CLKIN ENABLE IOGFC.IG Figure4-5 : I/O Multiplexing for DIR24 11 / /03/16

12 5. Electrical Parameter 5-1. Absolute Maximum Ratings The absolute maximum ratings as defined in below table are not meant to be exceeded during any time of the product life cycle. Exceeding the absolute maximum ratings will potentially result in permanent damage to the device. Table5-1 : Absolute Maximum Ratings (VSS(GND)=0V) Parameter Symbol Min Typ. Max UNIT Supply Voltage (-40 C to 85 C) VCC V Input Voltage (-40 C to 85 C) VIN VCC+0.3 V Output Voltage (-40 C to 85 C) VOUT VCC+0.3 V Input Current Iin ma Storage Temperature Tstg C 5-2. Recommended Operating Conditions Table5-2 : Recommended Operating Conditions (GND=0V) Parameter Symbol Min Typ. Max Unit Supply Voltage VCC V Internal Operation Frequency Note1 (Internal System Clock) Fsys 32 Note khz External Supply Frequency (External Clock Source) Fdir ,000 khz Operating Temperature Ta C Note1 : Internal operating frequency (Fsys) is made of external supply frequency (Fdir24) divided. Set register values which divides Fdir24 as Fsys is not over 100kHz. (Regarding the register setting, refer to the functional data sheet.) And set a register value to use doubler circuit or to divide Fdir24 as Fsys is greater than the SCL clock frequency divided by 6.5. In case Fdir24 is less than 1MHz, the internal doubler circuit can be used. * Example for Fsys setting Fdir24 : kHz (incase of using X-tal oscillating) I 2 C-bus SCL clock : 400kHz (maximal SCL clock frequency) In this case, 400kHz/ kHz. So, Fsys must be more than 61.54kHz. In case of using the doubler circuit, Fsys is Fdir24 x 2 = kHz. (It is not divided.) Note2 : If Fsys is less than 61.54kHz, SCL clock 400kHz can not be used. 12 / /03/16

13 5-3. Electronic Characteristics DC Electronic Characteristics IN case of no description in Condition, the characteristics are values in 6-2. Recommended Operating Conditions. Typ. shows a standard value at Ta=25 C. Table5-3-1 : DC Electronic Characteristics (GND=0V) Parameter Symbol Condition Min Typ. Max Unit Input Voltage H level VIH 0.65*VCC - VCC V Input Voltage L level VIL *VCC V VOH1 IOH=-1mA (DRV=00) (Note1) VCC VCC V Output Voltage H level Output Voltage L level Output Current H level (VCC=1.68V) Output Current H level (VCC=3.3V) Output Current L level (VCC=1.68V) Output Current L level (VCC=3.3V) Input Leak Current H level Input Leak Current L level VOH2 IOH=-2mA (DRV=01 or 10) VCC VCC V VOH3 IOH=-4mA (DRV=11) VCC VCC V VOL1 IOL=1mA (DRV=00) (Note1) V VOL2 IOL=2mA (DRV=01 or 10) V VOL3 IOL=4mA (DRV=11) V IOH1 VOH=VCC-0.4V, VCC=1.68V (DRV=00) (Note1) ma IOH2 VOH=VCC-0.4V, VCC=1.68V (DRV=01 or 10) ma IOH3 VOH=VCC-0.4V, VCC=1.68V (DRV=11) ma IOH4 VOH=VCC-0.4V, VCC=3.3V (DRV=00) (Note1) ma IOH5 VOH=VCC-0.4V, VCC=3.3V (DRV=01 or 10) ma IOH6 VOH=VCC-0.4V, VCC=3.3V (DRV=11) ma IOL1 VOL=0.4V, VCC=1.68V (DRV=00) (Note1) ma IOL2 VOL=0.4V, VCC=1.68V (DRV=01 or 10) ma IOL3 VOL=0.4V, VCC=1.68V (DRV=11) ma IOL4 VOL=0.4V, VCC=3.3V (DRV=00) (Note1) ma IOL5 VOL=0.4V, VCC=3.3V (DRV=01 or 10) ma IOL6 VOL=0.4V, VCC=3.3V (DRV=11) ma IIH01 (Note2) Vin=0V to VCC μa IIH02 (Note3) Vin=VCC, VCC=1.8V with pull-down resistor μa IIH04 (Note3) Vin=VCC, VCC=3.3V with pull-down resistor μa IIL01 (Note2) Vin=0V to VCC μa IIL02 (Note4) Vin=0V, VCC=1.8V with pull-up resistor μa IIL04 (Note4) Vin=0V, VCC=3.3V with pull-up resistor μa 13 / /03/16

14 Consumption Current Characteristics (Measured by Toshiba domestic tester) (The characteristics are different from measurement values in actual machines and boards.) Table5-3-2 : Consumption Current Characteristics (GND=0V) Parameter Symbol Condition Min Typ. Max Unit (Note5) Normal Slow Mode μa VCC=1.9V Ta=25 C Internal RC-OSC : Off IDDS (Note5) DIR24 : GND μa VCC=1.9V Ta=85 C (Note5) Normal Slow OSC Mode μa VCC=1.9V Ta=25 C Internal RC-OSC : On IDDSO (Note5) DIR24 : GND μa VCC=1.9V Ta=85 C (Note5) Normal Slow Mode μa VCC=3.6V Ta=25 C Internal RC-OSC : Off IDDS (Note5) DIR24 : GND μa VCC=3.6V Ta=85 C (Note5) Normal Slow OSC Mode μa VCC=3.6V Ta=25 C Internal RC-OSC : On IDDSO (Note5) DIR24 : GND μa VCC=3.6V Ta=85 C Note1 : The register default value is 00 which the current drive ability is minimum. Note2 : Pull-up & Pull-down are off on input mode. Note3 : Pull-down is on (Pull-up is off) on input mode. Note4 : Pull-up is on (Pull-down is off) on input mode. Note5 : Each GPIO condition is depended on the mode. Output Mode : Open Input Mode : Connected with GND or VCC 14 / /03/16

15 5-4. AC Electrical Characteristics I 2 C AC Timing (Operation Mode) t f I 2 CSDA t r t SU;DAT t f t SU;STA t HD;STA t SP t r I 2 CCLK t HD;STA t LOW t SU;STO t BUF t HD;DAT t HIGH START RE-START STOP START FIgure5-4-1 : I 2 C Timing Chart Table5-4-1 : I 2 C AC Timing Description (Note1) Symbol Min Max Unit I 2 CCLK Clock Frequency khz Hold time (repeated) START condition. After this period, the first clock pulse is generated t HD;STA μs LOW period of the SCL clock t LOW μs HIGH period of the SCL clock t HIGH μs Set-up time for a repeated START condition t SU;STA μs Data hold time t HD;DAT 0 - μs Data set-up time t SU;DAT ns Rise time of both SDA and SCL signals t r Cb (Note2) 300 ns Fall time of both SDA and SCL signals t f Cb (Note2) 300 ns Set-up time for STOP condition t SU;STO μs Pulse width of spikes which must be suppressed by the input filter t SP - 50 (Note3) ns Bus free time between a STOP and START condition t BUF μs Note1 : Output timings depend on the value of the externally used pull-up resistor. Given are the maximum allowed values from [1]. Note2 : Cb=One bus line total capacitor (Unit : pf) Note3 :.Different from [1] [1] The I 2 C-Bus Specification Version 2.1 January 2000, Philips Semiconductor 15 / /03/16

16 Clock Timing DIR24 can be driven by a LVCMOS level input clock. Then the following timings apply: C3 C2 0.9* XTAL1 DIR24 0.1*VCC1 C1 C4 Figure5-4-2 : Clock Input Timing Chart Table5-4-2 : Clock Timing (External Clock Input) Symbol Description Min Max Unit - DIR24 frequency (Note1) 32 20,000 khz C1 DIR24 input rise time - 4 ns C2 DIR24 input fall time - 4 ns C3 DIR24 input high time μs C4 DIR24 input low time μs - Duty cycle high/low 45/55 55/45 % Note1 : DIR24 < 32kHz will not lead to damage of the device but the operation of modules working at system clock can no longer be guaranteed Internal RC-OSC Clock Table5-4-3 : Internal Clock Characteristics Parameter Symbol Condition Min Typ. Max Unit Internal RC-OSC Frequency OSC_FREQ MHz Frequency Changing Level Δf/Δ C khz 16 / /03/16

17 Power Supply Timing T p1 Tp2 T p3 VCC Vcc rise Vcc fall PORSTN (internal) IRQN (from RSTINT) HiZ HiZ HiZ T p4 A B C D C Figure5-4-4 : Power up and Supply watchdog control Table5-4-4 : AC-parameters for power up and power watchdog Symbol Description Min Max T p1 Rise time for VCC (Note 1) - 80µs T p2 T p3 T p4 VCC rise VCC fall Time from VCC=VCC rise to release of PORSTN 20µs 120µs Time until VCC<=VCC fall. In case of detecting more than T p3 spike noise, 2µs - PORSTN takes by watchdog. Time from PORSTON trigger detection to activation of IRQN - 30µs Threshold level for triggering start of T p2 period to release PORSTN, when VCC rises 1.00V 1.55V Lower threshold level for activating PORSTN, when VCC starts rising again. 1.00V 1.55V VCC rise and VCC fall can be adjusted by register PORTRIM. Note1 : We assume any problem is not occurred until around 2ms. But, to make sure, we recommend to have software reset register setting after VCC power-on. 17 / /03/16

18 6. Application Circuit Example The following figures show a recommended printed circuit board design. In case of using the circuit for the application, it is necessary to confirm if there is no problem on the system System diagram of using external CMOS clock oscillator VCC1 Keyboard Matrix DIR24 KPX0... KPX7 R3 R4 KPY0... KPY11 C1 C2 + C3 SDA SCL R5 R6 IRQN PWM0... PWM2 RESETN GND Figure6-1 : System Integration Example with external CMOS clock Table6-1 : Recommended Values 1 Component R3, R4 R5, R6 C1 C2 C3 VCC=1.8V 3.3kΩ 10kΩ 1nF 10nF 10 µf 18 / /03/16

19 6-2. System diagram of using internal RC oscillator VCC1 KPX0... KPX7 R3 R4 KPY0... KPY11 C1 C2 + C3 SDA SCL PWM0... PWM2 EXTIO R5 R6 IRQN RESETN DIR24 DIR25 GND Figure6-2 : System Integration Example with Internal RC oscillator Table6-2 : Recommended Values 2 Component R3, R4 R5, R6 C1 C2 C3 VCC=1.8V 3.3kΩ 10kΩ 1nF 10nF 10 µf 19 / /03/16

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