MK7A20P 8 bit microcontroller

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1 MK7A2P. Feature ROM size: 2,48 Words OTP ROM RAM size: 72 Bytes 76 single word instruction Stack level: 2 I/O ports: 2 - Port B: 8 pull high I/O pin and has wake up function - Port A~3: 4 normal I/O pin - Port C~7: 8 normal I/O pin - RTCC: input pin Four kinds of external oscillation modes can be selected: RC, LS(Low Speed) Crystal, NS(Normal Speed) Crystal and HS(High Speed) Crystal Port B has signal toggle wake up function Built-in one 8 bit count up Timer/counter (TMR) with 8 bit programmable prescaler Built-in Watchdog Timer Operation Voltage: 2.2V 5. Different Package Type: MK7A2PD28C: 28 pin DIP MK7A2PSD28C: 28 pin SDIP MK7A2PS28C: 28 pin SOP MK7A2PSS28C: 28 pin SSOP MK7A2PSD2C: 2 pin SDIP MK7A2PS2C: 2 pin SOP MK7A2PSD8C: 8 pin SDIP MK7A2PS8C: 8 pin SOP 27/5/24 Rev.3

2 MK7A2P 2. Pin Assignment RTCC VDD NC VSS NC PA PA PA2 PA3 PB PB PB2 PB3 PB RESETB VSS OSC OSC2 PC7 PC6 PC5 PC4 PC3 PC2 PC PC PB7 PB6 PB5 RTCC VDD VDD PA PA PA2 PA3 PB PB PB2 PB3 PB4 VSS RESETB OSC OSC2 PC7 PC6 PC5 PC4 PC3 PC2 PC PC PB7 PB6 PB5 28 pin SDIP,DIP or SOP package 28 pin SSOP package PC4 PC5 PC6 PC7 OSC2 OSC RESETB VDD VSS PA PC3 PB7 PB6 PB5 PB4 PB3 PB2 PB PB PA PC5 PC6 PC7 OSC2 OSC RESETB VDD VSS PA PB7 PB6 PB5 PB4 PB3 PB2 PB PB PA 2 pin SDIP and SOP package 8 pin SDIP and SOP package 2 27/5/24 Rev.3

3 MK7A2P 3. Pin Description Name I/O Description RTCC I. External clock or pulse input to TMR counter 2. PA4 input ( When config bit6 is set to ) PA3~ I/O I/O Port A~3 PB7~ I/O. I/O Port B~7 2. Signal toggle wake up ( When config bit7 is set to ) 3. Pull-up resistor ( When config bit7 is set to ) PC7~ I/O I/O Port C~7 RESETB I System reset signal OSC I Oscillator input OSC2 O Oscillator output VDD P System power VSS P Ground <Note> I: Input; O: Output; I/O: Input/Output; P: Power 4. System Block Diagram I/O Port A I/O Port B I/O Port C I/O Port ALU 8 bit timer 72 Bytes RAM 248 word ROM Program Counter 2 Levels Stack Pre-scaler Watchdog Timer Oscillator RTCC OSC OSC2 3 27/5/24 Rev.3

4 MK7A2P 5. Memory Map 5. Program memory H PAGE FFH 2H PAGE 3FFH 4H PAGE 2 5FFH 6H PAGE 3 7FFH (RESET VECTOR) <Note> LCALL and LGOTO allow directly operate 2K word addressing. 5.2 Control Register Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit CONFIG TYPE RTCE LV LV CPT WDTE FOSC FOSC SELECT X X SUR EDGE PSA PS2 PS PS IAR $ X X X A4 A3 A2 A A TMR $ D7 D6 D5 D4 D3 D2 D D PC $2 D7 D6 D5 D4 D3 D2 D D STATUS $3 X SA SA TOB PDB Z DC C BSR $4 X X X D4 D3 D2 D D I/O Port A $5 X X X X PA3 PA2 PA PA I/O Port B $6 PB7 PB6 PB5 PB4 PB3 PB2 PB PB I/O Port C $7 PC7 PC6 PC5 PC4 PC3 PC2 PC PC 4 27/5/24 Rev.3

5 MK7A2P 5.3 Configuration Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit CONFIG TYPE RTCE LV LV CPT WDTE FOSC FOSC Bit Bit OSC Type Frequency Range LS (low speed) 32~2KHz NS (Normal speed) 2K~MHz HS (high speed) ~2MHz RC 32K~ MHz Bit 2 Description Watchdog timer disable Watchdog timer enable Bit 3 Description Code Protection ON Code Protection OFF Bit 5 Bit 4 Detected Voltage Level 4V No use 2V No use Bit 6 Description Timer Input Only PA4 Input 5 27/5/24 Rev.3

6 MK7A2P Bit 7 Description Port B has no signal toggle wake up function Port B has signal toggle wake up function <Note> When Port B is in input mode, it will has pull up resistor 5.4 Select Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit SELECT SUR EDGE PSA PS2 PS PS Bit 2 Bit Bit Description PS2 PS PS TMR rate WDT rate :2 :4 :8 :6 :32 :64 :28 :256 : :2 :4 :8 :6 :32 :64 :28 Bit 3 Description Prescaler assigned to TMR Prescaler assigned to WDT Bit 4 Description Increment when rising edge (Lo to Hi transition) on external clock Increment when falling edge (Hi to Lo transition) on external clock Bit 5 Description TMR clock source is (System Clock/4) TMR clock source is RTCC input 6 27/5/24 Rev.3

7 MK7A2P 5.5 Data memory (Register and RAM) The Data memory is composed of Register and RAM, the address map is as below: H H 2H 3H 4H 5H 6H 7H 8H FH BANK BANK BANK2 BANK3 IAR TMR PC STATUS BSR PORT A PORT B PORT C General Purpose Register General General General General Purpose Purpose Purpose Purpose Registers Registers Registers Registers H~FH 3H~3FH 5H~5FH 7H~7FH 5.5. IAR: Indirect Address Register. It is used with BSR to access a physical address TMR: 8 bit count up timer register PC: Program Counter. bit counter register. 7 27/5/24 Rev.3

8 MK7A2P STATUS: Status Register. Bit Symbol Description C DC 2 Z 3 PDB 4 TOB Carry and Borrow bit: ADD instruction SUB instruction : a carry occurred from the MSB : no carry : no borrow (Note) : a borrow occurred from the MSB Nibble Carry and Nibble Borrow bit ADD instruction SUB instruction : a carry from the low nibble bits of the result occurred : no carry Zero bit: : the result of a logic operation is zero : the result of a logic operation is not zero Power down flag bit: (Note2) : after power-on or by the CLRWDT instruction : execute SLEEP instruction : no borrow : a borrow from the low nibble bits of the result occurred Time out flag bit: : after power-on or by the CLRWDT or SLEEP instruction : Occur WDT time-overflow SA SA Page Location 6~5 SA~SA Page (H~FFH) Page (2H~3FFH) Page 2 (4H~5FFH) Page 3 (6H~7FFH) <Note>: A SUB instruction is executed by adding the 2 s complement of the subtrahend, so C = represents positive result. The below table show the relation between Carry and Borrow. BH 5H 5H BH C B7 B6 B5 B4 B3 B2 B B C B7 B6 B5 B4 B3 B2 B B 8 27/5/24 Rev.3

9 MK7A2P <Note2>: The TOB and PDB bits are active low that can be used to determine different causes of reset. The below table illustrates the value of TOB and PDB after the relative reset events. TOB PDB Reset Event WDT time out from sleep mode WDT time out from normal mode RESETB reset from sleep Power on reset Unchanged Unchanged RESETB reset from normal BSR: Bank Select Register. It is used with IAR for indirect addressing data memory. Direct Addressing Mode Indirect Addressing Mode (BSR) (opcode) (BSR) Select bank Select bank Offset data These location will map to ~F F 2F 3 4F 5 6F 7 Offset data F 3F 5F 7F Bank Bank Bank 2 Bank 3 Data Memory Port A/B/C are programmable I/O ports. All I/O pins were set to input mode in power on reset stage. 9 27/5/24 Rev.3

10 MK7A2P 5.6 Reset There are 3 kinds of condition will cause system reset: 5.6. Power-on Input a Lo signal into RESETB When WDTE flag is enabled and the timer escape 5.7 Reset condition of all the RAM Address Name Cold Reset Warm Reset N/A Accumulator xxxx xxxx pppp pppp N/A IODIR N/A Select h IAR h TMR xxxx xxxx pppp pppp 2h PC 3h STATUS xxx # #ppp 4h BSR xxx xxxx ppp pppp 5h PORTA xxxx pppp 6h PORTB xxxx xxxx pppp pppp 7h PORTC xxxx xxxx pppp pppp General Purpose RAM xxxx xxxx pppp pppp <Note> x: unknown; p: keep as previous data ; #: value depends on condition -:unimplemented and read as. 27/5/24 Rev.3

11 MK7A2P 5.8 Wake up function The chip provide pin signal toggle wake up function. It will return from sleep mode when signal toggle in input port. In order to safely wake up from sleep mode, we suggest to read the input pin to store data before entering sleep mode. The sample program is as below: MOVLA IODIR MOVM SLEEP NOP FFh PORTB ;// set bit~7 of port B as input. Only input pin can be wake up.. PORTB,a ;//Store the data of input pin before sleep ;// if doesn t perform the read instruction, then can not enter ;// SLEEP mode ;//Add NOP instruction to delay a while when chi 27/5/24 Rev.3

12 MK7A2P 6. Instruction Set <Note> Instruction cycle consist of 4 system clock Mnemonic Operands Instruction Code (Advance) Cycles Status Affected OP-code ADD M, m (M)+(acc) (M) C, DC, Z MMM MMMM ADD M, a (M)+(acc) (acc) C, DC, Z MMM MMMM AND M, m (M) (acc) (M) Z MMM MMMM AND M, a (M) (acc) (acc) Z MMM MMMM ANDLA I Literal (acc) (acc) Z iiii iiii BC M, b Clear bit of (M) None MMM MMMM BC M, b Clear bit of (M) None MMM MMMM BC M, b2 Clear bit2 of (M) None MMM MMMM BC M, b3 Clear bit3 of (M) None MMM MMMM BC M, b4 Clear bit4 of (M) None MMM MMMM BC M, b5 Clear bit5 of (M) None MMM MMMM BC M, b6 Clear bit6 of (M) None MMM MMMM BC M, b7 Clear bit7 of (M) None MMM MMMM BS M, b Set bit of (M) None MMM MMMM BS M, b Set bit of (M) None MMM MMMM BS M, b2 Set bit2 of (M) None MMM MMMM BS M, b3 Set bit3 of (M) None MMM MMMM BS M, b4 Set bit4 of (M) None MMM MMMM BS M, b5 Set bit5 of (M) None MMM MMMM BS M, b6 Set bit6 of (M) None MMM MMMM BS M, b7 Set bit7 of (M) None MMM MMMM BTSC M, b If bit of (M) =, skip next instruction + (skip) None MMM MMMM BTSC M, b If bit of (M) =, skip next instruction + (skip) None MMM MMMM BTSC M, b2 If bit2 of (M) =, skip next instruction + (skip) None MMM MMMM BTSC M, b3 If bit3 of (M) =, skip next instruction + (skip) None MMM MMMM BTSC M, b4 If bit4 of (M) =, skip next instruction + (skip) None MMM MMMM BTSC M, b5 If bit5 of (M) =, skip next instruction + (skip) None MMM MMMM BTSC M, b6 If bit6 of (M) =, skip next instruction + (skip) None MMM MMMM 2 27/5/24 Rev.3

13 MK7A2P BTSC M, b7 If bit7 of (M) =, skip next instruction + (skip) None MMM MMMM BTSS M, b If bit of (M) =, skip next instruction + (skip) None MMM MMMM BTSS M, b If bit of (M) =, skip next instruction + (skip) None MMM MMMM BTSS M, b2 If bit2 of (M) =, skip next instruction + (skip) None MMM MMMM BTSS M, b3 If bit3 of (M) =, skip next instruction + (skip) None MMM MMMM BTSS M, b4 If bit4 of (M) =, skip next instruction + (skip) None MMM MMMM BTSS M, b5 If bit5 of (M) =, skip next instruction + (skip) None MMM MMMM BTSS M, b6 If bit6 of (M) =, skip next instruction + (skip) None MMM MMMM BTSS M, b7 If bit7 of (M) =, skip next instruction + (skip) None MMM MMMM CLRA Clear accumulator Z CLR M Clear memory M Z MMM MMMM CLRWDT Clear watch-dog register TO, PO COM M, m ~(M) (M) Z MMM MMMM COM M, a ~(M) (acc) Z MMM MMMM DEC M, m Decrement M to M Z MMM MMMM DEC M, a (M) - (acc) Z MMM MMMM DECSZ M, m (M) - (M), skip if (M) = + (skip) None MMM MMMM DECSZ M, a (M) - (acc), skip if (M) = + (skip) None MMM MMMM INC M, m (M) + (M) Z MMM MMMM INC M, a (M) + (acc) Z MMM MMMM INCSZ M, m (M) + (M), skip if (M) = + (skip) None MMM MMMM INCSZ M, a (M) + (acc), skip if (M) = + (skip) None MMM MMMM IODIR M Set i/o direction None MMM IOR M, m (M) ior (acc) (M) Z MMM MMMM IOR M, a (M) ior (acc) (acc) Z MMM MMMM IORLA l Literal ior (acc) (acc) Z iiii iiii LCALL I Call subroutine. However, LCALL can addressing 2K address 2 None iii iiii iiii LGOTO I Go branch to any address 2 None iii iiii iiii 3 27/5/24 Rev.3

14 MK7A2P MOVAM m Move data form acc to memory None MMM MMMM MOVLA l Move literal to accumulator None iiii iiii MOV M, m (M) (M) Z MMM MMMM MOV M, a (M) (acc) Z MMM MMMM NOP No operation None RET Return 2 None RETI Return and enable INTM 2 None RETLA l Return and move literal to accumulator 2 None iiii iiii RL M, m Rotate left from m to itself C MMM MMMM RL M, a Rotate left from m to acc C MMM MMMM RR M, m Rotate right from m to itself C MMM MMMM RR M, a Rotate right from m to acc C MMM MMMM SELECT Set select register None SLEEP Enter sleep (saving) mode TO, PO SUB M, m (M) (acc) (M) C, DC, Z MMM MMMM SUB M, a (M) (acc) (acc) C, DC, Z MMM MMMM SWAP M, m Swap data from m to itself None MMM MMMM SWAP M, a Swap data from m to acc None MMM MMMM XOR M, m (M) xor (acc) (M) Z MMM MMMM XOR M, a (M) xor (acc) (acc) Z MMM MMMM XORLA l Literal xor (acc) (acc) Z iiii iiii 4 27/5/24 Rev.3

15 MK7A2P 7. Electrical Characteristics 7. Absolute Maximum Ratings Supply Voltage. Vss-.3V to Vss+5. Storage Temperature. 5 to 25 Input Voltage Vss-.3V to VDD+.3V Operating Temperature. to DC Characteristics Symbol Parameter VDD Test Conditions Conditions Min. Typ. Max. Unit VDD Operating Voltage V Low Voltage Detector (Idd = 3uA) 3.8 V V DVT Detect Voltage Config bit6.bit5= Low Voltage Detector 3V (Idd = ua) Config bit6.bit5= 2.2 V V IL Input Low Voltage I/O Port.8 V IDD Standby Current I IL I DD I IL R PUHI Input Leakage Current Standby Current Input Leakage Current Pull_Hi Pin Resister 3V 3V WDT disable WDT enable Vin=VDD, VSS UA UA LVD disable,wdt disable, LV disable ua LVD disable,wdt enable, LV disable LVD disable,wdt disable, LV disable LVD disable,wdt enable, LV disable 2 Vin=VDD, VSS Vol=V 35 ua Vol=. 5 Set PortB input pin and Pull_Hi Set PortB input pin and Pull_Hi 6 KΩ 5 27/5/24 Rev.3

16 MK7A2P Symbol Parameter VDD Test Conditions Conditions Min. Typ. Max. Unit Voh=4. 9 ma Voh=4.V 8 ma Voh=3. 22 ma I OH PA~3 output port, PB~7 output port, PC~3 output port, Driving Current Voh=3.V 26 ma Voh=2. 29 ma Voh=2.7V 4 ma Voh=2.4V 7 ma 3V Voh=2.V 9 ma Voh=2.V ma Voh=.8V 2 ma Voh=. 2 ma Voh=.V 37 ma Voh=. 48 ma I OL PA~3 output port, PB~7 output port, PC~3 output port, Sink Current Voh=2.V 55 ma Voh=2. 59 ma Voh=.3V 8 ma Voh=.6V 6 ma 3V Voh=.9V 2 ma Voh=.2V 25 ma Voh=. 26 ma 6 27/5/24 Rev.3

17 MK7A2P 7.3 AC Characteristics Test Conditions Symbol Parameter VDD Conditions Min Typ Max Unit f sys f sys2 f sys3 f sys4 T wdt T rht System Clock System Clock System Clock System Clock Watchdog Timer Reset Hold Time 3V 3V 3V 3V 3V 3V LP Crystal mode NT Crystal mode HS Crystal mode RC mode K 32K Khz Mhz Mhz Mhz ms ms 7.4 External RC Table R value C value RC frequency R connect to (VDD,OSC) 4.9 M.u (need) 32 Khz The capacitor is need for stabile frequency 25 K.u (suggest) 455 Khz 6 K.u (suggest) Mhz 6 K.u (suggest) 2 Mhz 32 K.u (suggest) 4 Mhz 8 K.u (suggest) 8 Mhz 4 K.u (suggest) Mhz 7 27/5/24 Rev.3

18 MK7A2P 7.5 Oscillator circuit in different mode VDD OSC2 C3 VDD OSC2 R RESETB MK7A2P OSC C2 R RESETB MK7A2P OSC R2 C C C4 Crystal mode RC mode Crystal mode Crystal C2 C3 LP mode 32 Khz 2~P 2~P 455 Khz P P NT mode 455 Khz P P Mhz 2~P 2~P 2 Mhz 2~P 2~P 4 Mhz 2~P 2~P 8 Mhz 2~5P 2~5P Mhz 2~5P 2~5P HS mode 2 Mhz 2~5P 2~5P 6 Mhz 2~5P 2~5P 2 Mhz 2~5P 2~5P <Note> R/C value of RESETB depends on user s system request 8 27/5/24 Rev.3

19 MK7A2P 8. Package Dimension (a) 28 Pin DIP (6 mil) L A A A2 B B e D D.85 E C E eb BOTTOM E-PIN INDENT # ø.25 x.6 DP x 2PLS TOP E-PIN INDENT ø.25" x.6dp xm 2PLS BOTTOM E-PIN INDENT #2 DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES SYMBOLS MIN NOM MAX MIN NOM MAX A A.38.5 A B B C D D.3.5 E E e L eb /5/24 Rev.3

20 MK7A2P (b) 28 Pin SOP (TOP7.78±.5) (BTM7.83±.5).58X45 5 ± (TOP7.443±.5) (BTM7.493±.5).3±. TOP ø.x.~.5dp BTM ø EPINX.5~.DP.27 3 ± ±.5.4± ± ±..762± /5/24 Rev.3

21 MK7A2P (c) 2 Pin DIP D E A L A A2 C B B e D eb.4 E TOP E-PIN INDENT ø.79 BOTTOM E-PIN INDENT ø.8 SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES MIN NOM MAX MIN NOM MAX A A.38.5 A B B C D D E E e L eb /5/24 Rev.3

22 MK7A2P (d) 2 Pin SOP (TOP2.65±.5) (BTM2.7±.5).58X45 5 ± ±2.524 (TOP7.443±.5) (BTM7.493±.5).3±..762± TOP.x.5~.DP BTM2. SEAING PLANE ±.5.4± ± ± /5/24 Rev.3

23 MK7A2P (e) 8 Pin DIP D E A L A A2 C B B e D eb.727 E PIN INDICATOR ø.39 TOP E-PIN INDENT ø.79 BOTTOM E-PIN INDENT ø.8 SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES MIN NOM MAX MIN NOM MAX A A.38.5 A B B C D D E E e L eb /5/24 Rev.3

24 MK7A2P (f) 8 Pin SOP (TOP.57±.5) (BTM.557±.5).58X (TOP7.443±.5) (BTM7.493±.5).3± ±3.762±.76 3 ±2.27 BTM2. TOP.x.~.5DP SEAING PLANE ±.5.4± ± ± /5/24 Rev.3

On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely 12 I/O pins with their own independent direction control 3. Applications The ap

On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely 12 I/O pins with their own independent direction control 3. Applications The ap MDT2010 1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology combines higher speeds and smaller size with the low power and high noise immunity of CMOS.