STUDIES OF THE SILICON DRIFT DETECTOR: DESIGN, TECHNOLOGY DEVELOPMENT, CHARACTERIZATION AND PHYSICS SIMULATIONS

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1 , pp STUDIES OF THE SILICON DRIFT DETECTOR: DESIGN, TECHNOLOGY DEVELOPMENT, CHARACTERIZATION AND PHYSICS SIMULATIONS Pourus Mehta*, K.M. Sudheer, V.D. Srivastava, V.B. Chandratre, C.K. Pithawa Electronics Division, Bhabha Atomic Research Centre, MOD Lab, Trombay, Mumbai, , India, * Received 6 October, 2011 Abstract Silicon Drift Detectors (SDDs) are being developed for low energy (0.12 kev to 12 kev) X-ray spectroscopy and position sensing applications using silicon bipolar technology available with Bharat Electronics Ltd (BEL), Bangalore. As a part of this development, the first batch of proto-type SDDs have been realized through a pilot stage fabrication run at the Micro-fabrication facility at Indian Institute of Technology - Bombay (IIT-B). This paper presents a detailed view on the design; fabrication and characterization of the first prototypes of SDDs. SDDs fabricated at IIT- Bombay were characterized to extract critical dc (I-V and C-V) performance parameters like total leakage current at anode, full depletion anode capacitance and full depletion voltage. Device simulations in Technology Computer Aided Design (TCAD) were employed to extract analytical values of these performance parameters. Based on the results from characterization of proto-type SDDs developed at IIT-B, the mask layout consisting of various designs of SDDs and JFETs to be fabricated at BEL was designed. Keywords: silicon drift detector, junction field effect transistor, technology computer aided design, I-V characterization, C-V characterization 1. Introduction The silicon drift detector (SDD) is a device based on the principle of sideward depletion and lateral charge transport in the bulk of a fully depleted detector, as proposed by Gatti and Rehak [1]. SDD is essentially a double-sided diode detector, in which a high resistivity n-type substrate is employed to fabricate p-n junctions on both sides of the substrate. p-n junctions on the front side are in the form of segmented strips, which act as field shaping cathodes whereas a uniform, p-n junction forms the back-cathode. A reverse bias gradient is applied to the field shaping electrodes w.r.t. anode such that the least reverse voltage is applied to the cathode nearest to the anode (Cathode-1) and the highest to the farthest cathode (Cathode-6). The back-cathode is held at a reverse bias, which is half of the maximum reverse bias applied to Cathode-6 w.r.t. anode. This reverse bias gradient can be applied through an external potential divider network or through and on-chip resistor network. The bulk of the silicon substrate depletes at a reverse bias of around 17 V applied to all field cathodes and back-cathode w.r.t. anode. As the reverse bias is increased further and reaches targeted detector bias of 100 V, the potential distribution in the SDD takes the shape of a Potential Gutter as shown in Fig. 1a. The potential in one-dimension along the thickness of the wafer is parabolic in nature and has a minima at a depth which is decided by the potential difference applied to the p cathode and p back-cathode. Electron-hole pairs created by passage of ionizing radiation are swept vertically by the parabolic potential along the depth/thickness of the wafer and are concentrated at the point of minimum potential in the depth, from where they get drifted along

2 the drift channel (Fig. 1b) towards the anode (ultimate potential energy minimum for electrons) where they ultimately get collected. The striking feature of the SDD is its small output (anode) capacitance, which is independent of its large detector active area. (a) Fig. 1. a) potential energy distribution in SDD, b) 2-dimensional cross-section of circular-220μm SDD. This makes SDD suitable for high resolution ( kev for MnK line; Ketek Vitus SDD) and high count rate (~ cps) X-ray spectroscopy [2] applications. Commercially available SDDs give energy resolution of the order of 190 ev FWHM at 5.9 kev for MnK line [3]. These detectors also find wide application in high-energy physics for tracking and have been employed in the ALICE experiment of Large Hadron Collider at CERN. The high-resolution capability of SDDs can be further augmented by integrating the input device of the pre-amplifier (JFET) with the detector so as to avoid stray capacitance and microphonism arising due to wire bonding between them [4]. The integration of JFET onto the detector also facilitates better matching between detector and transistor capacitances. The technology for fabrication of SDD is being developed and as a part of this development, prototyping stage fabrication was carried out at IIT-B. The fabrication process employed at 176

3 IIT-Bombay involved all the standard micro-fabrication steps like oxidation, lithography, etching, implantation, and metallization. Values of process parameters like implant dose, drive-in time-temperature cycle etc. employed for each of the above steps were derived through a process simulation study using standard models [5]. The process for the fabrication of SDD was formulated with a view of achieving a high breakdown voltage (>100 V) and as low a leakage current as possible using the existing fabrication setup at IIT-Bombay. The SDDs fabricated at IIT were characterized for their dc performance (I-V and C-V) to extract critical electrical performance parameters like breakdown voltages, full depletion anode capacitance and anode current at full-applied bias ( 100 V). In addition, process performance parameters like minority carrier lifetime, breakdown voltages, and interface oxide charge were derived from characterization of the test structures ( p-i-n diodes and MOS capacitors) fabricated on the same silicon substrate. Based on the results derived from the SDDs fabricated at IIT-B, the mask set for fabrication of SDDs on a commercial scale at Bharat Electronics Ltd (BEL), Bangalore was designed. SDDs commercially available through brands like KETEK and PNSensor are primarily aimed at X-ray spectroscopy applications whereas SDDs fabricated at BEL were aimed at both X-ray spectroscopy and position sensing applications. Among the SDDs designed for X-ray spectroscopy applications were detectors of circular, hexagonal and spiral geometries with in-built low noise JFETs. The SDD designed for X-ray spectroscopy applications had a circular geometry with on-chip resistors and an on-board hybrid design of JFET with embedded MOSFET for amplification and reset purposes respectively, together with a feedback (MOS) capacitor fabricated over the anode region [6]. Linear geometry SDDs with on-chip polysilicon resistors and in-built JFET were designed for position sensing applications. Additionally, there were miscellaneous designs of SDDs coupled with high transconductance ( gm 13 ms) JFETs. Among those, one particular design of SDD which had a linear geometry SDD having an anode which was sub-divided into 8 anode pads with each pad connected to its own on-chip JFET ( gm 2.32 ms) for on-chip readout of each anode pad. Lastly, there was one design of a prototype SDD imaging array implemented with hexagonal geometry SDDs and having 30 SDD cells. The fabrication of SDDs at BEL is at an advanced stage of processing and results are awaited. 2. Detector design A circular design for SDD is advantageous as the field across the detector is essentially radial and constant throughout the device. A cross-sectional view of the circular geometry SDD having a p cathode pitch of 220 μm is shown in Fig

4 (a) (b) Fig. 2. a) Composite layout of circular 220 μm SDD showing all layers of the mask and b) micrograph showing the completely fabricated circular SDD (bottom). Starting with an n-type, high resistivity (4 kω cm), <111>, 300 μm thick silicon wafer, a boron implant on the front side formed the p field shaping electrodes (cathodes/strips) whose widths in this design were 110 μm with a 110 μm interstrip gap between adjacent p strips (Pitch = Strip Width + Gap = 220 μm). The peak boron concentration in p 178 cathode region was approximated around cm 3 with a gaussian distribution along depth. Next, a phosphorus implant formed the n anode region having a 75 μm radial width (Area μm 2 ) and concentrically spaced from the first p strip at 55 μm. This particular SDD design had 6 p cathodes with two additional p implants encircling the outer perimeter functioning as guard rings. These guard rings were incorporated to prevent breakdown of the last p cathode, which is biased at the highest reverse bias. The first guard ring to last p cathode spacing and the interguard ring spacing was fixed at 70 μm on the basis of the following understanding. At zero applied bias, the equilibrium depletion width for p -n junctions of cathodes and guard-rings is 27.5 µm ( Vbi 0.57 V) which leaves just 15 microns of undepleted space between guard-rings, which will deplete at less than 10 V of applied guard-ring reverse bias. Lastly a uniform p implant on the backside of the wafer formed the back cathode. The total active area of the circular SDD of pitch 220 μm is μm Process technology and simulations The purpose behind performing process simulations was to arrive at an optimized process within the technological constraints associated with the fabrication laboratory at the IIT-Bombay.

5 The doping profiles in this case were mainly governed by drive-in diffusion and not by ion implantation as the ion energies required to create p cathodes at desired depths would be around >100 kev and the ion-implanter employed could only deliver ion energies of 30 kev. The process for the fabrication of SDD was formulated with a view of achieving a high breakdown voltage of >100 V, and achieving as low leakage current as possible using the existing fabrication setup at IIT-Bombay. Starting with an n-type high resistivity (3 5 kω cm), <100> (chosen due to unavailability of high resistivity <111> wafers at IIT-B), double side polished wafer, an initial oxide was grown employing the dry-wet-dry oxidation regime (T 1050 C, t total 2 h and 52 min). This was done to have a good quality (dry) oxide at the Si-SiO 2 interface whereas the bulk oxide was grown through wet regime to reduce oxidation time for growth of a 0.35 μm thick oxide. Then the n anode region was defined by a lithographic step (Mask-1), which was followed by an oxide etch step to expose the substrate for phosphorus implantation (E 25 kev; D cm 2 ). The dopant activation was performed in a pyrogenic oxygen ambient (t 30 min, T 1000 C) to grow a thick oxide (d ox = 0.3 µm) over the implant window for protection from the next implant species (boron). The simulated doping profile for the phosphorus implant (Fig. 3) shows a peak phosphorus concentration of cm 3 for a characteristic depth of 0.7 μm and sheet resistance extracted from simulation was Ω/. The sheet resistances were measured for both n and p implants using special four-probe structures, which were incorporated as test devices along with 13 different SDD designs on the 2-inch silicon wafer. The measured sheet resistance for n-type region was Ω/. Subsequently the p strips/cathodes were defined (Mask-2) and boron implantation (E 25 kev; D cm 2 ) was performed followed by a short drive-in step (t 30 min, T 1000 C) to form p cathodes. The value of sheet resistance from simulation for the boron implant was Ω/, for a junction depth of 0.56 μm and surface concentration of atoms/cm 3. The measured sheet resistance for the p-type cathode region was Ω/. The deviation in measured sheet resistances values from those derived from simulation was within 20 %. The third lithography (Mask-3) was performed for definition of contact windows for making contact with metal to be deposited in the next step. Aluminum was then deposited using electron-beam evaporation method in a vacuum of Torr for a deposition rate of 50 Å/sec to a thickness of 0.98 µm to form the metal electrodes over the p-n junctions. The aluminum film was then patterned by a positive photoresist lithography step (Mask-4). An aluminum film was deposited on the backside for back-contact connection followed by a post metallization annealing step (T 400 C, t 30 min, N 2 ambient) for alloying the aluminum films on both sides of the wafer. 179

6 Fig. 3. One-dimensional doping profile of boron and phosphorus implants. 4. I-V characterization and device simulation 4.1. Objectives and measurement methodology I-V characterization of the completely biased SDD was performed to get the total biasing current across all the p strips and the total leakage current at the anode for a detector bias of 100V. The SDDs designed for IIT case were such that all p cathodes had to be individually biased. The wafer containing 13 different designs of SDDs was scribed and the die s were packaged in 30 pin metal can packages with wire bonds connecting each bond pad, including all p cathodes (Fig. 4). A single Keithley-2400 source-measure unit was used to supply voltages to all the nodes through an external resistor network consisting of 20 resistors of 100 kω each, giving a minimum voltage of 5V at each node. Wafer level characterization was performed for each design of SDD. The anode was given a zero potential (ultimate potential energy minima for electrons) and the first p strip/cathode (Cathode-1) was given a bias of 19.7 V. The last p cathode (Cathode-6) was biased at 100V and the back-cathode potential was fixed at 50V. The p cathodes intermediate between the first and last cathodes got biased automatically by punch-through phenomenon. Potentials on individual electrodes were measured (including intermediate cathodes) and their values are tabulated in Table 1. (S1, S2, S3, S4, S5 and S6 correspond to Cathode-1, 2, 3 4, 5 and 6 respectively, G1 corresponds to guard-ring-1). To prevent any leaky p -n junction from modifying the potentials at the nodes of the external voltage divider, reverse biased Zener diodes with voltage ratings of 5 V, 10 V, till 100 V were 180

7 connected at the appropriate voltage nodes in reverse bias between the node on the resistor network and ground. A program was written in C++ to interface the Keithley meters and to automate the measurement process. Once the SDD was biased correctly, I-V was taken by ramping the voltage at the last strip (Cathode-6) from 100 V to 0 V and the anode current was measured through an ammeter (Keithley-2400 SMU used in current sense mode). Fig. 4. Photograph of the processed 2-inch wafer. Table 1. Measured potentials at various p cathodes/electrodes. Sr no Electrode Potential (Volts) 1 Anode 0 2 Cathode-1 (S1) Cathode-2 (S2) Cathode-3 (S3) Cathode-4 (S4) Cathode-5 (S5) Cathode-6 (S6) Guard-ring- 1 (G1) Results and Discussions The anode, Cathode-1, Cathode-6 and back-cathode electrodes were biased as described in section 4.1 and the resultant I-V characteristics were extracted for various values of guard-ring voltages (Fig. 5). The typical I-V characteristics of the circular SDD (pitch = 220 µm) device at a guard-ring voltage of 55V is shown in Fig. 6. The leakage current at the anode is dependent on the total depleted active volume of the device as well as the total number of thermally generated carriers at the ambient temperature (26 C). As seen from Fig. 7, the anode current increases as the depletion region width increases with voltage through a V relationship. It is seen that after the total detector bias voltage reaches 50V, the current begins to rise linearly with voltage up to 100V. The unexpected rise in anode current can attributed to either of the cases of Si-SiO 2 181

8 interface trap related increase in leakage current or increased thermally induced carrier generation due to a slight increase in silicon surface temperature caused by a high p cathode current density. Moreover a higher silicon surface temperature can also lead to changes in carrier mobility as a side effect. Fig. 5. Circuit Diagram for biasing scheme for SDD. Fig. 6. Anode current versus Cathode-6 voltage for various values of guard-ring voltages. Fig.7. Anode current versus Cathode-6 voltage at guard-ring voltage 55V for circular SDD of 220 m pitch. 182

9 At a particular guard ring voltage, as the Cathode-6 voltage is being ramped from 0 to 100V, the depletion width of the Cathode-6 junction increases and merges with the equilibrium depletion region of the floating Cathode-5, which gets biased at a potential lower than Cathode-6 voltage. As the Cathode-6 voltage reaches 70V, the depletion regions of all p + cathode junctions (Cathode-1 to Cathode-6) merge (punch-through) into one continuous region and all floating cathodes (Cathodes 2, 3, 4, 5) get biased. The negatively biased cathodes begin to attract holes and a small hole current begins to flow via the interstrip gaps from Cathode-1 to Cathode-6 (ultimate potential energy minima for holes). This hole current is referred to as p strip current in Fig. 8 as it is the current flowing between p strips/cathodes. As the Cathode-6 voltage increases further, the barrier to hole conduction vanishes leading to the hole current increasing linearly with voltage and reaching 1 ma at the Cathode-6 voltage of 100V (Fig. 8). Fig. 8. p strip current versus Cathode-6 Voltage for circular SDD of 220 m pitch. Table 2. Guard-ring bias v/s anode current. Sr no Guard-ring Bias, V Anode current na µa µa µa 5 Float 6.2 µa It was seen that the major component of p strip current flows between the Cathode-6 and first guard ring (guard-ring 1) at any guard ring voltage except 100V. Additionally I-V characteristics were also performed at various guard-ring voltages and the anode current (Fig. 5) was measured to study the effect of guard ring voltage variation on anode current (Table 2). For a guard ring bias of 0 V, the potential distribution is such that the potential minimum (drift) channel cannot be formed and hence the lateral drift of carriers is not possible. 183

10 At a guard-ring voltage of 20 V, the cathode current begins to flow from first to last cathode and the drift channel is restored. The optimum guard ring bias can be considered to be 55 V as baring the cases of guard ring bias of 0 V and 20 V, the anode current has the lowest value for V guard 55 V Device Simulation A device simulation of the I-V characteristics was performed for the Circular-220 micron SDD using a cylindrical mesh to emulate a 3-dimensional geometry using Silvaco ATLAS TCAD device simulator. Firstly, a virtual 2-dimensional cross section for the device had to be defined with the radius of the circular structure as the X-axis and the thickness of the wafer as the Y-axis. A suitable mesh was generated with a maximum number of grid points (~20,000), which is the grid point limit in ATLAS device simulator. The grid density in this case worked out to be grid-points/unit Area, which is the maximum possible density for this SDD structure. Then, regions like silicon, metal, oxide etc were defined for various areas of the 2-dimensional cross-section. Once the structure was generated, appropriate voltages were applied to metal electrodes viz. anode, Cathode-1 (S1), Cathode-6 (S6), Guard-ring-1 (G1), Guard-ring-2 (G2) and back-cathode as shown in Table 3. The one-dimensional surface potential across the lateral dimension of the simulated structure was plotted (Fig. 9). Additionally, cathodes 2, 3, 4 and 5 were attributed to a current boundary condition (I 0 A) to simulate floating nature of these electrodes as done in actual measurement. A Si-SiO 2 interface defect density of cm 3 and a fixed oxide charge of cm 2 (as measured by C-V measurement of Test MOS capacitors) have been added as interface parameters to the simulation. The Poisson and continuity equations were solved at every grid point with appropriate initial guesses using Newton s method. The minority carrier lifetime parameter was set to 150 μs as observed by actual lifetime measurement by diode reverse recovery method [7]. The anode current was plotted versus the Cathode-6 voltage (Fig. 10) as also the Cathode-6 current versus Cathode-6 voltage (Fig. 11). The anode current derived from simulation was 1.27 µa whereas the measured anode current was 1.03 µa (Table 4). This translated into a deviation of 18.89% in values derived from simulation versus experimental ones. It is many a times difficult to accurately model non-linear effects originating from fabrication related limitations like quality of deionized water, minor imperfections in fabricated masks, very minor misalignments in lithography, minor localized damage etc. using semiconductor device simulators. These can be the possible reasons why the deviation in anode current value is near 20%. Moreover, it is understood from TCAD simulation experience that a deviation of 10 20% in values between experiment and simulation is fairly standard. Additionally, the hole current flowing through interstrip gaps between p cathodes was found to be 1.4 ma from simulation. 184

11 Table 3. Electrode V/S potential. Sr no Electrode Potential, V 1 Anode 0 2 Cathode-1 (S1) 20 3 Cathode-6 (S6) Guard-ring-1 (G1) 50 5 Guard-ring- 2 (G2) Float 6 Back-cathode 50 Armenian Journal of Physics, 2011, vol. 4, issue 3 Fig D surface potential versus lateral distance for the circular-220 m device. Fig. 10. Anode current versus Cathode-6 voltage. 185

12 Fig. 11. Cathode-6 current versus Cathode-6 voltage. Device Table 4. I-V Simulation results for Circular-220 device. Simulated Anode current Experimental Anode Current Simulated Cathode-6 Current Experimental Cathode-6 Current Circular µa 1.03 µa 1.4 ma 1 ma 5. C-V characterizations and device simulation 5.1. Objectives and measurement methodology The C-V characterization gave an estimate of the total anode (output) capacitance appearing at full depletion in the SDD. SDD essentially is a low output capacitance device and hence presents a higher signal to noise ratio. This low output capacitance coupled with a low anode leakage current improves (increases) the signal to noise ratio of the detector. Hence measurement of this full depletion anode capacitance assumes importance. The anode capacitance has been measured at various frequencies viz. 1 MHz, 500 khz and 100 khz by passing an ac signal of 500 mv strength under a maximum reverse dc bias of 45V applied at the Cathode-1, Cathode-6 and back-cathode connected together w.r.t anode (Figs. 12 and 13). Additionally, capacitance contributions from Cathodes 2, 3, 4 and 5 w.r.t anode were found to be only 6.5% of total full-depletion capacitance contribution from Cathode 1, Cathode 6 and back-cathode w.r.t anode as derived from device simulations. Prior to taking any measurement it was essential to factor out the stray capacitances of cables connected in the setup as the cables act as capacitors in parallel to the SDD in between the node and ground and hence add to the total output (anode) capacitance. The correction was done at the same ac frequency and ac signal voltage as the actual measurement. The total corrected open 186

13 circuit capacitance of the fully connected setup without SDD was measured to be ~5 ff. A C++ program was written and compiled into an executable file to run an automated measurement. This program was designed to assign variable values to frequency, ac signal voltage, impedance mode of operation, and dc applied bias. The dc voltage was ramped from 45 V to 0 V and the anode capacitance was measured at each voltage point. Fig. 12. C-V Characteristics of circular-220 micron pitch device at 3 different frequencies. Fig. 13. Capacitance model in an SDD Results and Discussions The capacitance of the SDD device can be modeled as follows. As shown in Fig. 13, the SDD capacitance is a parallel combination of capacitances of the anode to back-contact (back-cathode) capacitor, the anode to Cathode-1 capacitor and the anode to Cathode-6 capacitor. At zero bias, the capacitance is corresponding to these three separate capacitors with their capacitances adding up to result in a high value of capacitance. At zero bias, the highest contribution to capacitance comes from the back-contact capacitor formed by one plate as the p back contact and second plate as the undepleted n-bulk connected to n anode region. This means that for a large area p back-contact, its 187

14 capacitance contribution at zero bias is the highest as compared to the other capacitors. Consequently the total anode capacitance has the highest value (2 pf) at zero bias (Fig. 12). As the reverse bias is increased, the high resistivity bulk begins to deplete and this leads to depletion of the bulk region between the anode and the Cathode-1. This results in a drop in the capacitance of the Cathode-1 capacitor and the total anode capacitance also drops to a low value (92 ff at 1 MHz) at a cathode bias of 5 V. As the reverse bias is increased further, the anode capacitance will be governed by the depletion region between the anode and the back-contact capacitor. This depletion region will increase uniformly with voltage owing to a uniform doping concentration in the bulk. This leads to a linear drop in capacitance with voltage till the depletion region between the anode and the back-contact completely vanishes. At this point, the capacitance drops indicating a full depletion of the wafer bulk. For any further increase in reverse voltage, the anode capacitance saturates to a value (31 ff), which is governed by the anode area and thickness of fully depleted wafer (300 μm). The measured anode capacitance varied with frequency at biases below full depletion voltage while at full depletion the saturation anode capacitance was nearly invariant of frequency. This is because at full depletion the anode capacitance was only dependent on the anode area and the full depletion thickness of the wafer. The measured full depletion anode capacitance of 31 ff is within range of targeted values of anode capacitance required for X-ray spectroscopy to achieve an energy resolution of the order of < 200 ev Device Simulations The C-V Characteristics for the circular 220 micron SDD device were simulated at a frequency of 1 MHz and an ac signal voltage of 500 mv. Cathodes 1, 6 and back-contact were shorted together and a dc reverse bias was applied w.r.t anode (Case-1). The anode capacitance showed the same behavior as described in the section 5.2 and the value of saturation anode capacitance from simulation was 45 ff for a full depletion cathode voltage of 25V (Fig. 14). Alternatively, the same device was simulated by giving the same potentials to Cathodes 1, 6 and back-contact, but without shorting them together i.e. through separate voltage sources (decoupled capacitances). This simulation gave values of anode capacitance w.r.t Cathode-1, anode capacitance w.r.t back-contact, and anode capacitance w.r.t Cathode-6 (Fig 15). These individual components were plotted and it was found that the sum of the anode capacitance w.r.t Cathode-1 and anode capacitance w.r.t back-contact tallied with the value of 45 ff as in simulation for Case-1. Hence the saturation anode capacitance is proved to be the sum of anode capacitance w.r.t Cathode-1, anode capacitance w.r.t back-contact and anode capacitance w.r.t Cathode-6 (as modeled in section 5.2). The total full depletion anode capacitance derived from simulation was 45 ff, whereas the measured value of anode capacitance was 31 ff (Table 5). This translated into a deviation of 31% in 188

15 values derived from experimental versus those derived from simulation. The main reason behind the measured capacitance values being lesser than simulated ones is the existence of inductances associated with the metal contacts over p + -n junctions in the SDD, which contributed to some extent to the total impedance offered to the small ac signal [8]. Since it was not possible to accurately quantify the values of lead inductances offered by metal regions over the SDD, this feature could not be incorporated in the C-V simulation. Fig. 14. Anode capacitance w.r.t Cathode-1 versus Cathode-1 voltage. Fig. 15. Anode capacitance w.r.t Cathode1 and back-contact versus Cathode-6 voltage. 189

16 Device Simulated Total Anode Capacitance Table 5. C-V simulation results for Circular-220 micron device. Experimental Anode Capacitance Armenian Journal of Physics, 2011, vol. 4, issue 3 Anode Capacitance w.r.t Cathode-1 Anode Capacitance w.r.t Back-contact Full Depletion Voltage Circular ff 31 ff 31 ff 14 ff 20V 6. Mask layout of SDDs to be fabricated at BEL 6.1. Design rules applicable to BEL foundry 1) Minimum contact width equal to 5 microns. 2) Minimum distance of contact from p or n edge equal to 4 microns (from all sides). 3) Minimum metal overlap over contact equal to 3 microns (all sides). 4) Minimum distance of p region edge within n region equal to 4 microns (all sides). 5) Minimum metal-to-metal spacing 6 microns (all sides). 6) Minimum metal width 8 microns Layout of 4-inch wafer The 4-inch silicon wafer is divided into sections dedicated for each type of device (Fig. 16). The central portion of the wafer circumscribed as a square, is the region where the main deliverable devices are located. It contains 49 dies in total with nearly 10 pieces of each design (circular, hexagonal and linear). The rest of the wafer area is dedicated to test devices, which are termed as non-deliverables. These contain SDDs of various geometries with embedded JFETs. In addition there are different kinds of JFETs separately fabricated for individual packaging. There is a SDD imaging array located in the peripheral area. Four point probe and two probe structures for process quality evaluation are also incorporated in addition to test polysilicon resistors. Fig. 16. Mask layout of 4-inch wafer showing all layers. 190

17 6.3. Circular SDD (pitch-120 μm) with embedded JFET Armenian Journal of Physics, 2011, vol. 4, issue 3 This version of SDD comes with an on-chip poly-resistor network for biasing the intermediate p strips together with an on-chip JFET for first level amplification (Fig. 17). The anode being an annular ring of 50 μm radii and area μm 2 that fetches a full depletion capacitance of 27 ff for 300 μm thick fully depleted wafer. The total active area of the detector is μm 2. This particular device has 20 p strips and two guard rings. The first, fifth, tenth, fifteenth, twentieth, and last p strips are individually biased and rest p strips are biased by the on-chip resistor. Each poly resistor was designed to present a resistance of kω (R s = kω/ ). The embedded JFET (named as JFET-10) for this SDD design had the smallest channel length (15 μm) possible with BEL process (Fig. 18). The gate length being 5 μm, gate drain and gate source spacing is 5 μm each and the gate (channel) width is 172 μm which gives a transconductance g m of 2.47 ms. Additionally, the gate area being μm 2 which should fetch a gate to source full depletion capacitance of ff. Fig. 17. Layout of circular SDD (Pitch 120 m) with embedded JFET. Fig. 18. A zoomed view of central region of circular SDD (Pitch 120 m) showing JFET. 191

18 7. Conclusions First prototypes of SDD have been successfully fabricated at IIT-Bombay. Process technology for fabrication of SDDs at IIT-B has been developed employing simulation studies in TCAD. Characterization of SDDs fabricated at IIT-B yielded values of anode current being 1.03 A, a full depletion anode capacitance of 31 ff and a full depletion voltage of 20 Volts. Analytical values for these dc performance parameters have been derived from TCAD device simulations and were found to be having a variation of 20 30% deviation from those achieved by characterization. Mask layout containing various SDD designs to be fabricated at BEL has been completed. Acknowledgements I express a deep sense of gratitude for Late Dr. S. K. Kataria for his guidance and leadership in this project. I would like to especially thank Dr. Srikumar Banerjee for his support, in addition to Mr. P. K. Mukhopadhyay. I am deeply indebted to Dr. Vijay Mishra for his role as a senior and mentor in this field. I am grateful to Prof. Dinesh Sharma, Prof. V. Ramgopal Rao, Prof. Prakash Apte and Prof. S. Mohapatra for the finer insights I got in the fabrication and characterization effort at IIT-Bombay. I am deeply indebted to Mrs. Prashanti Kovur for her kind assistance in carrying out the fabrication effort at IIT-B. Lastly, once again I would like to thank all my friends and colleagues in BARC and IIT-B for all their support. REFERENCES 1. E.Gatti, P.Rehak, Nucl. Instrum. Meth. A, 225, 608 (1984). 2. P.Lechner, C.Fiorini, R.Hartmann, J.Kemmer, et al., Nucl. Instrum. Meth. A, 458, 281 (2001). 3. A.Rashevsky, V.Bonvicini, P.Burger, S.Piano, C.Piemonte, A.Vacchi, Nucl. Instrum. Meth. A, 485, 54 (2002). 4. V.Mishra, P.Mehta, et al, Simulation Studies for the Development of JFET on High Resistivity Detector Grade Silicon, National Symposium on Nuclear Instrumentation 2004, NSNI-2004, India, p P.Mehta, V.Mishra, S.K.Kataria, Indian Journal of Pure and Applied Physics, 43, 705 (2005). 6. V.Mishra, P.Mehta, Simulation Studies for the Integration of p-mosfet with n-jfet on High Resistivity Silicon for Continuous Reset Purpose, National Symposium on Nuclear Instrumentation-2004, (NSNI-2004, India), p K.D.Schroder, Semiconductor Material and Device Characterization, New York: Wiley, K.S.A.Butcher, T.L.Tansley, D.Alexiev, Solid-State Electronics, 39(3), 333 (1996). 192