Deposited on: 19 March 2008 Glasgow eprints Service

Transcription

1 Passlack, M. and Zurcher, P. and Rajagopalan, K. and Droopad, R. and Abrokwah, J. and Tutt, M. and Park, Y-B and Johnson, E. and Hartin, O. and Zlotnicka, A. and Fejes, P. and Hill, R.J.W. and Moran, D.A.J. and Li, X. and Zhou, H. and Macintyre, D. and Thoms, S. and Asenov, A. and Kalna, K. and Thayne, I.G. (27) High mobility Ill- MOSFETs for RF and digital applications. In, IEEE International Electron Devices Meeting (IEDM 27), 1-12 December 27, pages pp , Washington DC, USA. Deposited on: 19 March 28 Glasgow eprints Service

2 High Mobility Ill- MOSFETs For RF and Digital Applications M. Passlack, P. Zurcher, K. Rajagopalan, R. Droopad, J. Abrokwah, M. Tutt, Y.-B. Park, E. Johnson,. Hartin, A. Zlotnicka, and P. Fejes Freescale Semiconductor, Inc., 21 East Elliot Road, Tempe, AZ USA R.J.W. Hill, D.A.J. Moran, X. Li, H. Zhou, D. Macintyre, S. Thoms, A. Asenov, K. Kalna, and I.G. Thayne Nanoelectronics Research Centre, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow, G12 8LT UK Abstract Developments over the last 15 years in the areas of materials and devices have finally delivered competitive Ill- MOS- FETs with high mobility channels. This paper briefly reviews the above developments, discusses properties of the GdGaO/ Ga2O3 MOS systems, presents GaAs MOSFET DC and RF data, and concludes with an outlook for high indium content channel MOSFETs. GaAs based MOSFETs are potentially suitable for RF power amplification, switching, and front-end integration in mobile and wireless applications while MOS- FETs with high indium content channels are of interest for future CMOS applications. Introduction Novel device architectures, high-k gate dielectrics, metal gates, and high mobility channel materials will be required to continue CMOS device scaling according to Moore's Law and the International Technology Roadmap for Semiconductors (1). In the shorter term, high mobility GaAs MOSFET development will likely be more driven by RF applications. Developments over the last 15 years including the discovery of the device quality, MBE (molecular beam epitaxy) grown Ga2O3/ GaAs interface in 1996 (2), the concept of bilayer dielectric stacks in 1995 (3), the proposal of heterostructure use to mitigate high band-edge interface-state density in 1997 (4), the realization of bilayer GdGaO/Ga2O3 dielectric stacks on GaAs in 1999 (5), the concept/fabrication of implant-free enhancement-mode high-mobility MOSFETs in 2/25 (6), (7), and the realization of low R, Ohmic contacts in 26 (8) have finally delivered competitive GaAs MOSFETs with effective channel mobilities exceeding 5,5 cm2/s. Electron Hall mobilities of 12, cm2/s have been measured in InP based MOSFET structures with In 75Ga.25As channel layers (9). This paper discusses oxide/gaas interface properties, presents GaAs MOSFET DC and RF data, and concludes with an outlook for high indium content channels for future CMOS applications. Wafer Manufacturing MOSFET wafers have been fabricated by MBE using an ultrahigh vacuum (UH) dual chamber configuration manufactured by DCA Instruments. Fig. 1 shows a dark field TEM micrograph of a typical GaAs MOSFET layer structure with an Ino3Ga7As channel. Further fabrication details can be found in (1). Results and Discussion A. Oxide-GaAs Interface Properties Electrical interface properties of Ga2O3 films and GdGaO/ Ga2O3 dielectric stacks have been determined by a photoluminescence-intensity (PL-I) technique and by capacitance-voltage measurements. All investigated materials (Si, AlN, In23, SiOx, MgO, AlxOy, TixO, TaxO, MoXO, ZrxO, Gd2O3, LaAlO3,, 2) show essentially native oxide behavior on GaAs (group of high-interface defectivity films) except for Ga2O3 which provides a device quality interface (Fig. 2). Typical quasi-static and high-frequency (1 MHz) C- curves of the dielectric stack deposited on a MOSFET-like epitaxial structure of Fig. 1 are shown in Fig. 3. Fig. 1 Dark field TEM micrograph of a typical MOSFET structure with an InGaAs channel. The inset shows a high resolution TEM micrograph of the oxide/semiconductor interface X/7/$25. c 27 IEEE 621

3 C ct to3 Fr 1o L 1-2 1o 1 1l 12 to3 Laser Excitation Intensity (W/cm2) Fig. 2 Normalized GaAs photoluminescence (PL) intensity as a function of excitation intensity for AlGaAs (solid circles), bulk Ga2O3 (open triangles), GdGaO/Ga2O3 (solid squares), high interface defectivity films, and native oxide (solid circles) on GaAs. All materials are deposited on MBE grown surfaces under UH conditions (except for native oxide). 15 m 1 5 MBE Grown GaAs Surface - ~~AlGaAs, ; - Hpassivated./ \ BulkAk As-Dep. Ga2O'-3 - GdGaO/Ga2O3' z.5 oltage () Fig. 3 Quasi-static and 1 MHz C- curves of the GaAs based MOSFET structure shown in Fig. 1. The midgap interface state density for the dielectric stack with K = 2 is determined to be _ 2.5x111 cm-2 e1. B. GaAs MOSFET DC and RF Data A- ^Az~ High interface Oxi A, Nadetectivity 4- ~~~Native Oxide Enhancement-mode 1 tm n-channel GaAs MOSFETs with metal gate (Pt) and a 1 nm high-k dielectric GdGaO/Ga2O3 (K = 2) have been manufactured based on the implant-free device architecture proposed in (6). A two-level wrap-around gate design (where the gate encircles the drain) was used to simplify the device process flow, removing the need for isolation (see Fig. 4). With typical figures of merit including threshold voltage, t = +.26, peak transconductance, gm,max = 477 ms/mm, on-resistance, Ron = 1.9 Q mm, saturation drive current, ID,sat = 47 ma/mm, gate leakage current, 19 < 6 pa, output conductance, gd 11 ms/mm, and subthreshold swing, S = 1 m/dec (Fig. 5, Fig. 6), our GaAs Fig. 4 Optical micrograph and SEM image of a 1,um gate length GaAs MOS- FET with wrap-around gate design. The source-drain distance is 2.7,um. 5 GaAs Enhancement Mode MOSFET G () = 4 -LG= 1 tm k _2. t n _D,sat 47 = ma/mm.ic =- 2 ~~~~~~~1.5 3 Ig9< 6 pa /,, 1 k 2 k = /~~~~g I I MSmm 1. 1 L //Ron = 1-9 Q mm. Le.( Drain oltage D () Fig. 5 Output characteristics of a 1,um GaAs MOSFET. lo3 I -l1 A I(I U I1 rn GaAs Enhancement- 2 Mode MOSFET 5 E lo1 D 1 / t.26 X 4 i 15 lo- ln i ~~~~~~~~~~~~~~~~~~~t Gate oltage G () Fig. 6 Transfer characteristics of a 1,um GaAs MOSFET. Ion/loff ratio and drain- 6.3x14 (Ioff, G=, D= 2 ) (Ion, G= 2, D = 2 ) induced barrier lowering, DIBL _. z~~~~~~~~~~~~~~.8 - O Zm,max= /m/e/ 477 msimm log / lnear *~~~~~~D ct Ioo;- enhancement-mode MOSFETs perform as predicted by 2- dimensional device simulation. In contrast, GaAs enhancement-mode devices published by other groups over the last 4 years had typical gm of less than 1 ms/mm with some recent marginal improvement into the 1-2 ms/mm range (11), (12). The peak effective channel electron mobility 622

4 N m b5 4 u 3 X 2 *,, 1 c 4ul..5 O4 G4teoltage1(~J) 2. f ) Sheet Carrier Concentration (cm-2) Fig. 7 Effective channel electron mobility as a function of sheet carrier density. The inset shows measured and simulated capacitance as a function of gate voltage U rs GaAs Enhancement Mode MOSFET LG 2 gm o8x17-6x17 1 Frequency (GHz) Simulated ~Measured. n 1x1 A 2x1 Split C Method Fig. 8 Current gain h2l and maximum available gain MAG for a.8,tm GaAs enhancement-mode MOSFET (W = 2x1,tm). ft and fmax are 13 and 42 GHz, respectively. is _ 5,5 cm2/s (Fig. 7) as measured by an advanced split- C method (13). The gate and ohmic modules employed in the wrap-around gate design have been integrated into a flow for coplanar devices using oxygen implantation for device isolation. A first run has resulted in enhancement-mode devices (t =_ +.4 ) with reduced DC performance of gm = ms/mm, Ron = 7-1 Q mm, and ID,sat = 175 ma/mm. Small-signal parameters have been measured (Fig. 8) and average ft and fmax of 13 GHz and 37 GHz (LG = 1 im), and of 14 GHz and 4 GHz (LG =.8 gim), respectively, have been obtained (2xlO, 2x2, 2x3 tm width). Preliminary on-wafer load-pull measurements at f= 9 MHz tuned for maximum power in class AB operation, provided Pout = 12.4 dbm with a corresponding gain of 11.3 db and a power added efficiency of cc 'N 1-lo, 1-1 cn o vu t u t 1i-1 U 17~.Q) o 1 1o 12 lo, 14 lo, 16 Frequency (Hz) Fig. 9 Current noise spectral density vs. frequency with log-log scale with gate voltage bias point as a parameter for a.8,um GaAs enhancement-mode MOSFET (W = 2x2,tm) k 5 k li.8 gtm GaAs Enhancement- G Mode MOSFET Pulse Width 2 AS -' Pulse Period 1ms 1 2 Drain oltage D () 3 Fig. 1 DC (solid lines) and pulsed (dashed lines) I- data of a.8,tm GaAs enhancement-mode MOSFET (W = 2x1 tim). The quiescent point for pulsed I- is D = 3 and 1% ID sat (G.6 ). 45.6% (2x3 gim). Low frequency noise results are indicative of 1/f noise behavior with flicker noise typical of Si based MOSFETs (Fig. 9). Preliminary pulsed I- measurements show small dispersion, with maximum dispersion occurring in the linear region at small D and in the threshold region (Fig. 1). C. Towards CMOS /- // -- ~~1.15 /- - ffi _-.61 Preliminary lateral scaling data for.3 < LG < 1 gm GaAs enhancement-mode MOSFETs with Ino 3Ga7As channels are shown in Fig. 11. To predict the performance of aggressively scaled Ill- MOSFETs, we have used a finite element Monte- Carlo device simulator (14) verified against experimental data (sheet carrier density and mobility). As shown in Fig. 12, sub- 2 nm gate length MOSFETs with Ino3Ga7As channels could reach peak drive currents of around 1 ta/gm at.8 623

5 .-)r >.25 't.2 7 E 6 v: 5 a flow produced an average ft and fmax of 13 GHz and 37 GHz 1 (LG Am), and of 14 GHz and 4 GHz (LG.8 gim). References o.15 ;.1 O.O5 (n (nnl J.JUU Gate Length (girn) 1. Fig. Threshold voltage and intrinsic transconductance.5, and.3,um GaAs MOSFET with an oxide thickness I cal layer structure was not scaled. Source-drain.3 and.5,um, and 2.7,um L 3 2 r 1 In75Ga25AsIFFET, Spacer=- n In75Ga25AsIFFET, Spacer=2 n IFEET, Spacer=4 n In.75Ga.2,As In3Ga 7AsIFFET, Spacer=2 nrr 4 nm high-k FinFET ID=31 1 ga/itm = D,,#%- t~~~~ m-m M GaAs Enhancement-Mode MOSFET InO75GaO25As IFFET, Spacer=1 n I..5 G I] Fig. 12 Comparison of Monte-Carlo simulation with different sidewall spacer sizes with a fabricated (supply voltage at the ITRS 22 nm node). supply voltages, outperforming the leading technologies (15). Moving to an In 75Ga; potentially improves the drive current in excess tm (thecurrent ITRS 22 un technology generat a device quality interface. tm GaAs enhan MOSFETs employing GdGaO/Ga2O3 dielectri( cstacks been manufactured with t, ID,sat, gm,max, Ron,.26, 47 ma/mm, 477 ms/mm, 1.9 Q mm, mmdec, and < 6 pa, respectively. An off-sta voltage of 18 was obtained for an oxide thickr iess of 18 An effective channel mobility 555 of cm2/ 's sured using the split C- method. A first cop 1- Li --A (1) International Technology Roadmap Semiconductors. (26). [Online]. Available: UpdateFinal.htm O. (2) M. Passlack, R.N. Legge, D. "Opti- 2 cal measurement system for characterizing EH interface and surface states," Trans. Instrum. Meas., vol. 47, no * pp , *_, (3) M. Passlack, "Method of forming a structure," 2 5,665,658, issued 9/9/ (4) M. Passlack, J. Abrokwah, Z. Yu, "Insulator-compound semiconductor interface structure" US Patent 6,359,294, 3/19/2. (5) M. Passlack, "Methodology for Development gate lengtheof 1, Dielectrics on Ill- Semiconductors," in Materials Fundamentals of 1nm. The verti- Gate Dielectrics," edited by A.A. Demkov and.7,um A. Navrotsky, Springer for LG erlag, 25, (6) M. Passlack,. Hartin, M. Ray, N. Medendorp, "Enhancement metal-oxide-semiconductor field effect transistor," issued 11/8/5. im (7) M. Passlack, K. Rajagopalan, J..O Abrokwah, and Droopad, "Implant- Free, High Mobility Flatband MOSFET: Principles of Operation," IEEE Trans. Electron. Dev., vol. ED-53, 1, pp , 26. (8) R.J.W. Hill et al., "Enhancement-mode GaAs MOSFETs with In 3Ga 7As channel, mobility over 475 (9) R. Droopad, K. Rajagopalan,,uS/,um," IEEE Electron. Dev. Lett., cm2s + lack, "Ino 25As Channel Layers Record Mobility Exceeding.+ ; 12, cm2/s for Use in High-K Dielectric NMOSFETs," Electronics, vol. Solid State t-- (1)R. Droopad, J. Abrokwah, K. Rajagopalan, Uebelhoer, and M. Passlack, "Development GaAs-based 1. using Molecular Beam Epitaxy," J , 27. (II)M. Tametou, M. Takebe, K. Nakamura, N.C. - MOSFETs Takamiya, "Improved Transconductance N-Channel Enhancement/Inver- at D.8 FINF sion qet Mode GaAs-MISFETs Oxi-Nitridation," Proc. 24 International Conference Indium Phosphide and Related Materials, pp Si FINFET (12)P. Fay, X. Li, Y Cao, J. Zhang, Kosel, and D.C. Hall, "Ill- MOS- FETs with Native Oxide Gate Dielectrics," Proc. 27 MANTECI, pp. 25As channel of 27 ta/ (13)W. Zhu W, J.-P. Han, andt.p. "Mobility "ion target). tion mechanism of MOSFETs high-k dielectrics," IEEE Trans. Electron Devices, vol. 51, no. 1, Summary (14)K. Kalna et al., "Monte Carlo simulations free In 3Ga 7As nano-mosfets for low-power All investigated materials on GaAs were found o show essen- IEEE Trans. Nanotechnol. vol , tially native oxide behavior except for Ga2O3,hich W provides (15)J. Kavalieros et al., "Tni-Gate Transistor Architecture with High-k Gate nt-m ode Tech Dig., nave 5, and of / mm, 1 te breakdown un. was mealnanar process Dielectrics, Metal Gates and Strain Engineering," Acknowledgment The authors would like to thank N. England and D. for MBE wafer growth, L. Adams for wafer processing, Kaufmann and H. Stewart for electrical device measurements, and the Physical Analysis Laboratories for analysis Finally, the authors would like to thank K. Johnson Miller for their support. 624