Biploar transistor: and the collector. regions are. called emitter. properties. very thin, it. intermediate. of the base. light doping.

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1 1) Transistors: Transistor operation Biploar transistor: A transistor is basically a Si on Ge crystal containing three separatee regions. It can be either NPNN or PNP type fig. 1. The middle region is called the base and the outer two regions are called emitter and the collector. The outer layers althoughh they are of same type but their functions cannot be changed. They have different physical and electrical properties. In most transistors, emitter is heavily doped. Its job is to emit or inject electrons into the base. These bases are lightly doped and very thin, it passes most of the emitter- collector. The doping level of collector is intermediate injected electrons on to the between the heavy doping of emitter and the light doping of the base. The collector is so named because it collects electrons from base. The collector is the largest of the three regions; it must dissipate more heat than the emitter or base. The transistor has two junctions. One between emitter and the base and other between the base and the collector. Because of this the transistor is similar to two diodes, one emitter diode and other collector base diode. Fig.1 When transistor is made, the diffusion of free electrons across the junction produces two depletion layers. For each of these depletion layers, the barrier potential is 0.7 V for Si transistor and 0.3 V for Ge transistor. The depletion layers do not have the same width, because different regions have different doping levels. The more heavily doped a region is, the greater the concentration of ions near the junction. This means the depletion layer penetrates more deeply into the base and slightly into emitter. Similarly, it penetration more into collector. The thickness of collector depletion layer is large while the base depletionn layer is smalll as shown in fig. 2. Fig. 2 If both the junctions j are forward biased using two d.c sources, as shown in fig. 3a. free electrons (majority carriers) enter the emitter and collector of the transistor, joins at the base and come out of the base. Because both the diodes

2 are forward biased, the emitter and collector currents are large. Fig. 3a Fig. 3b If both the junction j are reverse biased as shown in fig. 3b, then small currents flows through both junctions only due to thermally produced minority carriers and surface leakage. Thermally produced carriers are temperature dependent it approximately doubles for every 10 degree celsius rise in ambient temperature. The surface leakage current increases with voltage. When the emitter diode is forward biased and collector diode is reverse biased as shown in fig. 4 then one expect large emitter current and small collector current but collector current is almost as large as emitter current. Fig. 4 When emitter diodes forward biased and the applied voltage is more than 0.7 V (barrier potential) then larger number of majority carriers (electrons in n-type) diffuse across the junction. Once the electrons are injected by the emitter enter into the base, they become minority carriers. These electrons do not have separate identities from those, which are thermally generated, in the base region itself. The base is made very thin and is very lightly doped. Because of this only few electronss traveling from the emitter to base region recombine with holes. This gives rise to recombinationn current. The rest of the electrons exist for more time. Since the collector diode is reverse biased, (n is connected to positive supply) therefore mostt of the electrons are pushed into collector layer. These collector elections can then flow into the external collector lead. Thus, theree is a steady stream of electrons leaving the negative source terminal and entering the emitter region. The V EB forward bias forces these emitter electrons to enter the base region. The thin and lightly doped base gives almost all those electrons enough lifetime to diffuse into the depletion layer. The depletion layer field pushes a steady stream of electron into the collector region. These electrons leave the collector and flow into the positive terminal of the voltage source. In most transistor, more than 95% of the emitter injected electrons flow to the collector, less than 5% fall into base holes and flow out the external base lead. But the collector current is less than emitter current. Relation between different currents in a transistor: The total current flowing into the transistor must be equal to the total current flowing out of it. Hence, the emitter

3 current I E is equal to the sum of the collector (I C ) and base current (IB). That is, I E = I C + I B The currents directions are positive directions. The total collector current I C is made up of two components. 1. The fraction of emitter (electron) current which reaches the collector ( dc I E ) 2. The normal reverse leakage current I CO dc is known as large signal current gain or dc alpha. It is always positive. Since collector current is almost equal to the I E therefore αdc I E varies from 0.9 to Usually, the reverse leakage current is very small compared to the total collector current. NOTE: The forward bias on the emitter diode controls the number of f free electrons infected into the base. The larger (V BE ) forward voltage, the greater the number of injected electrons. The reverse bias on the collector diode has little influence on the number of electrons that enter the collector. Increasing V CB does not change the number of freee electrons arriving at the collector junction layer. The symbol of npn and pnp transistors are shown in fig. 5. Fig. 5 Breakdown Voltages: Since the two halves of a transistor are diodes, two much reverse voltage on eitherr diode can cause breakdown. The breakdown voltage depends on the width of the depletion layer and the doping levels. Because of the heavy doping level, the emitter diode has a low breakdown voltage approximately 5 to 30 V. The collector diode is less heavily doped so its breakdown voltage is higher around 20 to 300 V.

4 Configurations: M- Bipolar junction transistors Common Base Amplifier: The common base amplifier circuit is shown in Fig. 1. The V EE source forward biases the emitter diode and V CC source reverse biased collector diode. The ac source v in is connected to emitter through a coupling capacitor so that it blocks dc. This ac voltage produces small fluctuation in currents and voltages. The load resistance R L is also connected to collector through coupling capacitor so the fluctuation in collector base voltage will be observed across R L. The dc equivalent circuit is obtained by reducing all ac sources to zero and opening all capacitors. The dc collector current is same as IE and V CB is given by V CB = V CC - I C R C. Fig. 1 These current and voltage fix the Q point. The ac equivalent circuit iss obtained by reducing all dc sources to zero and shorting all coupling capacitors. r' e represents the ac resistance of the diode as shown in Fig. 2. Fig. 2 Fig. 3, shows the diode curve relating IE and V BE. In the absence of ac signal, the transistor operates at Q point (point of intersection of load line and input characteristic). When the ac signal is applied, the emitter current and voltage also change. If the signal is small, the operating point swings sinusoidally y about Q point (A to B).

5 Fig.3 If the ac signal is small, the points A and B are close to Q, and arc A B can be approximated by a straight line and diode appears to be a resistance given by If the input signal is small, input voltage and current will be sinusoidal but if the input voltage is large then current will no longer be sinusoidal because of the non linearity of diode curve. The emitter current is elongated on the positive half cycle and compressed on negative half cycle. Therefore the output will also be distorted. r' e is the ratio of ΔV BE and Δ I E and its value depends upon the location of Q. Higher up the Q point small will be the value of r' e because the same change in V BE produces large changee in I E. The slope of the curve at Q determines the value of r' e. From calculation it can be proved that. r' e = 25mV / I E

6 Proof In general, the current through a diode is given by Where q is he charge on electron, V is the drop acrosss diode, T is thee temperature and K is a constant. On differentiating w.r.t V, we get, The value of (q / KT) at 25 C is approximately 40. Therefore, or, To a close approximation the small changes in collector current equal the small changes in emitter current. In the ac equivalent circuit, the current i C ' is shown upward because if i e ' increases, then i C ' also increasess in the same direction. In general, the current through a diode is given by Where q is he charge on electron, V is the drop acrosss diode, T is thee temperature and K is a constant. On differentiating w.r.t V, we get, The value of (q / KT) at 25 C is approximately 40.

7 Therefore, or, To a close approximation the small changes in collector current equal the small changes in emitter current. In the ac equivalent circuit, the current i C ' is shown upward because if i e ' increases, then i C ' also increasess in the same direction. Voltage gain: Since the ac input voltage source is connected across r' e. Therefore, the ac emitterr current is given by i e = V in / r' e or, V in = ie r' e The outputt voltage is given by V out = i c ( R C R L ) Under open circuit condition v out = i c R c Example-1 Find the voltage gain and output of the amplifier shown in fig. 4, if input voltage is 1.5mV.

8 Fig. 4 Solution: The emitter dc current I E is given by Therefore, emitter ac resistance = or, A V = 56.6 and, V out = 1.5 x 56.6 = 84.9 mv Example-2 Repeat example-1 if ac source has resistance R s = 100 W. Solution: The ac equivalent circuit with ac source resistance is shown in fig. 5. Fig. 5

9 The emitter ac current is given by or, Therefore, voltage gain of the amplifier = and, V out = 1.5 x 8.71 =13.1 mv Common Emitter Curves: The common emitter configuration of BJT is shown in fig. 1. Fig. 1 In C.E. configuration the emitter is made common to the input and output. It is also referred to as grounded emitter configuration. It is most commonly used configuration. In this, base current and output voltages are taken as impendent parameters and input voltage and output current as dependent parameters V BE = f 1 ( IB, B V CE ) I C = f 2 ( I B, V CE ) Input Characteristic: The curve between I B and V BE for different values of VCE are shown in fig. 2. Since the base emitter junction of a transistor is a diode, therefore the characteristic is similar to diode one. With higherr values of V CE collector gathers slightly more electrons and therefore base current reduces. Normallyy this effect is neglected. (Early effect). When

10 collector is shorted with emitter then the input characteristic is the characteristic of a forward biased diode when V BE is zero and IB is also zero. Fig. 2 Output Characteristic: The outputt characteristic is the curve between V CE and I C for various values of I B. For fixed value of I B and is shown in fig. 3. For fixed value of I B, I C is not varying much dependent on V C CE but slopes are greater than CE characteristic. The outputt characteristicss can again be divided into three parts. Fig. 3 (1) Active Region: In this region collector junction is reverse biased and emitter junctionn is forward biased. It is the area to the right of V CE = 0.5 V and above I B = 0. In this region transistor current responds most sensitively to I B. If transistor is to be used as an amplifier, it must operate in this region.

11 If dc is truly constant then I C would be independent of V CE. But because of early effect, dc increases by 0.1% (0.001) e.g. from to as V CE increases from a few volts to 10V. Then dc increases from / ( ) = 200 to / ( ) = 250 or about 25%. This shows thatt small change in reflects large change in. Therefore the curves are subjected to large variations for the same type of transistors. (2) Cut Off: Cut off in a transistor is given by I B = 0, I C = I CO. A transistor is not at cut off if the base current is simply reduced to zero (open circuited) under this condition, I C = I E = I CO / ( 1-α dc ) = I CEO The actual collector current with base open is designated as I CEO. Since even in the neighborhood of cut off, dc may be as large as 0.9 for Ge, then I C =10 I CO O(approximately), at zero base current. Accordingly in order to cut off transistor it is not enough to reducee I B to zero, but it is necessary to reverse bias the emitter junction slightly. It is found that reverse voltage of 0.1 V is sufficient for cut off a transistor. In Si, the dc is very nearly equal to zero, therefore, I C = I CO. Hence even with I B = 0, I C = I E = I CO so that transistor is very close to cut off. In summary, cut off means I E = 0, I C = ICO, I B = -I C = -ICO, and V BE is a reverse voltage whose magnitude is of the order of 0.1 V for Ge and 0 V for Si. Reverse Collector Saturation Current I CBO : When in a physical transistor emitter current is reduced to zero, then the collector current is known as I CBO (approximately equal to I CO ). Reverse collector saturation current I CBO also varies with temperature, avalanche multiplication and variability from sample to sample. Consider the circuit shown in fig. 4. V BB is the reverse voltage applied to reduce the emitter current to zero. I E = 0, I B = -I CBO If we require, V BE = V Then - V BB B + I CBO R B < V

12 Fig. 4 If R B = 1000 K, I CBO = 100 m A, Then V BB B must be 10.1 Volts. Hence transistor must be capable to withstand this reverse voltage before breakdown voltage exceeds. (3).Saturation Region: In this region both the diodes are forward biased by at least cut in voltage. Since the voltage V BE and V BC acrosss a forward is approximately 0.7 V therefore, V CE = V CB + V BE = - V BC + V BE is also few tenths of volts. Hence saturation region is very close to zero voltage axis, where all the current rapidlyy reduces to zero. In this region the transistor collector current is approximately given by V CC / R C and independent of base current. Normal transistor action is last and it acts like a small ohmic resistance. Large Signal Current Gain β dc :- The ratio Ic / I B is defined as transfer ratio or large signal current gainn dc Where I C is the collector current and I B is the base current. The dc iss an indication if how well the transistor works. The typical value of dc varies from 50 to 300. In terms of h parameters, dc is known as dc current gain and in designated h fe ( dc = h fe ). Knowing the maximum collector current and dc the minimum base current can be found which will be needed to saturate the transistor. This expression of dc is defined neglecting reverse leakage current (I CO ). Taking reverse leakage current (I CO ) into account, the expression for r the dc can be obtained as follows:

13 dc in terms of dc is given by Since, I CO = I CBO Cut off of a transistor means I E = 0, then I C = I CBO and IB = - I CBO. Therefore, the above expression dc gives the collector current increment to the base current change form cut off too I B and hence it represents the large signal current gain of all common emitter transistor. Small signal analysis of basic transistor amplifier Small Signal CE Amplifiers: CE amplifiers are very popular to amplify the small signal ac. After a transistor has been biased with a Q point near the middle of a dc load line, ac source can be coupled to the base. This produces fluctuations in the base current and hence in the collector current of the same shape and frequency. Thee output will be enlarged sine wave of same frequency. The amplifier is called linear if it does not change the wave shape of the signal. As long as the input signal is small, the transistor will use only a small part of the load line and the operation will be linear. On the other hand, if the input signal is too large. The fluctuations along the load line will drive the transistor into either saturation or cut off. This clips the peaks of the input and the amplifier is no longer linear. The CE amplifier configuration is shown in fig. 1.

14 Fig. 1 The coupling capacitor (C C ) passes an ac signal from one point to another. At the same time it does not allow the dc to pass through it. Hence it is also called blocking capacitor. Fig. 2 For example in fig. 2, the ac voltage at point A is transmitted to pointt B. For this series reactance X C should be very small compared to series resistance R S. The circuit to the left of A may be a source and a series resistor or may be the Thevenin equivalent of a complex circuit. Similarly R L may be thee load resistance or equivalent resistance of a complex network. The current in the loop is given by As frequency increases, decreases, and current increases until it reaches to its maximum value v in / R. Therefore the capacitor couples the signal properly from A to B whenn X C << R. The size of the coupling capacitor depends upon the lowest frequency to be coupled. Normally, for lowest frequency X C 0.1R is taken as design rule. The coupling capacitor acts like a switch, which is open to dc and shorted for ac. The bypasss capacitor C b is similar to a coupling capacitor, except that it couples an ungrounded point to a grounded

15 point. The C b capacitor looks like a short to an ac signal and therefore emitter is said ac grounded. A bypass capacitor does not disturb the dc voltage at emitter because it looks open to dc current. As a design rule X Cb 0.1RE at lowest frequency. Analysis of CE amplifier: In a transistor amplifier, the dc source sets up quiescent current and voltages. The ac source then produces fluctuations in these current and voltages. The simplest way to analyze this circuit is to split the analysis in two parts: dc analysiss and ac analysis. One can use superposition theorem for analysis. AC & DC Equivalent Circuits: For dc equivalent circuit, reduce all ac voltage sourcess to zero and open all ac current sources and open all capacitors. With this reduced circuit shown in fig. 3 dc current and voltages can be calculated. Fig. 3 For ac equivalent circuits reduce dc voltage sources to zero and open current sources and short all capacitors. This circuit is used to calculate ac currents and voltage as shown in fig. 4. Fig. 4 The total current in any branch is the sum of dc and ac currents through that branch. The total voltage across any branch is the sum of the dc voltage and ac voltage across that branch.

16 Phase Inversion: Because of the fluctuation is base current; collector current and collector voltage also swings above and below the quiescent voltage. The ac output voltage is inverted with respect to the ac input voltage, meaning it is 180 o out of phase with input. During the positive half cycle base current increase, causing the collector current to increase. This produces a large voltage drop across the collector resistor; therefore, the voltage output decreases and negative half cycle of output voltage is obtained. Conversely, on the negative half cycle of input voltage less collector current flows and the voltage drop across the collector resistor decreases, and hence collector voltage increasess we get the positive half cycle of output voltage as shown in fig. 5. Fig. 5 Stabilization Stability of Operating Point Let us consider three operating points of transistor operating in common emitter amplifier. 1. Near cut off 2. Near saturation 3. In the middle of active region If the operating point is selected near the cutoff region, the output is clipped in negative half cycle as shown in fig. 1.

17 Fig. 1 If the operating point is selected near saturation region, then the output is clipped in positive cycle as shown in fig. 2. Fig. 2 Fig. 3 If the operating point is selected in the middle of active region, then there is no clipping and the output follows input faithfully as shown in fig. 3. If input is large then clipping at both sides will take place. The first circuit for biasing the transistor is CE configuration is fixed bias. In biasing circuit shown in fig. 4(a), two different power supplies are required. To avoid the use of two supplies the base resistance R B is connected to V CC as shown in fig. 4(b).

18 Fig. 4(a) Fig. 4(b) Now V CC is still forward biasing emitter diode. In this circuit Q point iss very unstable. The base resistance R B is selected by noting the required base current I B for operating point Q. I B = (V CC V BE ) / R B Voltage across base emitter junction is approximately 0.7 V. Since V CC is usually very high i.e. I B = V CC C/ R B Since I B is constant therefore it is called fixed bias circuit. Stability of quiescent operating point: Let us assume that the transistor is replaced by an other transistor off same type. The dc of the two transistors of same type may not be same. Therefore, if dc increases then for same I B, output characteristic shifts upward. If dc decreases, the output characteristic shifts downward. Since I B is maintained constant, therefore the operating point shiftss from Q to Q 1 as shown in fig. 5. The new operating point may be completely unsatisfactory. Therefore, to maintain operating point stable, I B should be allowed too change so ass to maintain V CE & I C constant as dc changes. Fig. 5

19 A second cause for bias instability i is a variation in temperature. The reverse saturation current changes with temperature. Specifically, I CO doubles for every 10 o C rise in temperature. The collector current I C causes the collector junction temperature to rise, which in turn increases ICO. As a result of this growth ICO, I C will increase ( dc I B + (1+ dc ) ICO ) and so on. It may be possible that this process goes on and the ratings of the transistors are exceeded. This increase in I C changes the characteristic and hence the operating point. Stability Factor: The operating point can be made stable by keeping I C and V CE constant. There are two techniques to make Q point stable. 1. stabilization techniques 2. compensation techniques In first, resistor biasing circuits are used which allow IB to vary so as to keep I C relatively constant with variations in dc, I CO and V BE. In second, temperature sensitive devices such as diodes, transistorss are used which provide compensating voltages and currents to maintain the operating point constant. To compare different biasing circuits, stability factor S is defined as the rate of change of collector current with respect to the I CO, keeping dc and V CE constant S = I C / I CO If S is large, then circuit is thermally instable. S cannot be less than unity. The other stability factors are, I C / dc and I C / V BE. The bias circuit, which provide stability with I CO, also show stability even if and V BE changes. I C = dc IB + (I + dc ) I C CO Differentiating with respect to I C, In fixed bias circuit, I B & IC are independent. Thereforee and S = 1 + dc. If dc =100, S = 101, which means I C increasess 101 times as fast as I CO. Such a large change definitely operate the transistor in saturation.

20 Essentials of a biasing network Emitter Feedback Bias: Fig. 1, shows the emitter feedback bias circuit. In this circuit, the voltage across resistor R E is used to offset the changes in dc. If dc increases, the collector current increases. Thiss increases the emitter voltage which decrease the voltage across base resistor and reduces base current. The reduced base current result in less collector current, which partially offsets the original increase in dc. The feedback term is used because output current ( I C ) produces a change in input i current ( I B ). R E is common in input and output circuits. In this case Fig. 1 Since I E = I C + I B Therefore, In this case, S is less compared to fixed bias circuit. Thus the stabilityty of the Q point is better. Further,

21 If I C is to be made insensitive to β dc than R E cannot be made large enough to swamp out the effects of β dc without saturating the transistor. Collector Feedback Bias: In this case, the base resistor is returned back to collector as shown in fig. 2. If temperature increases. β dc increases. This produces more collectors current. As I C increases, collector emitter voltage decreases. It means less voltage across R B and causes a decrease in base current this decreasing I C, and compensating the effect of dc. Fig. 2 In this circuit, the voltage equation is given by Circuit is stiff sensitive to changes in β dc c. The advantage is only two resistors are used. Then, Therefore,

22 It is better as compared to fixed bias circuit. Further, Circuit is still sensitive to changes in β dc c. The advantage is only two resistors are used. Voltage Divider Bias: If the load resistance R C is i very small, e.g. in a transformer coupled circuit, then there is no improvement in stabilization in the collector to base bias circuit over fixed bias circuit. A circuit which can be used even if there is no dc resistance in series with the collector, is the voltage divider bias or self bias. fig.. 3. The current in the resistance R E in the emitter lead causes a voltage drop which is in the direction to reverse bias the emitter junction. Since this junction must be forward biased, the basee voltage is obtained from the supply through R 1, R 2 network. If R b = R 1 R 2 equivalent resistance is very very small, then V BE voltage is independent of I CO and IC / I CO 0. For best stability R 1 & R 2 must be kept small. Fig. 3 If I C tends to increase, because of I CO, then the current in R C increases, hence base current is decreased because of more reverse biasing and it reduces I C. To analysiss this circuit, the base circuit is replaced by its thevenin's equivalent as shown in fig. 4.

23 Fig. 4 Thevenin's voltage is R b is the effective resistance seen back from the base terminal. If V BE is considered to be independent of I C, then The smaller the value of R b, the better is the stabilization but S cannot be reduced be unity. Hence I C always increases more than ICO. If R b is reduced, then current drawn from the supply increases. Also if R E is increased then to operatee at same Q-point, the magnitude of V CC must be increased. In both the cases the power loss increased and reduced. In order to avoid the loss of ac signal because of the feedback caused by R E, this resistance is often by passed by a

24 large capacitance (> 10 F) so that its reactance at the frequency under consideration is very small. Emitter Bias: Fig. 5, shown the emitter bias circuit. The circuit gets this name because the negative supply V EE is used to forward bias the emitter junction through resistor R E. V CC still reverse biases collector junction. This also gives the same stability as voltage divider circuit but it is used only if split supply is available. Fig. 5 In this circuit, the voltage equation is given by Lecture - 17: Biasing Techniques Example-1 Determine the Q-point for the CE amplifier given in fig. 1, if R1 = 1.5KK W and Rs = 7K W. A 2N3904 transistor is

25 used with β = 180, RE = 100W and RC = Rload = 1K W. Also determine the Pout(ac) and the dc power delivered to the circuit by the source. Fig. 1 Solution: We first obtain the Thevenin equivalent. and Note that this is not a desirable Q-point location since VBB is very close to VBE. Variation in VBE therefore significantly change IC.We find Rac = RC Rload= 500 W and Rdc = RC + RE =1..1KW. The value of VCErepresenting the quiescent value associated with ICQ is found as follows, Then Since the Q-point is on the lower half of the ac load line, the maximum possible symmetrical output voltage swing is

26 The ac power output can be calculated as The power drawn from the dc source is given by The power loss in the transistor is given by The Q-point in this example is not in the middle of the load line so that output swing is not as great as possible. However, if the input signal is small and maximum output is not required, a small IC can be used to reduce the power dissipated in the circuit. Moving Ground Around: Ground is a reference point that can be moved around. e.g. considerr a collector feedback bias circuit. The various stages of moving ground are shown in fig. 2.

27 Fig. 2 Biasing a pnp Transistor: The biasing of pnp transistor is done similar to npn transistor except that supply is of opposite polarity The various biasing circuits of pnp transistor are shown in fig. 3.

28 Fig. 3 Example 2: For the circuit shown in fig. 4, calculate I C and V CE Solution: Fig. 4 Biasing methods for amplifiers: Biasing Circuit Techniques or Locating the Q - Point: Fixed Bias or Base Bias:

29 In order for a transistor to amplify, it has to be properly biased. This means forward biasing the base emitter junction and reverse biasing collector base junction. For linear amplification, the transistor should operate in active region ( If I E increases, I C increases, V CE decreases proportionally). The source V BB, through a current limit resistor R B forward biases thee emitter diode and V CC through resistor R C (load resistance) reverse biases the collector junction as shown in fig. 1. Fig. 1 The dc base current through R B is given by I B = (V BB - V BE ) / R B or V B BE = V BB - I B R B Normally V BE is taken 0.7V or 0.3V. If exact voltage is required, then the input characteristic ( I B vs V BE ) of the transistor should be used to solve the above equation. The load line for the input circuit is drawn on input characteristic. The two points of the load line can be obtained as given below For I B = 0, V BE = V BB. and For V BE = 0, I B = V BB / R B. The intersection of this line with input characteristic gives the operating point Q as shown in fig. 2. If an ac signal is connected to the base of the transistor, then variation in V BE is aboutt Q - point. Thiss gives variation in I B and hence I C. Fig. 2

30 In the output circuit, the load equation can be written as V CE = V CC - I C R C This equation involves two unknown V C E and I C and therefore can not be solved. To solve this equation output characteristic ( I C vs V CE ) is used. The load equation is the equation of a straight line and given by two points: I C = 0, & V CE = V CC VCE = 0, I C = V CC / R C The intersection of this line which is also called dc load line and the characteristic gives the operating point Q as shown in fig. 3. Fig. 3 The point at which the load line intersects with I B = 0 characteristic iss known as cut off point. At this point base current is zero and collector current is almost negligibly small. At cut off the emitter diode comes out of forward bias and normal transistor action is lost. To a close approximation. V CE ( cut off) V CC (approximately). The intersection of the load line and I B = I B(max) characteristic is known as saturation point. At this point I B = I B(max x), I C = I C(sat). At this point collector diodes comes out of reverse bias and again transistor action is lost. To a close approximation, I C(sat) V C C / R C (approximately ). The I B(sat) is the minimum current required to operate the transistor inn saturation region. If the I B is less than I B (sa transistor will operate in active region. If I B > I B (sat) it always operatess in saturation region. If the transistor operates at saturation or cut off points and no where else then it is operating as a switch is shown in fig. 4. at), the

31 Fig. 4 V BB = I B RB+ B V BE I B = (V BB V BE ) / R B If I B > I B(sat), then it operates at saturation, If I B = 0, then it operates at cut off. If a transistor is operating as an amplifier then Q point must be selected carefully. Although we can select the operating point any wheree in the active region by choosing different values of R B & R C but the various transistor ratings such as maximumm collector dissipation P C(max) maximum collector voltage V C(max) and I C(ma ax) & V BE(max) limit the operating range. Once the Q point is established an ac input is connected. Due to thiss the ac source the base current varies. As a result of this collector current and collector voltage also varies and the amplified output is obtained. If the Q-point is not selected properly then the output waveform will not be exactly the input waveform. i.e. It may be clipped from one side or both sides or it may be distorted one. Field effect transistor: Junctionn field effect transistor:

32 Module 1 Power Semiconductor Devices Version 2 EE IIT, Kharagpur 1

33 Lesson 6 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Version 2 EE IIT, Kharagpur 2

34 Constructional Features, operating principle and characteristics of Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Instructional Objectives On completion the student will be able to Differentiate between the conduction mechanism of a MOSFET and a BJT. Explain the salient constructional features of a MOSFET. Draw the output i-v characteristics of a MOSFET and explain it in terms of the operating principle of the device. Explain the difference between the safe operating area of a MOSFET and a BJT. Draw the switching characteristics of a MOSFET and explain it. Design the gate drive circuit of a MOSFET. Interpret the manufacturer s data sheet rating of a MOSFET. Version 2 EE IIT, Kharagpur 3

35 6.1 Introduction Historically, bipolar semiconductor devices (i.e, diode, transistor, thyristor, thyristor, GTO etc) have been the front runners in the quest for an ideal power electronic switch. Ever since the invention of the transistor, the development of solid-state switches with increased power handling capability has been of interest for expending the application of these devices. The BJT and the GTO thyristor have been developed over the past 30 years to serve the need of the power electronic industry. Their primary advantage over the thyristors have been the superior switching speed and the ability to interrupt the current without reversal of the device voltage. All bipolar devices, however, suffer from a common set of disadvantages, namely, (i) limited switching speed due to considerable redistribution of minority charge carriers associated with every switching operation; (ii) relatively large control power requirement which complicates the control circuit design. Besides, bipolar devices can not be paralleled easily. The reliance of the power electronics industry upon bipolar devices was challenged by the introduction of a new MOS gate controlled power device technology in the 1980s. The power MOS field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. The new device promised extremely low input power levels and no inherent limitation to the switching speed. Thus, it opened up the possibility of increasing the operating frequency in power electronic systems resulting in reduction in size and weight. The initial claims of infinite current gain for the power MOSFET were, however, diluted by the need to design the gate drive circuit to account for the pulse currents required to charge and discharge the high input capacitance of these devices. At high frequency of operation the required gate drive power becomes substantial. MOSFETs also have comparatively higher on state resistance per unit area of the device cross section which increases with the blocking voltage rating of the device. Consequently, the use of MOSFET has been restricted to low voltage (less than about 500 volts) applications where the ON state resistance reaches acceptable values. Inherently fast switching speed of these devices can be effectively utilized to increase the switching frequency beyond several hundred khz. From the point of view of the operating principle a MOSFET is a voltage controlled majority carrier device. As the name suggests, movement of majority carriers in a MOSFET is controlled by the voltage applied on the control electrode (called gate) which is insulated by a thin metal oxide layer from the bulk semiconductor body. The electric field produced by the gate voltage modulate the conductivity of the semiconductor material in the region between the main current carrying terminals called the Drain (D) and the Source (S). Power MOSFETs, just like their integrated circuit counterpart, can be of two types (i) depletion type and (ii) enhancement type. Both of these can be either n- channel type or p-channel type depending on the nature of the bulk semiconductor. Fig 6.1 (a) shows the circuit symbol of these four types of MOSFETs along with their drain current vs gate-source voltage characteristics (transfer characteristics). Version 2 EE IIT, Kharagpur 4

36 G D I D G D I D G D I D G D I D S S S S I D I D I D I D V GS n-channel depletion type MOSFET V GS p-channel depletion type MOSFET V GS n-channel enhancement type MOSFET V GS p-channel enhancement type MOSFET (a) (b) Fig 6.1: Different types of power MOSFET. (a) Circuit symbols and transfer characteristics (b) Photograph of n-channel enhancement type MOSFET. From Fig 6.1 (a) it can be concluded that depletion type MOSFETs are normally ON type switches i.e, with the gate terminal open a nonzero drain current can flow in these devices. This is not convenient in many power electronic applications. Therefore, the enhancement type MOSFETs (particularly of the n-channel variety) is more popular for power electronics applications. This is the type of MOSFET which will be discussed in this lesson. Fig 6.1 (b) shows the photograph of some commercially available n-channel enhancement type Power MOSFETs. 6.2 Constructional Features of a Power MOSFET As mentioned in the introduction section, Power MOSFET is a device that evolved from MOS integrated circuit technology. The first attempts to develop high voltage MOSFETs were by redesigning lateral MOSFET to increase their voltage blocking capacity. The resulting technology was called lateral double deffused MOS (DMOS). However it was soon realized that Version 2 EE IIT, Kharagpur 5

37 much larger breakdown voltage and current ratings could be achieved by resorting to a vertically oriented structure. Since then, vertical DMOS (VDMOS) structure has been adapted by virtually all manufacturers of Power MOSFET. A power MOSFET using VDMOS technology has vertically oriented three layer structure of alternating p type and n type semiconductors as shown in Fig 6.2 (a) which is the schematic representation of a single MOSFET cell structure. A large number of such cells are connected in parallel (as shown in Fig 6.2 (b)) to form a complete device. Source FIELD OXIDE Gate conductor Gate oxide n + n + n + n + p(body) n - (drain drift) n + p(body) Drain (a) Contact to source Field oxide Source Conductor Gate Oxide Gate Conductor n + p n + n + p n + n - n + Single MOSFET Cell n - n + (b) Fig. 6.2: Schematic construction of a power MOSFET (a) Construction of a single cell. (b) Arrangement of cells in a device. Version 2 EE IIT, Kharagpur 6

38 The two n + end layers labeled Source and Drain are heavily doped to approximately the same level. The p type middle layer is termed the body (or substrate) and has moderate doping level (2 to 3 orders of magnitude lower than n + regions on both sides). The n - drain drift region has the lowest doping density. Thickness of this region determines the breakdown voltage of the device. The gate terminal is placed over the n - and p type regions of the cell structure and is insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate oxide). The source and the drain region of all cells on a wafer are connected to the same metallic contacts to form the Source and the Drain terminals of the complete device. Similarly all gate terminals are also connected together. The source is constructed of many (thousands) small polygon shaped areas that are surrounded by the gate regions. The geometric shape of the source regions, to same extent, influences the ON state resistance of the MOSFET. S n + p n + Body spreading Parasitic BJT resistance n - n + G MOSFET G D Parasitic BJT G D Body diode D S S Fig. 6.3: Parasitic BJT in a MOSFET cell. One interesting feature of the MOSFET cell is that the alternating n + n - p n + structure embeds a parasitic BJT (with its base and emitter shorted by the source metallization) into each MOSFET cell as shown in Fig 6.3. The nonzero resistance between the base and the emitter of the parasitic npn BJT arises due to the body spreading resistance of the p type substrate. In the design of the MOSFET cells special care is taken so that this resistance is minimized and switching operation of the parasitic BJT is suppressed. With an effective short circuit between the body and the source the BJT always remain in cut off and its collector-base junction is represented as an anti parallel diode (called the body diode) in the circuit symbol of a Power MOSFET. 6.3 Operating principle of a MOSFET At first glance it would appear that there is no path for any current to flow between the source and the drain terminals since at least one of the p n junctions (source body and body-drain) will be reverse biased for either polarity of the applied voltage between the source and the drain. There is no possibility of current injection from the gate terminal either since the gate oxide is a very good insulator. However, application of a positive voltage at the gate terminal with respect to the source will covert the silicon surface beneath the gate oxide into an n type layer or channel, thus connecting the Source to the Drain as explained next. Version 2 EE IIT, Kharagpur 7

39 The gate region of a MOSFET which is composed of the gate metallization, the gate (silicon) oxide layer and the p-body silicon forms a high quality capacitor. When a small voltage is application to this capacitor structure with gate terminal positive with respect to the source (note that body and source are shorted) a depletion region forms at the interface between the SiO 2 and the silicon as shown in Fig 6.4 (a). Source Electrode V GS Gate Electrode Si0 2 n + p Ionized acceptor Depletion layer boundary. n - (a) Source Electrode V GS2 V GS2 > V GS Gate Electrode Si0 2 n + p n - Ionized acceptor Free electron Depletion layer boundary. (b) Version 2 EE IIT, Kharagpur 8

40 Source Electrode V GS3 n + V GS3 > V GS2 > V GS Gate Electrode Si0 2 Inversion layer with free electrons p n - Ionized acceptor Depletion layer boundary. (c) Fig. 6.4: Gate control of MOSFET conduction. (a) Depletion layer formation; (b) Free electron accumulation; (c) Formation of inversion layer. The positive charge induced on the gate metallization repels the majority hole carriers from the interface region between the gate oxide and the p type body. This exposes the negatively charged acceptors and a depletion region is created. Further increase in V GS causes the depletion layer to grow in thickness. At the same time the electric field at the oxide-silicon interface gets larger and begins to attract free electrons as shown in Fig 6.4 (b). The immediate source of electron is electron-hole generation by thermal ionization. The holes are repelled into the semiconductor bulk ahead of the depletion region. The extra holes are neutralized by electrons from the source. As V GS increases further the density of free electrons at the interface becomes equal to the free hole density in the bulk of the body region beyond the depletion layer. The layer of free electrons at the interface is called the inversion layer and is shown in Fig 6.4 (c). The inversion layer has all the properties of an n type semiconductor and is a conductive path or channel between the drain and the source which permits flow of current between the drain and the source. Since current conduction in this device takes place through an n- type channel created by the electric field due to gate source voltage it is called Enhancement type n-channel MOSFET. The value of V GS at which the inversion layer is considered to have formed is called the Gate Source threshold voltage V GS (th). As V GS is increased beyond V GS (th) the inversion layer gets some what thicker and more conductive, since the density of free electrons increases further with increase in V GS. The inversion layer screens the depletion layer adjacent to it from increasing V GS. The depletion layer thickness now remains constant. Version 2 EE IIT, Kharagpur 9

41 Exercise 6.1 (after section 6.3) 1. Fill in the blank(s) with the appropriate word(s) i. A MOSFET is a controlled carrier device. ii. iii. iv. Enhancement type MOSFETs are normally devices while depletion type MOSFETs are normally devices. The Gate terminal of a MOSFET is isolated from the semiconductor by a thin layer of. The MOSFET cell embeds a parasitic in its structure. v. The gate-source voltage at which the layer in a MOSFET is formed is called the voltage. vi. The thickness of the layer remains constant as gate source voltage is increased byond the voltage. Answer: (i) voltage, majority; (ii) off, on; (iii) SiO 2, (iv) BJT, (v) inversion, threshold; (vi) depletion, threshold. 2. What are the main constructional differences between a MOSFET and a BJT? What effect do they have on the current conduction mechanism of a MOSFET? Answer: A MOSFET like a BJT has alternating layers of p and n type semiconductors. However, unlike BJT the p type body region of a MOSFET does not have an external electrical connection. The gate terminal is insulated for the semiconductor by a thin layer of SiO 2. The body itself is shorted with n + type source by the source metallization. Thus minority carrier injection across the source-body interface is prevented. Conduction in a MOSFET occurs due to formation of a high density n type channel in the p type body region due to the electric field produced by the gate-source voltage. This n type channel connects n + type source and drain regions. Current conduction takes place between the drain and the source through this channel due to flow of electrons only (majority carriers). Where as in a BJT, current conduction occurs due to minority carrier injection across the Base-Emitter junction. Thus a MOSFET is a voltage controlled majority carrier device while a BJT is a minority carrier bipolar device. 6.4 Steady state output i-v characteristics of a MOSFET The MOSFET, like the BJT is a three terminal device where the voltage on the gate terminal controls the flow of current between the output terminals, Source and Drain. The source terminal is common between the input and the output of a MOSFET. The output characteristics of a MOSFET is then a plot of drain current (i D ) as a function of the Drain Source voltage (v DS ) with gate source voltage (v GS ) as a parameter. Fig 6.5 (a) shows such a characteristics. Version 2 EE IIT, Kharagpur 10

42 i D ohmic r DS (ON) V GS V GS (th) = V DS Increasing V GS V GS6 Active [V GS V GS (th)]<v DS V GS5 Electron Drift Velocity V GS4 V GS3 V GS2 v gs1 Cut off (V GS < V GS (th)) S (a) G V DSS v DS i D (c) Electric Field n + Source region resistance p n - n + Channel resistance i D Drift region resistance Drain resistance (b) D V GS (th) (d) V GS Fig. 6.5: Output i-v characteristics of a Power MOSFET (a) i-v characteristics; (b) Components of ON-state resistance; (c) Electron drift velocity vs Electric field; (d) Transfer With gate-source voltage (V GS ) below the threshold voltage (v GS (th)) the MOSFET operates in the cut-off mode. No drain current flows in this mode and the applied drain source voltage (v DS ) is supported by the body-collector p-n junction. Therefore, the maximum applied voltage should be below the avalanche break down voltage of this junction (V DSS ) to avoid destruction of the device. When V GS is increased beyond v GS (th) drain current starts flowing. For small values of v DS (v DS < (v GS v GS (th)) i D is almost proportional to v DS. Consequently this mode of operation is called ohmic mode of operation. In power electronic applications a MOSFET is operated either in the cut off or in the ohmic mode. The slope of the v DS i D characteristics in this mode is called the ON state resistance of the MOSFET (r DS (ON)). Several physical resistances as shown in Fig 6.5 (b) contribute to r DS (ON). Note that r DS (ON) reduces with increase in v GS. This is mainly due to reduction of the channel resistance at higher value of Version 2 EE IIT, Kharagpur 11

43 v GS. Hence, it is desirable in power electronic applications, to use as large a gate-source voltage as possible subject to the dielectric break down limit of the gate-oxide layer. At still higher value of v DS (v DS > (v GS v GS (th)) the i D v DS characteristics deviates from the linear relationship of the ohmic region and for a given v GS, i D tends to saturate with increase in v DS. The exact mechanism behind this is rather complex. It will suffice to state that, at higher drain current the voltage drop across the channel resistance tends to decrease the channel width at the drain drift layer end. In addition, at large value of the electric field, produced by the large Drain Source voltage, the drift velocity of free electrons in the channel tends to saturate as shown in Fig 6.5 (c). As a result the drain current becomes independent of V DS and determined solely by the gate source voltage v GS. This is the active mode of operation of a MOSFET. Simple, first order theory predicts that in the active region the drain current is given approximately by i = K(v - v (th)) (6.1) D GS GS Where K is a constant determined by the device geometry. At the boundary between the ohmic and the active region v = v - v (th) (6.2) DS GS GS 2 D DS Therefore, i = Kv (6.3) 2 Equation (6.3) is shown by a dotted line in Fig 6.5 (a). The relationship of Equation (6.1) applies reasonably well to logic level MOSFETs. However, for power MOSFETs the transfer characteristics (i D vs v GS ) is more linear as shown in Fig 6.5 (d). At this point the similarity of the output characteristics of a MOSFET with that of a BJT should be apparent. Both of them have three distinct modes of operation, namely, (i)cut off, (ii) active and (iii) ohmic (saturation for BJT) modes. However, there are some important differences as well. Unlike BJT a power MOSFET does not undergo second break down. The primary break down voltage of a MOSFET remains same in the cut off and in the active modes. This should be contrasted with three different break down voltages (V SUS, V CEO & V CBO ) of a BJT. The ON state resistance of a MOSFET in the ohmic region has positive temperature coefficient which allows paralleling of MOSFET without any special arrangement for current sharing. On the other hand, v CE (sat) of a BJT has negative temperature coefficient making parallel connection of BJTs more complicated. As in the case of a BJT the operating limits of a MOSFET are compactly represented in a Safe Operating Area (SOA) diagram as shown in Fig 6.6. As in the case of the FBSOA of a Version 2 EE IIT, Kharagpur 12

44 BJT the SOA of a MOSFET is plotted on a log-log graph. On the top, the SOA is restricted by the absolute maximum permissible value of the drain current (I DM ) which should not be exceeded even under pulsed operating condition. To the left, operating restriction arise due to the non zero value of r DS (ON) corresponding to v GS = v GS (Max). To the right, the first operating restriction is due to the limit on the maximum permissible junction temperature rise which depends on the power dissipation inside the MOSFET. This limit is different for DC (continuous) and pulsed operation of different pulse widths. As in the case of a BJT the pulsed safe operating areas are useful for shaping the switching trajectory of a MOSFET. A MOSFET does not undergo second break down and no corresponding operating limit appears on the SOA. The final operation limit to the extreme right of the SOA arises due to the maximum permissible drain source voltage (V DSS ) which is decided by the avalanche break down voltage of the drain -body p-n junction. This is an instantaneous limit. There is no distinction between the forward biased and the reverse biased SOAs for the MOSFET. They are identical. Log (i D ) I DM r DS (ON) limit (V GS = V GS (max)) Max. Power Dissipation Limit (T imax ) 10-5 sec 10-4 sec 10-3 sec DC V DSS Fig. 6.6: Safe operating area of a MOSFET. Primary voltage breakdown limit Log (v DS ) Due to the presence of the anti parallel body diode, a MOSFET can not block any reverse voltage. The body diode, however, can carry an RMS current equal to I DM. It also has a substantial surge current carrying capacity. When reverse biased it can block a voltage equal to V DSS. For safe operation of a MOSFET, the maximum limit on the gate source voltage (V GS (Max)) must be observed. Exceeding this voltage limit will cause dielectric break down of the thin gate oxide layer and permanent failure of the device. It should be noted that even static charge inadvertently put on the gate oxide by careless handling may destroy it. The device user should ground himself before handling any MOSFET to avoid any static charge related problem. Exercise 6.2 Fill in the blank(s) with the appropriate word(s) i. A MOSFET operates in the mode when v GS < v GS (th) Version 2 EE IIT, Kharagpur 13

45 ii. In the ohmic region of operation of a MOSFET v GS v GS (th) is greater than. iii. r DS (ON) of a MOSFET with increasing v GS. iv. In the active region of operation the drain current i D is a function of alone and is independent of. v. The primary break down voltage of MOSFET is of the drain current. vi. Unlike BJT a MOSFET does not undergo. vii. temperature coefficient of r DS (ON) of MOSFETs facilitates easy of the devices. viii. In a Power MOSFET the relation ship between i D and v GS v GS (th) is almost in the active mode of operation. ix. The safe operating area of a MOSFET is restricted on the left hand side by the limit. Answer: (i) Cut off; (ii) v DS ; (iii) decreases; (iv) v GS, v DS ; (v) independent; (vi) break down; (vii) Positive, paralleling; (viii) linear; (ix) r DS (ON); second 6.5 Switching characteristics of a MOSFET Circuit models of a MOSFET cell Like any other power semiconductor device a MOSFET is used as a switch in all power electronic converters. As a switch a MOSFET operates either in the cut off mode (switch off) or in the ohmic mode (switch on). While making transition between these two states it traverses through the active region. Being a majority carrier device the switching process in a MOSFET does not involve any inherent delay due to redistribution of minority charge carriers. However, formation of the conducting channel in a MOSFET and its disappearance require charging and discharging of the gate-source capacitance which contributes to the switching times. There are several other capacitors in a MOSFET structure which are also involved in the switching process. Unlike bipolar devices, however, these switching times can be controlled completely by the gate drive circuit design. Version 2 EE IIT, Kharagpur 14

46 S G Gate oxide n + p C DS C GS C GD Drain body depletion layer C GD C GD1 idealized Actual n - n + C GD2 (a) D V GS V GS (th) = V DS (b) V DS D D D C GD C GD C GD G (cut off) G i D = f(v GS ) G r DS (ON) C GS C GS (Active) C GS (Ohmic) S S (c) Fig. 6.7: Circuit model of a MOSFET (a) MOSFET capacitances (b) Variation of C GD with V DS (c) Circuit models. S Fig 6.7 (a) shows three important capacitances inherent in a MOSFET structure. The most prominent capacitor in a MOSFET structure is formed by the gate oxide layer between the gate metallization and the n + type source region. It has the largest value (a few nano farads) and remains more or less constant for all values of v GS and v DS. The next largest capacitor (a few hundred pico forwards) is formed by the drain body depletion region directly below the gate metallization in the n - drain drift region. Being a depletion layer capacitance its value is a strong function of the drain source voltage v DS. For low values of v DS (v DS < (v GS v GS (th))) the value of C GD (C GD2 ) is considerably higher than its value for large v DS as shown in Fig 6.7 (b). Although variation of C GD between C GD1 and C GD2 is continuous a step change in the value of C GD at v DS = v GS v GS (th) is assumed for simplicity. The lowest value capacitance is formed between the drain and the source terminals due to the drain body depletion layer away form the gate metallization and below the source metallization. Although this capacitance is important for some design considerations (such as snubber design, zero voltage switching etc) it does not appreciably affect the hard switching performance of a MOSFET. Consequently, it will be neglected in our discussion. From the Version 2 EE IIT, Kharagpur 15

47 above discussion and the steady state characteristics of a MOSFET the circuit models of a MOSFET in three modes of operation can be drawn as shown in Fig 6.7 (c) Switching waveforms The switching behavior of a MOSFET will be described in relation to the clamped inductive circuit shown in Fig 6.8. For simplicity the load current is assumed to remain constant over the small switching interval. Also the diode D F is assumed to be ideal with no reverse recovery current. The gate is assumed to be driven by an ideal voltage source giving a step voltage between zero and V gg in series with an external gate resistance R g. V D D F I O i f + i D C GD V DS R g V gg + - i g C GS - Fig. 6.8: Clamped inductive switching circuit using a MOSFET. To turn the MOSFET on, the gate drive voltage changes from zero to V gg. The gate source voltage which was initially zero starts rising towards V gg with a time constant τ 1 = R g (C GS + C GD1 ) as shown in Fig 6.9. Version 2 EE IIT, Kharagpur 16

48 V gg V GS τ 2 V GS I 0 V GS (th) V R gg g i g i g I 0 τ 2 = R g (C GS +C GD2 ) τ 1 = R g (C GS +C GD1 ) V R gg g τ 1 i g I 0 t t i D, i f i D i f I 0 I 0 i f i D t V DS I 0 r os (ON) t don t ri t fv1 t fv2 t ON t d (off) t rv2 t off t rvi t fi t Fig. 6.9: Switching waveforms of a clamped inductive switching circuit using MOSFET Note that during this period the drain voltage v DS is clamped to the supply voltage V D through the free wheeling diode D F. Therefore, C GS and C GD can be assumed to be connected in parallel effectively. A part of the total gate current ig charges C GS while the other part discharges C GD. Till v GS reaches v GS (th) no drain current flows. This time period is called turn on delay time (t d (ON)). Note that t d (ON) can be controlled by controlling R g. Byond t d (ON) i D increases linearly with v GS and in a further time t ri (current rise time) reaches I o. The corresponding value of v GS and i g are marked as V GS I o and i g I o respectively in Fig 6.9. At this point the complete load current has been transferred to the MOSFET from the free wheeling diode D F. i D does not increase byond this point. Since in the active region i D and v GS are linearly related, v GS also becomes clamped at the value v GS I o. The gate current i g now discharges C GD and the drain voltage starts falling. d d d i V -V I v DS = v GS + v GD = v GD = = 6.4 dt dt dt C C R g GG GS o ( ) ( ) GD GD g Version 2 EE IIT, Kharagpur 17

49 The fall of v DS occurs in two distinct intervals. When the MOSFET is in the active region (v DS > (v GS v GS (th)) C GD = C GD1.Since C GD1 << C GD2, v DS falls rapidly. This fast fall time of v DS is marked t fv1 in Fig 6.9. However, once in the ohmic region, C GD = C GD2 >> C GD1. Therefore, rate of fall of v DS slows down considerably (t fv2 ). Once v DS reaches its on state value (r DS (ON) I o ) v GS becomes unclamped and increases towards V gg with a time constant τ 2 = R g (C GS + C GD2 ). Note that all switching periods can be reduced by increasing Vgg or / and decreasing Rg. The total turn on time is t ON = t d (ON) + t ri + t fv1 + t fv2. To turn the MOSFET OFF, V gg is reduced to zero triggering the exact reverse process of turn on to take place. The corresponding waveforms and switching intervals are show in Fig 6.9. The total turn off time t off = t d (off) + t rv1 + t rv2 + t fi MOSFET Gate Drive MOSFET, being a voltage controlled device, does not require a continuous gate current to keep it in the ON state. However, it is required to charge and discharge the gate-source and the gate-drain capacitors in each switching operation. The switching times of a MOSFET essentially depends on the charging and discharging rate of these capacitors. Therefore, if fast charging and discharging of a MOSFET is desired at fast switching frequency the gate drive power requirement may become significant. Fig 6.10 (a) shows a typical gate drive circuit of a MOSFET. Version 2 EE IIT, Kharagpur 18

50 V GG V D V GG R 1 R G + (β 1 +1) R 1 Logic level gate pulse Q 1 Q 2 R G V GG R G Q 3 (a) (b) V D D D F I L R R G G D R G B S R B (d) S (c) Fig. 6.10: MOSFET gate drive circuit. (a) Gate drive circuit; (b) Equivalent circuit during turn on and off; (b) Effect of parasitic BJT; (d) Parallel connection of MOSFET s. To turn the MOSFET on the logic level input to the inverting buffer is set to high state so that transistor Q 3 turns off and Q 1 turns on. The top circuit of Fig 6.10 (b) shows the equivalent circuit during turn on. Note that, during turn on Q 1 remains in the active region. The effective gate resistance is R G + R 1 / (β 1 + 1). Where, β 1 is the dc current gain of Q 1. Version 2 EE IIT, Kharagpur 19

51 Exercise 6.3 To turn off the MOSFET the logic level input is set to low state. Q 3 and Q 2 turns on whole Q 1 turns off. The corresponding equivalent circuit is given by the bottom circuit of Fig 6.10 (b) The switching time of the MOSFET can be adjusted by choosing a proper value of R G. Reducing R G will incase the switching speed of the MOSFET. However, caution should be exercised while increasing the switching speed of the MOSFET in order not to turn on the parasitic BJT in the MOSFET structure inadvertently. The drain-source capacitance (C DS ) is actually connected to the base of the parasitic BJT at the p type body region. The body source short has some nonzero resistance. A very fast rising drain-source voltage will send sufficient displacement current through C DS and R B as shown in Fig 6.10 (c). The voltage drop across R B may become sufficient to turn on the parasitic BJT. This problem is largely avoided in a modern MOSFET design by increasing the effectiveness of the body-source short. The devices are now capable of dv DS /dt in excess to 10,000 V/μs. Of course, this problem can also be avoided by slowing down the MOSFET switching speed. Since MOSFET on state resistance has positive temperature coefficient they can be paralleled without taking any special precaution for equal current sharing. To parallel two MOSFETs the drain and source terminals are connected together as shown in Fig 6.10 (d). However, small resistances (R) are connected to individual gates before joining them together. This is because the gate inputs are highly capacitive with almost no losses. Some stray inductance of wiring may however be present. This stray inductance and the MOSFET capacitance can give rise to unwanted high frequency oscillation of the gate voltage that can result in puncture of the gate qxide layer due to voltage increase during oscillations. This is avoided by the damping resistance R. 1. Fill in the blank(s) with the appropriate word(s) i. The Gate-Source capacitance of a MOSFET is the among all three capacitances. ii. The Gate-Drain transfer capacitance of a MOSFET has large value in the region and small value in the region. iii. During the turn on delay time the MOSFET gate source voltage rises from zero to the voltage. iv. The voltage fall time of a MOSFET is proportional to the gate charging resistance. v. Unlike BJT the switching delay times in a MOSFET can be controlled by proper design of the circuit. Answer: (i) largest; (ii) ohmic, active; (iii) threshold; (iv) inversely; (v) gate drive. Version 2 EE IIT, Kharagpur 20

52 2. A Power MOSFET has the following data C GS = 800 pf ; C GD = 150 pf; g f = 4; v GS (th) = 3V; It is used to switch a clamped inductive load (Fig 6.8) of 20 Amps with a supply voltage V D = 200V. The gate drive voltage is v gg = 15V, and gate resistance R g = 50Ω. Find out maximum value of did dt and dv dt DS Answer: During turn on i g v -v (th) ( ) D f gs gs di dv D gs =gf dt dt dv V - v C GS +C GD = dt R But ( ) gs gg gs di dv g dt dt R C + C g during turn ON. D gs =g f = V -v g GS GD f ( ) ( ) gg gs g ( ) ( ) gf ( Vgg -v gs(th) ) f gg gs Min ( ) did = V -v = dt R C +C R C +C Max g GS GD g GS GD did since for v gs < v gs(th) i D = = 0 dt did 4 9 = -12 ( 15-3 ) = A sec dt Max From equation (6.4) dv V -V,I DS = dt C R gg GS o GD g For I o = 20 A, v gs (th) = 3V, and g f = 4 Io 20 V GS,I o = +v gs(th)= +3=8 volts g 4 dvds 15-8 dt f 6 = = V sec MOSFET Ratings Steady state operating limits of a MOSFET are usually specified compactly as a safe operating area (SOA) diagram. The following limits are specified. V DSS : This is the drain-source break down voltage. Exceeding this limit will destroy the device due to avalanche break down of the body-drain p-n junction. Version 2 EE IIT, Kharagpur 21

53 I DM : This is the maximum current that should not be exceeded even under pulsed current operating condition in order to avoid permanent damage to the bonding wires. Continuous and Pulsed power dissipation limits: They indicate the maximum allowable value of the V DS, i D product for the pulse durations shown against each limit. Exceeding these limits will cause the junction temperature to rise beyond the acceptable limit. All safe operating area limits are specified at a given case temperature. In addition, several important parameters regarding the dynamic performance of the device are also specified. These are Gate threshold voltage (V GS (th)): The MOSFET remains in the cut off region when v GS in below this voltage. V GS (th) decreases with junction temperature. Drain Source on state resistance (r DS (ON)): This is the slope of the i D v DS characteristics in the ohmic region. Its value decreases with increasing v GS and increases with junction temperature. r DS (ON) determines the ON state power loss in the device. Forward Transconductance (g fs ): It is the ratio of i D and (v GS v GS (th)). In a MOSFET switching circuit it determines the clamping voltage level of the gate source voltage and thus influences dv DS /dt during turn on and turn off. Gate-Source breakdown voltage: Exceeding this limit will destroy the gate structure of the MOSFET due to dielectric break down of the gate oxide layer. It should be noted that this limit may by exceeded even by static charge deposition. Therefore, special precaution should be taken while handing MOSFETs. Input, output and reverse transfer capacitances (C GS, C DS & C GD ): Value of these capacitances are specified at a given drain-source and gate-source voltage. They are useful for designing the gate drive circuit of a MOSFET. In addition to the main MOSFET, specifications pertaining to the body diode are also provided. Specifications given are Reverse break down voltage: This is same as V DSS Continuous ON state current (I S ): This is the RMS value of the continuous current that can flow through the diode. Pulsed ON state current (I SM ): This is the maximum allowable RMS value of the ON state current through the diode given as a function of the pulse duration. Forward voltage drop (v F ): Given as an instantaneous function of the diode forward current. Reverse recovery time (t rr ) and Reverse recovery current (I rr ): These are specified as functions of the diode forward current just before reverse recovery and its decreasing slope (di F /dt). Version 2 EE IIT, Kharagpur 22

54 Exercise 6.4 Fill in the blank(s) with the appropriate word(s) i. The maximum voltage a MOSFET can with stand is of drain current. ii. The FBSOA and RBSOA of a MOSFET are. iii. The gate source threshold voltage of a MOSFET with junction temperature while the on state resistance with junction temperature. iv. The gate oxide of a MOSFET can be damaged by electricity. v. The reverse break down voltage of the body diode of a MOSFET is equal to while its RMS forward current rating is equal to. Answer: (i) independent; (ii) identical; (iii) decreases, increases; (iv) static; (v) V DSS ; I DM. Reference [1] Evolution of MOS-Bipolar power semiconductor Technology, B. Jayant Baliga, Proceedings of the IEEE, VOL.76, No-4, April [2] Power Electronics,Converters Application and Design Third Edition, Mohan, Undeland, Robbins. John Wiley & Sons Publishers [3] GE Power MOSFET data sheet. Version 2 EE IIT, Kharagpur 23

55 Lesson Summary MOSFET is a voltage controlled majority carrier device. A Power MOSFET has a vertical structure of alternating p and n layers. The main current carrying terminals of an n channel enhancement mode MOSFET are called the Drain and the Source and are made up of n + type semiconductor. The control terminal is called the Gate and is isolated form the bulk semiconductor by a thin layer of SiO 2. p type semiconductor body separates n + type source and drain regions. A conducting n type channel is produced in the p type body region when a positive voltage greater than a threshold voltage is applied at the gate. Current conduction in a MOSFET occurs by flow of electron from the source to the drain through this channel. When the gate source voltage is below threshold level a MOSFET remains in the Cut Off region and does not conduct any current. With v GS > v GS (th) and v DS < (v GS v GS (th)) the drain current in a MOSFET is proportional to v DS. This is the Ohmic region of the MOSFET output characteristics. For larger values of v DS the drain current is a function of v GS alone and does not depend on v Ds. This is called the active region of the MOSFET. In power electronic applications a MOSFET is operated in the Cut Off and Ohmic regions only. The on state resistance of a MOSFET (V DS (ON)) has a positive temperature coefficient. Therefore, MOSFETs can be easily paralleled. A MOSFET does not undergo second break down. The safe operating area (SOA) of a MOSFET is similar to that of a BJT except that it does not have a second break down limit. Unlike BJT the maximum forward voltage withstanding capability of a MOSFET does not depend on the drain current. The safe operating area of a MOSFET does not change under Forward and Reverse bias conditions. The drain body junction in a MOSFET structure constitute an anti parallel diode connected between the source and the drain. This is called the MOSFET body diode. The body diode of a MOSFET has the same break down voltage and forward current rating as the main MOSFET. The switching delays in a MOSFET are due to finite charging and discharging time of the input and output capacitors. Switching times of a MOSFET can be controlled completely by external gate drive design. Version 2 EE IIT, Kharagpur 24

56 The input capacitor along with the gate drive resistance determine the current rise and fall time of a MOSFET during switching. The transfer capacitor (C gd ) determines the drain voltage rise and fall times. r DS (ON) of a MOSFET determines the conduction loss during ON period. r DS (ON) reduces with higher v gs. Therefore, to minimize conduction power loss maximum permissible v gs should be used subject to dielectric break down of the gate oxide layer. The gate oxide layer can be damaged by static charge. Therefore MOSFETs should be handled only after discharging one self through proper grounding. For similar voltage rating, a MOSFET has a relatively higher conduction loss and lower switching loss compared to a BJT. Therefore, MOSFETs are more popular for high frequency (>50 khz) low voltage (<100 V) circuits. Version 2 EE IIT, Kharagpur 25

57 Practice Problems and Answers Version 2 EE IIT, Kharagpur 26

58 Practice Problems 1. How do you expect the gate source capacitance of a MOSFET to varry with gate source voltage. Explain your answer. 2. The gate oxide layer of a MOSFET is 1000 Angstrom thick Assuming a break down field strength of V/cm and a safely factor of 50%, find out the maximum allowable gate source voltage. 3. Explain why in a high voltage MOSFET switching circuit the voltage rise and fall time is always greater than current fall and rise times. 4. A MOSFET has the following parameters V GS (th) = 3V, g fs = 3, C GS = 800 PF, C GD = 250 PF. The MOSFET is used to switch an inductive load of 15 Amps from 150V supply. The switching frequency is 50 khz. The gate drive circuit has a driving voltage of 15V and output resistance of 50Ω. Find out the switching loss in the MOSFET. Version 2 EE IIT, Kharagpur 27

59 Answer to practice problems 1. When the gate voltage is zero the thickness of the gate-source capacitance is approximately equal to the thickness of the gate oxide layer. As the gate source voltage increases the width of the depletion layer in the p body region also increases. Since the depletion layer is a region of immobile charges it in effect increases the thickness of the gate-source capacitance and hence the value of this capacitances decreases with increasing v GS. However, as v GS is increased further free electrons generated by thermal ionization get attracted towards the gate oxide-semiconductor interface. These free electrons screen the depletion layer partially and the gate-source capacitance starts increasing again. When v GS is above v gs (th) the inversion layer completely screens the depletion layer and the effective thickness of the gate-source capacitance becomes once again equal to the thickness of the oxide layer. There after the value of C GS remains more or less constant. 2. From the given data the break down gate source voltage v GS BD = E BD t gs where E BD = Break down field strength t gs = thickness of the oxide layer. So Let vgs safety. 6-8 v GS BD = = 50V Max be the maximum allowable gate source voltage assuming 50% factor of 1.5 v = v = 50 V gs Max GS BD 50 v gs Max = V 33 Volts We Know that for MOSFET i = g V - V (th) ( ) D fs GS GS ( Vgg -vgs ) did d =gfs v GS =gfs dt dt R C During current rise V gg >> v GS did gfs Vgg dt R C g GS I t = t R C where I = load current. g GS o ri fi g GS o gfsvgg Now From equation (6.4) d Vgg -V g s,io Vgg v DS = dt R C R C g GD g GD Version 2 EE IIT, Kharagpur 28

60 Since V gg >> V gs, I o VD t rr = t fv R gc GD where V D = Load voltage. V gg tri tfi Io C = = t t V g C G S rr fr D fs G D That is current rise and fall times are much shorter than voltage rise and fall times. 4. Referring to Fig 6.9 energy loss during switching occurs during intervals t ri, t fv1, t fv2, t rv2,t rv1, and t fi. For simplicity it will be assumed that t fv2 = t rv2 = 0. Also the rise and fall of i D and v DS will be assumed to be linear. During t ri i =g (v -v (th)) D fs gs gs did d Vgg -vgs =gfs v gs =gfs dt dt (C + C )R di gfsvgg dt (C + C )R D GS GD g I t = (C + C )R o ri GS GD g gfsvgg GS GD g sincev Energy loss during t ri is 2 1 VI D o E = t V Io= (C +C )R 2 2g V ON1 ri D GS GD g fs gg During t fv dv V DS gg -V I = dt C R But V, I = dv dt DS I GD o gs o gs gfs V = gg gs, o g + v (th) I -v (th)- gs R C g GD V t = R C D fv g GD I V o gg -V gs(th)- gfs Energy loss during t fv is E ON2 = 1 tfviov 2 D 2 VD Io = R I 2 V o gg -v gs(th)- g fs Energy loss during Turn on is o g fs gg >> v during current rise gs g C GD Version 2 EE IIT, Kharagpur 29

61 ( ) VIR D o g Io C GS+CGD VC D GD E ON =E ON1 +E ON2 = + 2 gfsv gg ( Vgg -V gs(th) ) From the symmetry of the Turn ON and the Turn OFF operation of MOSFET (i.e. t ri = t fi, t fv = t rv ) E =E ON OFF Total switching energy lass is E sw = E ON + E OFF = 2 E ON Io g fs C VD V GS gg E sw = VD IoR gc GD 1+ + Vgg CGD V (th) I g - Vgg Vgg C I g Substituting the values given P sw = 32 mw, GS o fs PswE sw = VD IoRgCGDfsw 1+ + CGD Vgg gs o fs VD Vgg v (th) I g 1- - V v gs o fs gg gg Version 2 EE IIT, Kharagpur 30

62 Classification of power amplifiers Darlington Amplifier: It consists of two emitter followers in cascaded mode as shown in fig. 1. The overall gain is close to unity. The main advantage of Darlington amplifier is very large increase in input impedence and an equal decrease in output impedancee. Fig. 1 DC Analysis: The first transistor has one V BE drop and second transistor has second V BE drop. The voltage divider produces V TH to the input base. The dc emitter current of the second stage is I E2 = (V TH 2 v BE ) / (R E ) The dc emitter current of the first stage that is the base current of second stage is given by 2 I E1 I E2 / If r' e(2) is neglected then input impedance of second stage is Z in (2) = 2 R R E This is the impedance seen by the first transistor. If r' e (1) is also neglected then the input impedance of 1 becomes. Z in (1) = 1 2 R E which is extremely high because of the products of two betas, so thee approximate input impedance of Darlingtonn amplifier is Z in = R 1 R R 2

63 Output impedance: The Thevenin impedancee at the input is given by R TH = R S R 1 R 2 Similar to single stage common collector amplifier, the output impedance of the two stages z out(1) and z out(2) are given by. Therefore, t he output impedance of the amplifier is very small. Example-1 Design a single stage npnn emitter follower amplifier as shown in fig. 2 with β =60, V BE =0.7V, R sou urce =1 KΩ, and V CC = 12V. Determine the circuit element values for the stage to achieve A i = 10 with a 100 Ω load. Fig. 2 Solution: We must select R 1, R 2 and R E, but we only have two equations. These two equations are specified by the current gain and the placement of the Q-point. As discussed earlier, the best choice for a CE amplifier is to make R C =R load. We could derive a similar result for R E and R loa ad in the CC amplifier. We shall therefore begin by constraining R E to be equal to R load. This yields a third equation,

64 R E = R load = 100 W Now finding the load line slopes, R ac = R E R load =50 W R dc = R E = 100 V Since the amplitude of the input is not specified, we choose the quiescent current to place the Q-point in the center of the ac load line for maximum swing. We now find the value of r' e Since r e is insignificant compared to R E R load, it can be ignored. This is usually the case for emitter follower circuits. Using the equation for current gain we find Everything in this equation is known except R B. We solve for R B withh the result R B = 1500 W V BB is found from the base loop. Continuing with the design as discussedd earlier, we find R 1 = 13.8 K Ω R 2 = 1.68 K Ω The voltage gain of the CC amplifier is approximately unity. The input resistance is given by R in = R B [ β ( R E R load ) ] = 1 kω The outputt resistance is given by

65 The maximum peak to peak symmetrical output swing is given by V out (p-p) 1.8 I CQ (R E R load ) = 7.2 V The power dissipated in the load, P load, and the maximum power required of the transistor, P transist tor, are Example-2 (Capacitor-Coupled CB Design) Design a CB amplifier using an npn transistor as shown in fig. 3 withh β = 100, V CC = 24 V, R load = 2KΩ, R E = 400ΩΩ V BE = 0.7V. Design this amplifier for a voltage gain of 20. Fig. 3 Solution: Since theree are fewer equations than there are unknowns, we need an additional constraint, so we set R C = R load = 2 K Ω Then we have, R ac = 1.40 K Ω and R dc =2.40 KΩ For maximum swing, we set I CQ to

66 We now find that The current gain is given by and input impedance is given by We use the bias equation to find the parameters of the input bias circuitry. The bias resistors are then given by The maximum peak-to-peak undistortedd output voltage is V out (peak-peak) = 1.8 I CQ (R load R C ) = 11.3 V Push pull power amplifiers: Class A current drain: In a class A amplifier shown in fig.1, the dc source V CC C must supply direct current to the voltage divider and the collector circuit.

67 Fig. 1 Assuming a stiff voltage divider circuit, the dc current drain of the voltage divider circuit is I 1 = V CC / (R 1 +R 2 ) In the collector circuit, the dc current drain is I 2 = I CQ In a class A amplifier, the sinusoidal variations in collector current averages to zero. Therefore, whether the ac signal is present or not, the dc source must supply an average current of I S = I 1 + I 2. This is the total dc current drain. The dc source voltage multiplied byy the dc currentt drain gives the ac power supplied to an amplifier. P S = V CC I S Therefore, efficiency of the amplifier, = (P L (max) / P S ) * 100 % Where,, P L (max) = maximum ac load line power. In class A amplifier, there is a wastage of power in resistor R C and R E i.e. I CQ 2 * (R C + R E ). To reduce this wastage of power R C and R E should be made zero. R E cannot be made zero because this will give rise to bias stability problem. R C can also not be made zero becausee effective load resistance gets shorted. This results in more current and no power transfer to the load R L. The R C resistance can, however, be replaced by an inductance whose dc resistance is zero and there is no dc voltage drop across the choke as shown in fig. 1. Since in most application the load is loudspeaker, therefore power amplifier drives the loudspeaker, and the maximum power transfer takes place only when load impedence is equal to the source impedence. If it is not, the loud speaker gets less power. The impedence matching is done withh the help of transformer, as shown in fig. 2.

68 Fig. 2 The ratio of number of turns is so selected that the impedence referred to primary side can be matched with the output impedence of the amplifier. Class B amplifier: The efficiency ( ) of class A amplifier is poor. The reason is that these circuits draw considerablee current from the supply even in the absence of input signals. In class B operation the transistor collector current flows for only 180 of the ac cycle. This implies that the Q-point is located approximately at cutoff on both dc and ac load lines. The advantages of class B operation are Lower transistorr power dissipation Reduced current drain. Push pull circuit:

69 When a transistor operates in class B, it clips off a half cycle. To avoid the resulting distortion, two transistors are used in push pull arrangement. This means thatt one transistorr conducts during positive half cycle and other transistor conducts during negative half cycle. The distortion is low, load power is large and efficiency ( ) is more. fig. 3, shows how a npn and pnp transistor emitter followers are connected in push pull arrangement. The dc & ac equivalent circuit are shown in fig. 4 & fig. 5. The biasing resistors are selected so that Q-point is set at cutoff. This biases the emitter diode of each transistor between 0.6V and 0.7V i.e. I CQ = 0. Because the biasing resistors are equal each emitter diode is biased with the same voltage. As a result half the supply voltage is droppedd across each transistor. V CEQ = V CC C / 2. Fig. 3 Fig. 4 Fig. 5 Since theree is no dc resistance in the collector or emitter circuits, thee dc saturation current is infinite. The dc load line is vertical as shown in fig. 6. The most difficult thing is setting up a stable Q-point at cut off. Any significant increase in V BE with temperature can move the Q-point up the dc load line to dangerously high currents. Ac load line is given by

70 I C(sat) = I CQ + (V CEQ / r E ) V CE (cut off) = V CEQ + I CQ r r E I CQ = 0; V CEQ = V CC / 2 i.e. I C(sat) = V CC / 2R L ( i.e. r E = R L ) V CE (cut off) = V CC / 2. Fig. 6 When either transistor is conducting, that transistor's operating point swings along the ac load line and the operating point of the other transistor remains at cut off. The voltage swing of the conducting transistor can go from cut offf to saturation. In the next half cycle, the other transistor does the same thing. Therefore, PP = V CC Voltage gain of loaded amplifier: A V = R L / (R L + r' e ) Z in (base) (R L + r' e ) Z out = r' e + (r B ) / A P =A V * A A i Without signal the capacitor charges up to V CC / 2 relative to ground. In the positive half cycle of input voltage, the upper transistor conducts and the lower one cut off. The upper transistor acts like an ordinary emitter follower, so that the outpu voltage approximately equals the input voltage. The current flow through R L is such as direct as to make output positive. In the negative half cycle of input voltage, the upper transistor cuts off and the lower transistor conducts. The lower transistor acts like an ordinary emitter follower and produces a load voltage approximately equal to the input voltage (i.e. negative output. Since Q, is off, no current can flow from V CC through Q, but capacitor acts like a battery source and discharges). During either half cycle, the source seess a high input impedence looking into eitherr base and the load sees a low output impedence.

71 Cross over distortion: Fig. 1 shows the ac equivalent circuit of a class B push pull amplifier. Suppose thatt no bias is applied to the emitter diodes. Then the incoming voltage has to rise to about 0.7 V to overcome the barrier potential. Because of this no current flows through Q, when the signal is less than 0.7 V. The action is similar on the other half cycle no current flows in Q2 until ac voltage is more negative the 0.7 V. If no bias is applied the output of class B amplifier looks like as shown in fig. 1. Fig. 1 The signal output is distorted. Because of clipping action between half cycles, it no longer is a sine wave. Since the clipping occurs between the time one transistor cuts off and the time the other comes on, it is called cross over distortion. To eliminate cross over distortion, the slight forward bias must be applied to each emitter diode. This means locating the Q-point slightly above cut off as shown in fig. 2. In fact, this is class AB operation. This means that collector current flows for more than 180 degrees but less than 360. Fig. 2 Class A amplifier introduces non-linear distortion in input wave means elongates one half cycle and compressess one half cycle. This can be reduced by swamping. In this case it can be further reducedd because both half cycles are identical in shape, is given by non-linear distortion is much less than class A. Load power is given by

72 Since the ac output compliance equals the peak-to-peak voltage, thee maximum load power is Where, I 1 = current through biasing resistance. When no signal is present I 2 = I CQ and the current drain is small. But when a signal is present, the current drain increase because the upper collector current becomes large. If the entiree ac load line is used, then the upper transistor has a half sine wave of current through it with a peak value of I C(sat) = V CE EQ / R L The average value of half sine wave is given by The dc power is supplied to the circuit is P S = V CC is under no signal conditions, the dc power is small because the current drain is minimum. But when a signal uses the entire ac load line, the dc power supplied to the circuit reaches a maximum. Biasing a class B amplifier: In class B amplifier, two complement any transistors are required. Because of the series connection, each transistor drops half the supply voltage. To avoid cross over distortion, the Q-point slightly above cut off, with the correct V BE somewhere between 0.6 and 0.7. If there is an increase in V BE by few mv it produces 10 times as much emitter current. Because of this it is difficult to find standard resistors that can produce the correct VBE and it needs an adjustable resistor. The biasing does not solve thermal instability problem. Because for a given collector current, V BE requirement decreases by 2 mv per degree rise in temperature. The voltage divider produces a stiff drive for each diode. Therefore as the temperature increases, the fixed voltage on each emitter diode forces the collector current to increase and this gives rise to thermal run away. When the temperature increases collector current increases, and this is equivalent to Q-point moving up along the vertical dc load line. As the Q-point moves toward higher collector currents, the temperaturee of the transistor increases further reducingg the required V BE.

73 Fig. 3 One way to avoid thermal run away is to use diode bias. It is based on the concept t of current mirror as shown in fig. 3, the base current is much smaller than the current through the resistor and diode. For this reason, I 1 and I 2 are approximately equal. If the diode curve is identical to the V BE curve of the transistorr (V BE, I E ). The diode current equals the emitter and also collector current. Thereforee I 1 is nearly equal to I C. I 1 = I C. The collector current is set by controlling the resistor current. This is called a current mirror. Similarly, pnp transistor can be used as a current mirror. If the V BE curve of the transistor matches the diode curve, the collector equals the resistor current. Diode bias of class B push pull emitter follower relies on two current mirrors as shown in fig. 4.

74 Fig. 4 The upper half is an npn current mirror, and the lower half is a pnp current mirror as shown in fig. 4. For diode bias to be immune to changes in temperature, the diode curve must match the V BE curves of the transistor over a wide temperature range. This is easily done in ICs.

75 Module 3 DC to DC Converters Version 2 EE IIT, Kharagpur 1

76 Lesson 17 Types of Basic DC-DC Converters Version 2 EE IIT, Kharagpur 2

77 Instructional Objectives Study of the following: Three basic types of dc-dc converter circuits buck, boost and buck-boost The expressions for the output voltage in the above circuits, with inductive (R-L) and battery (or back emf = E) load Introduction In the last module (#2) consisting of eight lessons, the various types of circuits used in both single-phase and three-phase ac-dc converters, were discussed in detail. This includes half-wave and full-wave, and also half-controlled and full-controlled ones. In this lesson the first one in this module (#3), firstly, three basic types of dc-dc converter circuits buck, boost and buck-boost, are presented. Then, the expressions for the output voltage in the above circuits, with inductive (R-L) and battery (or back emf = E), i.e., R-L-E, load, are derived, assuming continuous conduction. The different control strategies employed are briefly described. Keywords: DC-DC converter circuits, Thyristor choppers, Buck, boost and buck-boost converters (dc-dc), Step-down (buck) and step-up (boost) choppers, Output voltage and current. DC-DC Converters There are three basic types of dc-dc converter circuits, termed as buck, boost and buck-boost. In all of these circuits, a power device is used as a switch. This device earlier used was a thyristor, which is turned on by a pulse fed at its gate. In all these circuits, the thyristor is connected in series with load to a dc supply, or a positive (forward) voltage is applied between anode and cathode terminals. The thyristor turns off, when the current decreases below the holding current, or a reverse (negative) voltage is applied between anode and cathode terminals. So, a thyristor is to be force-commutated, for which additional circuit is to be used, where another thyristor is often used. Later, GTO s came into the market, which can also be turned off by a negative current fed at its gate, unlike thyristors, requiring proper control circuit. The turnon and turn-off times of GTOs are lower than those of thyristors. So, the frequency used in GTObased choppers can be increased, thus reducing the size of filters. Earlier, dc-dc converters were called choppers, where thyristors or GTOs are used. It may be noted here that buck converter (dc-dc) is called as step-down chopper, whereas boost converter (dc-dc) is a step-up chopper. In the case of chopper, no buck-boost type was used. With the advent of bipolar junction transistor (BJT), which is termed as self-commutated device, it is used as a switch, instead of thyristor, in dc-dc converters. This device (NPN transistor) is switched on by a positive current through the base and emitter, and then switched off by withdrawing the above signal. The collector is connected to a positive voltage. Now-adays, MOSFETs are used as a switching device in low voltage and high current applications. It may be noted that, as the turn-on and turn-off time of MOSFETs are lower as compared to other switching devices, the frequency used for the dc-dc converters using it (MOSFET) is high, thus, reducing the size of filters as stated earlier. These converters are now being used for applications, one of the most important being Switched Mode Power Supply (SMPS). Similarly, when application requires high voltage, Insulated Gate Bi-polar Transistors (IGBT) are preferred over Version 2 EE IIT, Kharagpur 3

78 BJTs, as the turn-on and turn-off times of IGBTs are lower than those of power transistors (BJT), thus the frequency can be increased in the converters using them. So, mostly self-commutated devices of transistor family as described are being increasingly used in dc-dc converters. Buck Converters (dc-dc) A buck converter (dc-dc) is shown in Fig. 17.1a. Only a switch is shown, for which a device as described earlier belonging to transistor family is used. Also a diode (termed as free wheeling) is used to allow the load current to flow through it, when the switch (i.e., a device) is turned off. The load is inductive (R-L) one. In some cases, a battery (or back emf) is connected in series with the load (inductive). Due to the load inductance, the load current must be allowed a path, which is provided by the diode; otherwise, i.e., in the absence of the above diode, the high induced emf of the inductance, as the load current tends to decrease, may cause damage to the switching device. If the switching device used is a thyristor, this circuit is called as a step-down chopper, as the output voltage is normally lower than the input voltage. Similarly, this dc-dc converter is termed as buck one, due to reason given later. + V s - S Switch L + V 0 D F - Fig. 17.1(a): Buck converter (dc-dc) I 0 L O A D v 0 V s V 0 T ON T T OFF t i 0 Fig. 17.1(b): Output voltage and current waveforms t The output voltage and current waveforms of the circuit (Fig. 17.1a) are shown in Fig. 17.1b. The output voltage is same as the input voltage, i.e., v 0 = Vs, when the switch is ON, during the period, T ON t 0. The switch is turned on at t = 0, and then turned off at t = T ON. This is Version 2 EE IIT, Kharagpur 4

79 called ON period. During the next time interval, T t T ON, the output voltage is zero, i.e., v = 0 0, as the diode, DF now conducts. The OFF period is TOFF = T TON, with the time period being T = T ON + T OFF. The frequency is f = 1/ T. With T kept as constant, the average value of the output voltage is, V 0 T TON 1 1 T = v dt = Vs dt = Vs T 0 T T 0 0 ON = k Vs The duty ratio is k = ( TON / T ) = [ TON /( TON + TOFF )], its range being 1.0 k 0.0. Normally, due to turn-on delay of the device used, the duty ratio (k) is not zero, but has some positive value. Similarly, due to requirement of turn-off time of the device, the duty ratio (k) is less than 1.0. So, the range of duty ratio is reduced. It may be noted that the output voltage is lower than the input voltage. Also, the average output voltage increases, as the duty ratio is increased. So, a variable dc output voltage is obtained from a constant dc input voltage. The load current is assumed to be continuous as shown in Fig. 17.1b. The load current increases in the ON period, as the input voltage appears across the load, and it (load current) decreases in the OFF period, as it flows in the diode, but is positive at the end of the time period, T. Boost Converters (dc-dc) A boost converter (dc-dc) is shown in Fig. 17.2a. Only a switch is shown, for which a device belonging to transistor family is generally used. Also, a diode is used in series with the load. The load is of the same type as given earlier. The inductance of the load is small. An inductance, L is assumed in series with the input supply. The position of the switch and diode in this circuit may be noted, as compared to their position in the buck converter (Fig. 17.1a). + I s L D I + 0 V s - S V 0 Switch - Fig. 17.2(a): Boost converter (dc-dc) L O A D I 2 I 1 0 T ON T 2T T OFF Fig. 17.2(b): Waveforms of source current (i S ) Version 2 EE IIT, Kharagpur 5

80 The operation of the circuit is explained. Firstly, the switch, S (i.e., the device) is put ON (or turned ON) during the period, t 0, the ON period being T. The output voltage is T ON zero ( v = 0 0 ), if no battery (back emf) is connected in series with the load, and also as stated earlier, the load inductance is small. The current from the source ( i ) flows in the inductance L. The value of current increases linearly with time in this interval, with ( di dt) being positive. As the current through L increases, the polarity of the induced emf is taken as say, positive, the left hand side of L being +ve. The equation for the circuit is, dis dis Vs Vs = L or, = dt dt L The switch, S is put OFF during the period, T t s ON, the OFF period being TOFF = T T ON. ( T = T ON + TOFF ) is the time period. As the current through L decreases, with its direction being in the same direction as shown (same as in the earlier case), the induced emf reverses, the left hand side of L being -ve. So, the induced emf (taken as ve in the equation given later) is added with the supply voltage, being of the same polarity, thus, keeping the current ( i s = i 0 ) in the same direction. The current ( i = i s 0 ) decreases linearly in the time interval,, as the output voltage is assumed to be nearly constant at v, with ( i d t ) being TOFF 0 V0 T ON negative, as V s < V 0, which is derived later. The equation for the circuit is, dis dis ( Vs V0 ) Vs = V 0 + L or, = dt dt L The source current waveform is shown in Fig. 17.2b. As stated earlier, the current varies linearly from I1 ( I min ) to I 2 ( I max ) during the time interval, TON. So, using the expression for di s dt during this time interval, I 2 I1 = I max I min = ( V s / L) T ON. Similarly, the current varies linearly from I 2 ( I max ) to I1 ( I min ) during the time interval, TOFF. So, using the expression for di s dt during this time interval, I 2 I1 = I max I min = [( V0 Vs )/ L] TOFF. Equating the two equations, ( V s / L ) TON = [( V 0 V s )/ L ] TOFF, from which the average value of the output voltage is, T T 1 1 V = = = ( ) 0 = Vs Vs Vs Vs TOFF T TON 1 TON / T 1 k The time period is T = T ON + T OFF, and the duty ratio is, k = T / T = T / T + T )], with its range as 1.0 k 0.0. The ON time interval is ( ) ( ON [ ON ON OFF d s T ON = k T. As stated in the previous case, the range of k is reduced. This is, because the minimum value is higher than the minimum (0.0), and the maximum value is lower than the maximum (1.0), for reasons given there, which are also valid here. As shown, the source current is assumed to be continuous. The expression for the output voltage can be obtained by using other procedures. In this case, the output voltage is higher than the input voltage, as contrasted with the previous case of buck converter (dc-dc). So, this is called boost converter (dc-dc), when a self- Version 2 EE IIT, Kharagpur 6

81 commutated device is used as a switch. Instead, if thyristor is used in its place, this is termed as step-up chopper. The variation (range) of the output voltage can be easily computed. Buck-Boost Converters (dc-dc) A buck-boost converter (dc-dc) is shown in Fig Only a switch is shown, for which a device belonging to transistor family is generally used. Also, a diode is used in series with the load. The connection of the diode may be noted, as compared with its connection in a boost converter (Fig. 17.2a). The inductor, L is connected in parallel after the switch and before the diode. The load is of the same type as given earlier. A capacitor, C is connected in parallel with the load. The polarity of the output voltage is opposite to that of input voltage here. When the switch, S is put ON, the supply current ( is ) flows through the path, Vs, S and L, during the time interval, TON. The currents through both source and inductor ( il ) increase and are same, with ( d i L d t ) being positive. The polarity of the induced voltage is same as that of the input voltage. The equation for the circuit is, dil di V Vs = L or, L s = dt dt L + I s S Switch I 0 - V s L I L L O A D V 0 C - Fig. 17.3(a): Buck-boost converter (dc-dc) + I L2 I L1 T ON T 2T T OFF Fig. 17.3(b): Inductor current (i L ) waveform Then, the switch, S is put OFF. The inductor current tends to decrease, with the polarity of the induced emf reversing. ( i d t ) is negative now, the polarity of the output voltage, d L being opposite to that of the input voltage, combination of load & C, and diode D, during the time interval, remains nearly constant, as the capacitor is connected across the load. V s. The path of the current is through L, parallel T OFF V 0. The output voltage Version 2 EE IIT, Kharagpur 7

82 The equation for the circuit is, di L L di V = V 0 or, L = 0 dt dt L The inductor current waveform is shown in Fig. 17.3b. As stated earlier, the current varies linearly from to I during the time interval,. Note that and are the minimum I L1 L2 TON I L1 I L 2 and maximum values of the inductor current respectively. So, using the expression for I I V / L T. during this time interval, L L 1 ( s ) ON 2 = Similarly, the current varies linearly from to I during the time interval, T. So, using I L2 L1 the expression for di L dt during this time interval, I L2 I L1 = ( V0 / L) TOFF. Equating the two equations, ( V s / L ) TON = ( V 0 / L ) TOFF, from which the average value of the output voltage is, TON TON ( TON / T ) k V = = = ( ) 0 = Vs Vs Vs Vs TOFF T TON 1 TON / T 1 k The time period is T = T ON + T OFF, and the duty ratio is, k = ( TON / T ) = [ TON /( TON + TOFF )]. The ON time interval is T ON = k T. It may be observed that, for the range 0 k > 0.5, the output voltage is lower than the input voltage, thus, making it a buck converter (dc-dc). For the range 0.5 > k 1.0, the output voltage is higher than the input voltage, thus, making it a boost converter (dc-dc). For k = 0.5, the output voltage is equal to the input voltage. So, this circuit can be termed as a buck-boost converter. Also it may be called as step-up/down chopper. It may be noted that the inductor current is assumed to be continuous. The range of k is somewhat reduced due to the reasons given earlier. The expression for the output voltage can be obtained by using other procedures. Control Strategies In all cases, it is shown that the average value of the output voltage can be varied. The two types of control strategies (schemes) are employed in all cases. These are: (a) Time-ratio control, and (b) Current limit control. Time-ratio Control In the time ratio control the value of the duty ratio, k = T / ON T is varied. There are two ways, which are constant frequency operation, and variable frequency operation. Constant Frequency Operation OFF di L dt In this control strategy, the ON time, TON is varied, keeping the frequency ( f = 1/ T ), or time period T constant. This is also called as pulse width modulation control (PWM). Two cases with duty ratios, k as (a) 0.25 (25%), and (b) 0.75 (75%) are shown in Fig Hence, the output voltage can be varied by varying ON time,. T ON Version 2 EE IIT, Kharagpur 8

83 Load-voltage v 0 T ON T OFF V 0 k = 0.25 T t v 0 V 0 T ON T OFF k = 0.75 T t Fig. 17.4: Pulse-width modulation control (constant frequency) Variable Frequency Operation In this control strategy, the frequency ( f = 1/ T ), or time period T is varied, keeping either (a) the ON time, T constant, or (b) the OFF time, T constant. This is also called as ON frequency modulation control. Two cases with (a) the ON time, constant, and (b) the OFF time, T constant, with variable frequency or time period ( T ), are shown in Fig The OFF output voltage can be varied in both cases, with the change in duty ratio, k = T / ON T. OFF T ON Version 2 EE IIT, Kharagpur 9

84 v 0 T ON k = 0.25 t v 0 T ON T T OFF (a) Constant T ON k = 0.75 t v 0 T OFF T T ON k = 0.25 t v 0 Load voltage T OFF T ON k = 0.75 T t (b) Constant T OFF Fig. 17.5: Output voltage waveforms for variable frequency system There are major disadvantages in this control strategy. These are: (a) The frequency has to be varied over a wide range for the control of output voltage in frequency modulation. Filter design for such wide frequency variation is, therefore, quite difficult. (b) For the control of a duty ratio, frequency variation would be wide. As such, there is a possibly of interference with systems using certain frequencies, such as signaling and telephone line, in frequency modulation technique. (c) The large OFF time in frequency modulation technique, may make the load current discontinuous, which is undesirable. Thus, the constant frequency system using PWM is the preferred scheme for dc-dc converters (choppers). Version 2 EE IIT, Kharagpur 10

85 Current Limit Control As can be observed from the current waveforms for the types of dc-dc converters described earlier, the current changes between the maximum and minimum values, if it (current) is continuous. In the current limit control strategy, the switch in dc-dc converter (chopper) is turned ON and OFF, so that the current is maintained between two (upper and lower) limits. When the current exceed upper (maximum) limit, the switch is turned OFF. During OFF period, the current freewheels in say, buck converter (dc-dc) through the diode, D F, and decreases exponentially. When it reaches lower (minimum) limit, the switch is turned ON. This type of control is possible, either with constant frequency, or constant ON time, T ON. This is used only, when the load has energy storage elements, i.e. inductance, L. The reference values are load current or load voltage. This is shown in Fig In this case, the current is continuous, varying between I max and I min, which decides the frequency used for switching. The ripple in the load current can be reduced, if the difference between the upper and lower limits is reduced, thereby making it minimum. This in turn increases the frequency, thereby increasing the switching losses. i 0 I max I min t v 0 T ON T OFF T Fig. 17.6: Current limit control t In this lesson, first one in this module (#3), the three basic circuits buck, boost and buckboost, of dc-dc converters (choppers) are presented, along with the operation and the derivation of the expressions for the output voltage in each case, assuming continuous conduction. The different strategies employed for their control are discussed. In the next lesson second one, the expression for the maximum and currents for continuous conduction in buck dc-dc converter will be derived. Version 2 EE IIT, Kharagpur 11

86 Operational Amplifiers: The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MH Z to which feedback is added to control its overall response characteristicc i.e. gain and bandwidth. The op-amp exhibits the gain down to zero frequency. Such direct coupled (dc) amplifiers do not use blocking (coupling and by pass) capacitors since these would reduce the amplification to zero at zero frequency. Large by pass capacitors may be used but it is not possible to fabricate large capacitors onn a IC chip. The capacitors fabricated are usually less than 20 pf. Transistor, diodes and resistors are also fabricated on the same chip. Differential Amplifiers: Differential amplifier is a basic building block of an op-amp. The function of a differential amplifier is to amplify the difference between two input signals. How the in fig. 1. differential amplifier is developed? Let us consider two emitter-biased circuits as shown Fig. 1 The two transistors Q 1 and Q 2 have identical characteristics. The resistances of the circuits are equal, i.e. R E1 = R E2, R C1 = R C2 and the magnitude of +V CC is equall to the magnitude of V EE. These voltages are measured with respect to ground. To make a differential amplifier, the two circuits are connected as shown in fig. 1. The two + and V EE E supply terminals are made common because they are same. The two emitters are also connected and the parallel combination of RE1 and R E2 iss replaced by a resistance R E. The two input signals v 1 & v 2 are applied at the base of Q 1 and at the base of Q 2. The output voltage is taken between two collectors. The collector resistances are equal and therefore denoted by R C = R C1 = RC2. +V CC

87 Ideally, the output voltage is zero when the two inputs are equal. When v 1 is greater then v 2 the output voltage with the polarity shown appears. When v 1 is less than v 2, the output voltage has the opposite polarity. The differential amplifiers are of different configurations. The four differential amplifier configurations are following: Dual input, balanced output differential amplifier. Dual input, unbalanced output differential amplifier. Single input balanced output differential amplifier. Single input unbalanced output differential amplifier.

88 Fig. 2 These configurations are shown in fig. 2, and are definedd by numberr of input signals used and the way an output voltage is measured. If use two input signals, the configurationn is said to be dual input, otherwisee it is a single input configuration. On the other hand, if the output voltage is measured between two collectors, it is referred to as a balanced outpu because both the collectors are at the same dc potential w.r.t. ground. If the output is measured at one of the collectors w.r.t. ground, the configuration is called an unbalanced output. A multistage amplifier with a desired gain can be obtained using direct connection between successive stages of differential amplifiers. The advantage of direct coupling is that it removes the lower cut off frequency imposed by the coupling capacitors, and they are therefore, capable of amplifying dc as well as ac input signals. Differential Input Resistance: Differential input resistance is defined as the equivalent resistance that would be measured at either input terminal with the other terminal grounded. This means that the input resistance R i1 seen from the input signal source v 1 is determined with the signal source v 2 set at zero. Similarly, the input signal v 1 is set at zero to determine the input resistance R i2 seen from the input signal source v2. 2 Resistancee R S1 and R S 2 are ignored because they are very small. Substituting i e1, Similarly,

89 The factor of 2 arisess because the r e ' of each transistor is in series. To get very high input impedance with differential amplifier is to use Darlingtonn transistors. Another ways is to use FET. Output Resistance: Output resistance is defined as the equivalent resistance that would be measured at output terminal with respect to ground. Therefore, the output resistance R O1 1 measured between collector C 1 and ground is equal to that of the collector resistance R C. Similarly the outputt resistance R O2 measured at C 2 with respect to ground is equal to that of the collector resistor R C C. R O1 = RO2 = R C (E-5) The current gain of the differential amplifier is undefined. Like CE amplifier the differential amplifier is a small signal amplifier. It is generally used as a voltage amplifier and not as current or power amplifier. Example - 1 The following specifications are given for the dual input,, balanced-output differential amplifier: R C = 2.2 kω, R B = 4. 7 kω, R in 1 = R in 2 = 50Ω, +V CC = 10V, -V EE = -10 V, β dc =100 and V BE = 0.715V. Solution: I CQ = ma V CEQ =8.54V a. Determine the voltage gain. b. Determine the input resistancee c. Determine the output resistance. The ac emitter resistance (a). The parameters of the amplifiers are same as discussed in example-1 of lecture-1. The operating point of the two transistors obtained in lecture-1 are given below Therefore, substituting the knownn values in voltage gain equation (E-2), we obtain

90 b). The input resistance seen from each input source is given by (E-3) and (E-4): (c) The output resistance seen looking back into the circuit from each of the two output terminals is given by (E-5) R o1 = R o2 = 2.2 k Ω Example - 2 For the dual input, balanced output differential amplifier r of Example-1: a. Determine the output voltage (v o ) if v in 1 = 50mV peak to peak (pp) at 1 khz and v in 2 = 20 mv pp at 1 khz. b. What is the maximum peal to peak outputt voltage without clipping? Solution: (a) In Example-1 we have determined the voltage gain of the dual input, balanced output differential amplifier. Substituting this voltage gain (A d = 86.96) and given values of input voltages in (E-1), we get (b) Note that in case of dual input, balanced output difference amplifier, the output voltage v o is measured across the collector. Therefore, to calculate thee maximum peak to peak output voltage, we need to determinee the voltage drop acrosss each collector resistor: Substituting I C = I CQ = ma, we get This means that the maximum change in voltage across each collector resistor is ± 2.17 (ideally) or 4.34 V PP. In other words, the maximum peak to peak output voltage with out clipping is (2) (4.34) = 8.68 V PP.

91 Module 1 Power Semiconductor Devices Version 2 EE IIT, Kharagpur 1

92 Lesson 1 Power Electronics Version 2 EE IIT, Kharagpur 2

93 Introduction This lesson provides the reader the following: (i) (ii) (iii) (iv) (v) Create an awareness of the general nature of Power electronic equipment; Brief idea about topics of study involved, The key features of the principal Power Electronic Devices; An idea about which device to choose for a particular application. A few issues like base drive and protection of PE devices and equipment common to most varieties. Power Electronics is the art of converting electrical energy from one form to another in an efficient, clean, compact, and robust manner for convenient utilisation. A passenger lift in a modern building equipped with a Variable-Voltage-Variable-Speed induction-machine drive offers a comfortable ride and stops exactly at the floor level. Behind the scene it consumes less power with reduced stresses on the motor and corruption of the utility mains. Fig. 1.1 The block diagram of a typical Power Electronic converter Power Electronics involves the study of Power semiconductor devices - their physics, characteristics, drive requirements and their protection for optimum utilisation of their capacities, Power converter topologies involving them, Control strategies of the converters, Digital, analogue and microelectronics involved, Capacitive and magnetic energy storage elements, Rotating and static electrical devices, Quality of waveforms generated, Electro Magnetic and Radio Frequency Interference, Version 2 EE IIT, Kharagpur 3

94 Thermal Management The typical converter in Fig. 1.1 illustrates the multidisciplinary nature of this subject. How is Power electronics distinct from linear electronics? It is not primarily in their power handling capacities. While power management IC's in mobile sets working on Power Electronic principles are meant to handle only a few milliwatts, large linear audio amplifiers are rated at a few thousand watts. The utilisation of the Bipolar junction transistor, Fig. 1.2 in the two types of amplifiers best symbolises the difference. In Power Electronics all devices are operated in the switching mode - either 'FULLY-ON' or 'FULLY-OFF' states. The linear amplifier concentrates on fidelity in signal amplification, requiring transistors to operate strictly in the linear (active) zone, Fig 1.3. Saturation and cutoff zones in the V CE - I C plane are avoided. In a Power electronic switching amplifier, only those areas in the V CE - I C plane which have been skirted above, are suitable. Onstate dissipation is minimum if the device is in saturation (or quasi-saturation for optimising other losses). In the off-state also, losses are minimum if the BJT is reverse biased. A BJT switch will try to traverse the active zone as fast as possible to minimise switching losses. Fig. 1.2 Typical Bipolar transistor based (a) linear (common emitter) (voltage) amplifier stage and (b) switching (power) amplifier Version 2 EE IIT, Kharagpur 4

95 Fig 1.3 Operating zones for operating a Bipolar Junction Transistor as a linear and a switching amplifier Linear operation Active zone selected: Good linearity between input/output Saturation & cut-off zones avoided: poor linearity Transistor biased to operate around quiescent point Common emitter, Common collector, common base modes Output transistor barely protected Utilisation of transistor rating of secondary importance Switching operation Active zone avoided : High losses, encountered only during transients Saturation & cut-off (negative bias) zones selected: low losses No concept of quiescent point Transistor driven directly at base - emitter and load either on collector or emitter Switching-Aid-Network (SAN) and other protection to main transistor Utilisation of transistor rating optimised Version 2 EE IIT, Kharagpur 5

96 An example illustrating the linear and switching solutions to a power supply specification will emphasise the difference. Spec: Input : 230 V, 50 Hz, Output: 12 V regulated DC, 20 W Series regulator - high losses Ferrite core HF transfr: Light, efficient 230 V 230 V Line freq transformer: heavy, lossy (a) High-freq Duty-ratio (ON/OFF) control - low losses Fig. 1.4 (a) A Linear regulator and (b) a switching regulator solution of the specification above The linear solution, Fig. 1.4 (a), to this quite common specification would first step down the supply voltage to V through a power frequency transformer. The output would be rectified using Power frequency diodes, electrolytic capacitor filter and then series regulated using a chip or a audio power transistor. The tantalum capacitor filter would follow. The balance of the voltage between the output of the rectifier and the output drops across the regulator device which also carries the full load current. The power loss is therefore considerable. Also, the stepdown iron-core transformer is both heavy, and lossy. However, only twice-line-frequency ripples appear at the output and material cost and technical know-how required is low. In the switching solution Fig. 1.4 (b) using a MOSFET driven flyback converter, first the line voltage is rectified and then isolated, stepped-down and regulated. A ferrite-core high-frequency (HF) transformer is used. Losses are negligible compared to the first solution and the converter is extremely light. However significant high frequency (related to the switching frequency) noise appear at the output which can only be minimised through the use of costly 'grass' capacitors. Power Semiconductor device - history Power electronics and converters utilizing them made a head start when the first device the Silicon Controlled Rectifier was proposed by Bell Labs and commercially produced by General Electric in the earlier fifties. The Mercury Arc Rectifiers were well in use by that time and the robust and compact SCR first started replacing it in the rectifiers and cycloconverters. The necessity arose of extending the application of the SCR beyond the line-commutated mode of action, which called for external measures to circumvent its turn-off incapability via its control terminals. Various turn-off schemes were proposed and their classification was suggested but it became increasingly obvious that a device with turn-off capability was desirable, which would permit it a wider application. The turn-off networks and aids were impractical at higher powers. The Bipolar transistor, which had by the sixties been developed to handle a few tens of amperes and block a few hundred volts, arrived as the first competitor to the SCR. It is superior to the SCR in its turn-off capability, which could be exercised via its control terminals. This permitted the replacement of the SCR in all forced-commutated inverters and choppers. However, the gain (power) of the SCR is a few decades superior to that of the Bipolar transistor (b) Version 2 EE IIT, Kharagpur 6

97 and the high base currents required to switch the Bipolar spawned the Darlington. Three or more stage Darlingtons are available as a single chip complete with accessories for its convenient drive. Higher operating frequencies were obtainable with a discrete Bipolars compared to the 'fast' inverter-grade SCRs permitting reduction of filter components. But the Darlington's operating frequency had to be reduced to permit a sequential turn-off of the drivers and the main transistor. Further, the incapability of the Bipolar to block reverse voltages restricted its use. The Power MOSFET burst into the scene commercially near the end seventies. This device also represents the first successful marriage between modern integrated circuit and discrete power semiconductor manufacturing technologies. Its voltage drive capability giving it again a higher gain, the ease of its paralleling and most importantly the much higher operating frequencies reaching upto a few MHz saw it replacing the Bipolar also at the sub-10 KW range mainly for SMPS type of applications. Extension of VLSI manufacturing facilities for the MOSFET reduced its price vis-à-vis the Bipolar also. However, being a majority carrier device its on-state voltage is dictated by the R DS(ON) of the device, which in turn is proportional to about VDSS 2.3 rating of the MOSFET. Consequently, high-voltage MOSFETS are not commercially viable. Improvements were being tried out on the SCR regarding its turn-off capability mostly by reducing the turn-on gain. Different versions of the Gate-turn-off device, the Gate turn-off Thyristor (GTO), were proposed by various manufacturers - each advocating their own symbol for the device. The requirement for an extremely high turn-off control current via the gate and the comparatively higher cost of the device restricted its application only to inverters rated above a few hundred KVA. The lookout for a more efficient, cheap, fast and robust turn-off-able device proceeded in different directions with MOS drives for both the basic thysistor and the Bipolar. The Insulated Gate Bipolar Transistor (IGBT) basically a MOSFET driven Bipolar from its terminal characteristics has been a successful proposition with devices being made available at about 4 KV and 4 KA. Its switching frequency of about 25 KHz and ease of connection and drive saw it totally removing the Bipolar from practically all applications. Industrially, only the MOSFET has been able to continue in the sub 10 KVA range primarily because of its high switching frequency. The IGBT has also pushed up the GTO to applications above 2-5 MVA. Subsequent developments in converter topologies especially the three-level inverter permitted use of the IGBT in converters of 5 MVA range. However at ratings above that the GTO (6KV/6KA device of Mitsubishi) based converters had some space. Only SCR based converters are possible at the highest range where line-commutated or load-commutated converters were the only solution. The surge current, the peak repetition voltage and I 2 t ratings are applicable only to the thyristors making them more robust, specially thermally, than the transistors of all varieties. 1200V Version 3 ASIPM Presently there are few hybrid devices and Intelligent Power Modules (IPM) are marketed by some manufacturers. The IPMs have already gathered wide acceptance. The 4500 V, 1200 A Version 2 EE IIT, Kharagpur 7

98 IEGT (injection-enhanced gate transistor) of Toshiba or the 6000 V, 3500 A IGCT (Integrated Gate Commutated Thyristors) of ABB which are promising at the higher power ranges. However these new devices must prove themselves before they are accepted by the industry at large. Silicon carbide is a wide band gap semiconductor with an energy band gap wider than about 2 ev that possesses extremely high thermal, chemical, and mechanical stability. Silicon carbide is the only wide band gap semiconductor among gallium nitride (GaN, E G = 3.4 ev), aluminum nitride (AlN, E G = 6.2 ev), and silicon carbide that possesses a high-quality native oxide suitable for use as an MOS insulator in electronic devices The breakdown field in SiC is about 8 times higher than in silicon. This is important for high-voltage power switching transistors. For example, a device of a given size in SiC will have a blocking voltage 8 times higher than the same device in silicon. More importantly, the on-resistance of the SiC device will be about two decades lower than the silicon device. Consequently, the efficiency of the power converter is higher. In addition, SiC-based semiconductor switches can operate at high temperatures (~600C) without much change in their electrical properties. Thus the converter has a higher reliability. Reduced losses and allowable higher operating temperatures result in smaller heatsink size. Moreover, the high frequency operating capability of SiC converters lowers the filtering requirement and the filter size. As a result, they are compact, light, reliable, and efficient and have a high power density. These qualities satisfy the requirements of power converters for most applications and they are expected to be the devices of the future. Ratings have been progressively increasing for all devices while the newer devices offer substantially better performance. With the SCR and the pin-diodes, so called because of the sandwiched intrinsic i -layer between the p and n layers, having mostly line-commutated converter applications, emphasis was mostly on their static characteristics - forward and reverse voltage blocking, current carrying and over-current ratings, on-state forward voltage etc and also on issues like paralleling and series operation of the devices. As the operating speeds of the devices increased, the dynamic (switching) characteristics of the devices assumed greater importance as most of the dissipation was during these transients. Attention turned to the development of efficient drive networks and protection techniques which were found to enhance the performance of the devices and their peak power handling capacities. Issues related to paralleling were resolved by the system designer within the device itself like in MOSFETS, while the converter topology was required to take care of their series operation as in multi-level converters. The range of power devices thus developed over the last few decades can be represented as a tree, Fig. 1.5, on the basis of their controllability and other dominant features. Version 2 EE IIT, Kharagpur 8

99 POWER SEMICONDUCTOR DEVICES UNCONTROLLED CONTROLLED RECTIFIERS ACCESSORIES REGENERATIVE NON-REGENERATIVE INTEGRATED POWER SILICON DIODES FREDS SCHOTTKY DIAC Zenner MOV SCR TRIAC GTO BJT MOSFET IGBT IGCT PIC INTELLIGENT POWER MODULES Fig. 1.5 Power semiconductor device variety Power Diodes di F /dt t 0 t 1 t 2 SNAPPY SOFT Δ t o Q1 Q2 I RM Silicon Power diodes are the successors of Selenium rectifiers having significantly improved forward characteristics and voltage ratings. They are classified mainly by their turn-off (dynamic) characteristics Fig The minority carriers in the diodes require finite time - t rr (reverse recovery time) to recombine with opposite charges and neutralise. Large values of Q rr (= Q 1 + Q 2 ) - the charge to be dissipated as a negative current when the and diode turns off and t rr (= t 2 - t 0 ) - the time it takes to regain its blocking features, impose strong current stresses on the controlled device in series. Also a 'snappy' type of recovery of the diode effects high di/dt voltages on all associated power device in the converter because of load or stray inductances present in the network. There are broadly three types of diodes used in Power electronic applications: Line-frequency diodes: These PIN diodes with general-purpose rectifier type applications, are available at the highest voltage (~5kV) and current ratings (~5kA) and have excellent overcurrent (surge rating about six times average current rating) and surge-voltage withstand capability. They have relatively large Q rr and t rr specifications. V RM Fig. 1.6 Typical turn-off dynamics of a soft and a 'snappy' diode' Version 2 EE IIT, Kharagpur 9

100 Fast recovery diodes: Fast recovery diffused diodes and fast recovery epitaxial diodes, FRED's, have significantly lower Q rr and trr (~ 1.0 sec). They are available at high powers and are mainly used in association with fast controlled-devices as free-wheeling or DC-DC choppers and rectifier applications. Fast recovery diodes also find application in induction heating, UPS and traction. Schottky rectifiers: These are the fastest rectifiers being majority carrier devices without any Q rr.. However, they are available with voltage ratings up to a hundred volts only though current ratings may be high. Their conduction voltages specifications are excellent (~0.2V). The freedom from minority carrier recovery permits reduced snubber requirements. Schottky diodes face no competition in low voltage SPMS applications and in instrumentation. Silicon Controlled Rectifier (SCR) The Silicon Controlled Rectifier is the most popular of the thyristor family of four layer regenerative devices. It is normally turned on by the application of a gate pulse when a forward bias voltage is present at the main terminals. However, being regenerative or 'latching', it cannot be turned off via the gate terminals specially at the extremely high amplification factor of the gate. There are two main types of SCR's. Converter grade or Phase Control thyristors These devices are the work horses of the Power Electronics. They are turned off by natural (line) commutation and are reverse biased at least for a few milliseconds subsequent to a conduction period. No fast switching feature is desired of these devices. They are available at voltage ratings in excess of 5 KV starting from about 50 V and current ratings of about 5 KA. The largest converters for HVDC transmission are built with series-parallel combination of these devices. Conduction voltages are device voltage rating dependent and range between 1.5 V (600V) to about 3.0 V (+5 KV). These devices are unsuitable for any 'forced-commutated' circuit requiring unwieldy large commutation components. The dynamic di/dt and dv/dt capabilities of the SCR have vastly improved over the years borrowing emitter shorting and other techniques adopted for the faster variety. The requirement for hard gate drives and di/dt limting inductors have been eliminated in the process. Inverter grade thyristors: Turn-off times of these thyristors range from about 5 to 50 μsecs when hard switched. They are thus called fast or 'inverter grade' SCR's. The SCR's are mainly used in circuits that are operated on DC supplies and no alternating voltage is available to turn them off. Commutation networks have to be added to the basic converter only to turn-off the SCR's. The efficiency, size and weight of these networks are directly related to the turn-off time, t q of the SCR. The commutation circuits utilised resonant networks or charged capacitors. Quite a few commutation networks were designed and some like the McMurray-Bedford became widely accepted. Asymmetrical, light-activated, reverse conducting SCR's Quite a few varieties of the basic SCR have been proposed for specific applications. The Asymmetrical thyristor is convenient when reactive powers are involved and the light activated SCR assists in paralleling or series operation. Version 2 EE IIT, Kharagpur 10

101 MOSFET The Power MOSFET technology has mostly reached maturity and is the most popular device for SMPS, lighting ballast type of application where high switching frequencies are desired but operating voltages are low. Being a voltage fed, majority carrier device (resistive behaviour) with a typically rectangular Safe Operating Area, it can be conveniently utilized. Utilising shared manufacturing processes, comparative costs of MOSFETs are attractive. For low frequency applications, where the currents drawn by the equivalent capacitances across its terminals are small, it can also be driven directly by integrated circuits. These capacitances are the main hindrance to operating the MOSFETS at speeds of several MHz. The resistive characteristics of its main terminals permit easy paralleling externally also. At high current low voltage applications the MOSFET offers best conduction voltage specifications as the R DS(ON) specification is current rating dependent. However, the inferior features of the inherent antiparallel diode and its higher conduction losses at power frequencies and voltage levels restrict its wider application. The IGBT It is a voltage controlled four-layer device with the advantages of the MOSFET driver and the Bipolar Main terminal. IGBTs can be classified as punch-through (PT) and non-punchthrough (NPT) structures. In the punch-through IGBT, a better trade-off between the forward voltage drop and turn-off time can be achieved. Punch-through IGBTs are available up to about 1200 V. NPT IGBTs of up to about 4 KV have been reported in literature and they are more robust than PT IGBTs particularly under short circuit conditions. However they have a higher forward voltage drop than the PT IGBTs. Its switching times can be controlled by suitably shaping the drive signal. This gives the IGBT a number of advantages: it does not require protective circuits, it can be connected in parallel without difficulty, and series connection is possible without dv/dt snubbers. The IGBT is presently one of the most popular device in view of its wide ratings, switching speed of about 100 KHz a easy voltage drive and a square Safe Operating Area devoid of a Second Breakdown region. The GTO The GTO is a power switching device that can be turned on by a short pulse of gate current and turned off by a reverse gate pulse. This reverse gate current amplitude is dependent on the anode current to be turned off. Hence there is no need for an external commutation circuit to turn it off. Because turn-off is provided by bypassing carriers directly to the gate circuit, its turn-off time is short, thus giving it more capability for highfrequency operation than thyristors. The GTO symbol and turn-off characteristics are shown in Fig GTOs have the I 2 t withstand capability and hence can be protected by semiconductor fuses. For reliable operation of GTOs, the critical aspects are proper design of the gate turn-off circuit and the snubber circuit. Power Converter Topologies A Power Electronic Converter processes the available form to another having a different frequency and/or voltage magnitude. There can be four basic types of converters depending upon the function performed: Version 2 EE IIT, Kharagpur 11

102 CONVERSION FROM/TO NAME FUNCTION SYMBOL DC to DC Chopper Constant to variable DC or variable to constant DC DC to AC Inverter DC to AC of desired voltage and frequency ~ AC to DC Rectifier AC to unipolar (DC) current ~ AC to AC Cycloconverter, AC-PAC, Matrix converter AC of desired frequency and/or magnitude from generally line ~ AC ~ Base / gate drive circuit All discrete controlled devices, regenerative or otherwise have three terminals. Two of these are the Main Terminals. One of the Main Terminals and the third form the Control Terminal. The amplification factor of all the devices (barring the now practically obsolete BJT) are quite high, though turn-on gain is not equal to turn-off gain. The drive circuit is required to satisfy the control terminal characteristics to efficiently tun-on each of the devices of the converter, turn them off, if possible, again optimally and also to protect the device against faults, mostly overcurrents. Being driven by a common controller, the drives must also be isolated from each other as the potentials of the Main Terminal which doubles as a Control terminal are different at various locations of the converter. Gate-turn-off-able devices require precise gate drive waveform for optimal switching. This necessitates a wave-shaping amplifier. This amplifier is located after the isolation stage. Thus separate isolated power supplies are also required for each Power device in the converter (the ones having a common Control Terminal - say the Emitter in an IGBT - may require a few less). There are functionally two types of isolators: the pulse transformer which can transmit after isolation, in a multi-device converter, both the un-shaped signal and power and optical isolators which transmit only the signal. The former is sufficient for a SCR without isolated power supplies at the secondary. The latter is a must for practically all other devices. Fig. 1.7 illustrates to typical drive circuits for an IGBT and an SCR. Version 2 EE IIT, Kharagpur 12

103 IGBT V ref COMPARATOR TIMER Fig. 1.7 Simple gate-drive and protection circuit for a stand-alone IGBT and a SCR Protection of Power devices and converters Power electronic converters often operate from the utility mains and are exposed to the disturbances associated with it. Even otherwise, the transients associated with switching circuits and faults that occur at the load point stress converters and devices. Consequently, several protection schemes must be incorporated in a converter. It is necessary to protect both the Main Terminals and the control terminals. Some of these techniques are common for all devices and converters. However, differences in essential features of devices call for special protection schemes particular for those devices. The IGBT must be protected against latching, and similarly the GTO's turn-off drive is to be disabled if the Anode current exceeds the maximum permissible turn-off-able current specification. Power semiconductor devices are commonly protected against: 1. Over-current; 2. di/dt; 3. Voltage spike or over-voltage; 4. dv/dt ; 5. Gate-under voltage; 6. Over voltage at gate; 7. Excessive temperature rise; 8. Electro-static discharge; Semiconductor devices of all types exhibit similar responses to most of the stresses, however there are marked differences. The SCR is the most robust device on practically all counts. That it has an I 2 t rating is proof that its internal thermal capacities are excellent. A HRC fuse, suitably selected, and in co-ordination with fast circuit breakers would mostly protect it. This sometimes becomes a curse when the cost of the fuse becomes exorbitant. All transistors, specially the BJT and the IGBT is actively protected (without any operating cost!) by sensing the Main Terminal voltage, as shown in Fig This voltage is related to the current carried by the device. Further, the transistors permit designed gate current waveforms to minimise voltage spikes as a consequence of sharply rising Main terminal currents. Gate resistances have significant effect on turn-on and turn-off times of these devices - permitting optimisation of switching times for the reduction of switching losses and voltage spikes. Version 2 EE IIT, Kharagpur 13

104 Protection schemes for over-voltages - the prolonged ones and those of short duration - are guided by the energy content of the surges. Metal Oxide Varistors (MOV's), capacitive dynamic voltage-clamps and crow-bar circuits are some of the strategies commonly used. For high dv/dt stresses, which again have similar effect on all devices, R-C or R-C-D clamps are used depending on the speed of the device. These 'snubbers' or 'switching-aid-networks', additionally minimise switching losses of the device - thus reducing its temperature rise. Gates of all devices are required to be protected against over-voltages (typically + 20 V) specially for the voltage driven ones. This is achieved with the help of Zener clamps - the zener being also a very fast-acting device. Protection against issues like excessive case temperatures and ESD follow well-set practices. Forced-cooling techniques are very important for the higher rated converters and whole environments are air-cooled to lower the ambient. Objective type questions Qs#1 Which is the Power semiconductor device having a) Highest switching speed; b) Highest voltage / current ratings; c) Easy drive features; d) Can be most effectively paralleled; e) Can be protected against over-currents with a fuse; f) Gate-turn off capability with regenerative features; g) Easy drive and High power handling capability Ans: a) MOSFET; b) SCR; c) MOSFET; d) MOSFET; e) SCR ; (f) GTO; (g) IGBT Qs#2 An SCR requires 50 ma gate current to switch it on. It has a resistive load and is supplied from a 100 V DC supply. Specify the Pulse transformer details and the circuit following it, if the driver circuit supply voltage is 10 V and the gate-cathode drop is about 1 V. Ans: The most important ratings of the Pulse transformer are its volt-secs rating, the isolation voltage and the turns ratio. The volt-secs is decided by the product of the primary pulse-voltage multiplied by the period for which the pulse is applied to the winding If the primary pulse voltage = (Supply voltage drive transistor drop) The turn-on time of he SCR may be in the range 50 μsecs for an SCR of this rating. Consequently the volt secs may be in the range of 9 x 50 = 450 μvolt-secs The Pulse transformer may be chosen as: 1:1, 450 μvs, V isol = 2.5 KV, I M = 150 ma The circuit shown in Fig. 1.7 may be used. Diodes 1N4002 Series resistance = (Supply voltage drive transistor drop gate-cathode drop)/100ma = (10 1 1) / 100 E-3 = 80 Ohm = 49 or 57 Ohm (nearest available lower value) Version 2 EE IIT, Kharagpur 14

105 Module 1 Power Semiconductor Devices Version 2 EE IIT, Kharagpur 1

106 Lesson 4 Thyristors and Triacs Version 2 EE IIT, Kharagpur 2

107 Instructional objects On completion the student will be able to Explain the operating principle of a thyristor in terms of the two transistor analogy. Draw and explain the i-v characteristics of a thyristor. Draw and explain the gate characteristics of a thyristor. Interpret data sheet rating of a thyristor. Draw and explain the switching characteristics of a thyristor. Explain the operating principle of a Triac. Version 2 EE IIT, Kharagpur 3

108 4.1 Introduction Although the large semiconductor diode was a predecessor to thyristors, the modern power electronics area truly began with advent of thyristors. One of the first developments was the publication of the P-N-P-N transistor switch concept in 1956 by J.L. Moll and others at Bell Laboratories, probably for use in Bell s Signal application. However, engineers at General Electric quickly recognized its significance to power conversion and control and within nine months announced the first commercial Silicon Controlled Rectifier in This had a continuous current carrying capacity of 25A and a blocking voltage of 300V. Thyristors (also known as the Silicon Controlled Rectifiers or SCRs) have come a long way from this modest beginning and now high power light triggered thyristors with blocking voltage in excess of 6kv and continuous current rating in excess of 4kA are available. They have reigned supreme for two entire decades in the history of power electronics. Along the way a large number of other devices with broad similarity with the basic thyristor (invented originally as a phase control type device) have been developed. They include, inverter grade fast thyristor, Silicon Controlled Switch (SCS), light activated SCR (LASCR), Asymmetrical Thyristor (ASCR) Reverse Conducting Thyristor (RCT), Diac, Triac and the Gate turn off thyristor (GTO). From the construction and operational point of view a thyristor is a four layer, three terminal, minority carrier semi-controlled device. It can be turned on by a current signal but can not be turned off without interrupting the main current. It can block voltage in both directions but can conduct current only in one direction. During conduction it offers very low forward voltage drop due to an internal latch-up mechanism. Thyristors have longer switching times (measured in tens of μs) compared to a BJT. This, coupled with the fact that a thyristor can not be turned off using a control input, have all but eliminated thyristors in high frequency switching applications involving a DC input (i.e, choppers, inverters). However in power frequency ac applications where the current naturally goes through zero, thyristor remain popular due to its low conduction loss its reverse voltage blocking capability and very low control power requirement. In fact, in very high power (in excess of 50 MW) AC DC (phase controlled converters) or AC AC (cyclo-converters) converters, thyristors still remain the device of choice. 4.2 Constructional Features of a Thyristor Fig 4.1 shows the circuit symbol, schematic construction and the photograph of a typical thyristor. Version 2 EE IIT, Kharagpur 4

109 A A p n - G K p n + n + (a) G (b) K (c) Fig. 4.1: Constructional features of a thysistor (a) Circuit Symbol, (b) Schematic Construction, (c) Photograph As shown in Fig 4.1 (b) the primary crystal is of lightly doped n - type on either side of which two p type layers with doping levels higher by two orders of magnitude are grown. As in the case of power diodes and transistors depletion layer spreads mainly into the lightly doped n - region. The thickness of this layer is therefore determined by the required blocking voltage of the device. However, due to conductivity modulation by carriers from the heavily doped p regions on both side during ON condition the ON state voltage drop is less. The outer n + layers are formed with doping levels higher then both the p type layers. The top p layer acls as the Anode terminal while the bottom n + layers acts as the Cathode. The Gate terminal connections are made to the bottom p layer. As it will be shown later, that for better switching performance it is required to maximize the peripheral contact area of the gate and the cathode regions. Therefore, the cathode regions are finely distributed between gate contacts of the p type layer. An Involute structure for both the gate and the cathode regions is a preferred design structure. 4.3 Basic operating principle of a thyristor The underlying operating principle of a thyristor is best understood in terms of the two transistor analogy as explained below. Version 2 EE IIT, Kharagpur 5

110 A A A I A G p n - p n + n + K (a) p G J 2 J 3 p p J 1 n - J 2 n + K (b) n - J 3 i C2 (α 2 ) Q 2 I K K (c) Q 1 (α 1 ) i C1 I G G Fig. 4.2: Two transistor analogy of a thyristor construction. (a) Schematic Construction, (b) Schematic division in component transistor (c) Equivalent circuit in terms of two transistors. a) Schematic construction, b) Schematic division in component transistor c) Equivalent circuit in terms of two transistors. Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode positive with respect to the cathode and the gate terminal open. With this voltage polarity J 1 & J 3 are forward biased while J 2 reverse biased. Under this condition. 2 2 K co2 ( ) ( ) ic 1= 1I A+ I co1 4.1 ic = I + I 4.2 Where 1 & 2 are current gains of Q 1 & Q 2 respectively while I co1 & I co2 are reverse saturation currents of the CB junctions of Q 1 & Q 2 respectively. Now from Fig 4.2 (c). i c1 + i c2 = I A ( 4.3) & I A = I K ( 4.4 ) ( I G = 0) Combining Eq 4.1 & 4.4 I +I I ( ) co1 co2 co I A = = ( 1+ 2) 1- ( 1+ 2) Version 2 EE IIT, Kharagpur 6

111 Where I I +I is the total reverse leakage current of J co co1 co2 2 Now as long as V AK is small I co is very low and both 1 & 2 are much lower than unity. Therefore, total anode current I A is only slightly greater than I co. However, as V AK is increased up to the avalanche break down voltage of J 2, I co starts increasing rapidly due to avalanche multiplication process. As I co increases both 1 & 2 increase and approaches unity. Under this condition large anode current starts flowing, restricted only by the external load resistance. However, voltage drop in the external resistance causes a collapse of voltage across the thyristor. The CB junctions of both Q 1 & Q 2 become forward biased and the total voltage drop across the device settles down to approximately equivalent to a diode drop. The thyristor is said to be in ON state. Just after turn ON if I a is larger than a specified current called the Latching Current I L, 1 and 2 remain high enough to keep the thyristor in ON state. The only way the thyristor can be turned OFF is by bringing I A below a specified current called the holding current (I H ) where upon 1 & 2 starts reducing. The thyristor can regain forward blocking capacity once excess stored charge at J 2 is removed by application of a reverse voltage across A & K (ie, K positive with respect A). It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate to cathode) without increasing the forward voltage across the device up to the forward break-over level. With a positive gate current equation 4.4 can be written as K A G ( ) I = I + I 4.6 Combining with Eqns. 4.1 to 4.3 I +I ( ) 2 G co I A = ( 1+ 2) Obviously with sufficiently large I G the thyristor can be turned on for any value of I co (and hence V AK ). This is called gate assisted turn on of a Thyristor. This is the usual method by which a thyristor is turned ON. When a reverse voltage is applied across a thyristor (i.e, cathode positive with respect to anose.) junctions J 1 and J 3 are reverse biased while J 2 is forward biased. Of these, the junction J 3 has a very low reverse break down voltage since both the n + and p regions on either side of this junction are heavily doped. Therefore, the applied reverse voltage is almost entirely supported by junction J 1. The maximum value of the reverse voltage is restricted by a) The maximum field strength at junction J 1 (avalanche break down) b) Punch through of the lightly doped n - layer. Since the p layers on either side of the n - region have almost equal doping levels the avalanche break down voltage of J 1 & J 2 are almost same. Therefore, the forward and the reverse break down voltage of a thyristor are almost equal.up to the break down voltage of J 1 the reverse current of the thyristor remains practically constant and increases sharply after this voltage. Thus, the reverse characteristics of a thyristor is similar to that of a single diode. Version 2 EE IIT, Kharagpur 7

112 If a positive gate current is applied during reverse bias condition, the junction J 3 becomes forward biased. In fact, the transistors Q 1 & Q 2 now work in the reverse direction with the roles of their respective emitters and collectors interchanged. However, the reverse 1 & 2 being significantly smaller than their forward counterparts latching of the thyristor does not occur. However, reverse leakage current of the thyristor increases considerably increasing the OFF state power loss of the device. If a forward voltage is suddenly applied across a reverse biased thyristor, there will be considerable redistribution of charges across all three junctions. The resulting current can become large enough to satisfy the condition = 1 and consequently turn on the thyristor. This is called dv turn on of a thyristor and should be avoided. dt Exercise 4.1 1) Fill in the blank(s) with the appropriate word(s) i. A thyristor is a carrier semi controlled device. ii. A thyristor can conduct current in direction and block voltage in direction. iii. A thyristor can be turned ON by applying a forward voltage greater than forward voltage or by injecting a positive current pulse under forward bias condition. iv. To turn OFF a thyristor the anode current must be brought below current and a reverse voltage must be applied for a time larger than time of the device. v. A thyristor may turn ON due to large forward. Answers: (i) minority; (ii) one, both; (iii) break over, gate; (iv) holding, turn off; (v) dv dt 2. Do you expect a thyristor to turn ON if a positive gate pulse is applied under reverse bias condition (i. e cathode positive with respect to anode)? Answer: The two transistor analogy of thyristor shown in Fig 4.2 (c) indicates that when a reverse voltage is applied across the device the roles of the emitters and collectors of the constituent transistors will reverse. With a positive gate pulse applied it may appear that the device should turn ON as in the forward direction. However, the constituent transistors have very low current gain in the reverse direction. Therefore no reasonable value of the gate current will satisfy the turn ON condition (i.e = 1). Hence the device will not turn ON. Version 2 EE IIT, Kharagpur 8

113 4.4 Steady State Characteristics of a Thyristor Static output i-v characteristics of a thyristor I A V BRF V AK + - A I A K i g I g I s V BRR I H I L V BRF i g1 i g2 i g3 i g4 V AK i g4 > i g3 > i g2 > i g1 > i g = 0 V H i g4 > i g3 > i g2 > i g1 > i g = 0 Fig. 4.3: Static output characteristics of a Thyristor The circuit symbol in the left hand side inset defines the polarity conventions of the variables used in this figure. With ig = 0, V AK has to increase up to forward break over voltage V BRF before significant anode current starts flowing. However, at V BRF forward break over takes place and the voltage across the thyristor drops to V H (holding voltage). Beyond this point voltage across the thyristor (V AK ) remains almost constant at V H (1-1.5v) while the anode current is determined by the external load. The magnitude of gate current has a very strong effect on the value of the break over voltage as shown in the figure. The right hand side figure in the inset shows a typical plot of the forward break over voltage (V BRF ) as a function of the gate current (I g ) After Turn ON the thyristor is no more affected by the gate current. Hence, any current pulse (of required magnitude) which is longer than the minimum needed for Turn ON is sufficient to effect control. The minimum gate pulse width is decided by the external circuit and should be long enough to allow the anode current to rise above the latching current (I L ) level. Version 2 EE IIT, Kharagpur 9

114 The left hand side of Fig 4.3 shows the reverse i-v characteristics of the thyristor. Once the thyristor is ON the only way to turn it OFF is by bringing the thyristor current below holding current (I H ). The gate terminal has no control over the turn OFF process. In ac circuits with resistive load this happens automatically during negative zero crossing of the supply voltage. This is called natural commutation or line commutation. However, in dc circuits some arrangement has to be made to ensure this condition. This process is called forced commutation. During reverse blocking if i g = 0 then only reverse saturation current (I s ) flows until the reverse voltage reaches reverse break down voltage (V BRR ). At this point current starts rising sharply. Large reverse voltage and current generates excessive heat and destroys the device. If i g > 0 during reverse bias condition the reverse saturation current rises as explained in the previous section. This can be avoided by removing the gate current while the thyristor is reverse biased. The static output i-v characteristics of a thyristor depends strongly on the junction temperature as shown in Fig 4.4. V BRF I A T j = T j V AK T j = Fig. 4.4: Effect of junction temperature (T j ) on the output i v characteristics of a thyristor Thyristor Gate Characteristics The gate circuit of a thyristor behaves like a poor quality diode with high on state voltage drop and low reverse break down voltage. This characteristic usually is not unique even within the same family of devices and shows considerable variation from device to device. Therefore, manufacturer s data sheet provides the upper and lower limit of this characteristic as shown in Fig 4.5. Version 2 EE IIT, Kharagpur 10

115 V g V g max A E c d R g S 2 P gav Max E V g i g V g min b h Load line e P gm K V ng g S 1 f I g max I g min I g Fig. 4.5: Gate characteristics of a thyristor. Each thyristor has maximum gate voltage limit (V gmax ), gate current limit (I gmax ) and maximum average gate power dissipation limit( P gav Max ). These limits should not be exceeded in order to avoid permanent damage to the gate cathode junction. There are also minimum limits of V g (V gmin ) and Ig (I gmin ) for reliable turn on of the thyristor. A gate non triggering voltage (V ng ) is also specified by the manufacturers of thyristors. All spurious noise signals should be less than this voltage V ng in order to prevent unwanted turn on of the thyristor. The useful gate drive area of a thyristor is then b c d e f g h. Referring to the gate drive circuit in the inset the equation of the load line is given by V g = E - R g i g A typical load line is shown in Fig 4.5 by the line S 1 S 2. The actual operating point will be some where between S 1 & S 2 depending on the particular device. For optimum utilization of the gate ratings the load line should be shifted forwards the P gav curve without violating V g Maxor I gmax ratings. Therefore, for a dc source E c f represents the optimum load line from which optimum values of E & R g can be determined. It is however customary to trigger a thyristor using pulsed voltage & current. Maximum power dissipation curves for pulsed operation (P gm ) allows higher gate current to flow which in turn reduces the turn on time of the thyristor. The value of P gm depends on the pulse width (T ON ) of the gate current pulse. T ON should be larger than the turn on time of the thyristor. For T ON larger Max Version 2 EE IIT, Kharagpur 11

116 than 100 μs, average power dissipation curve should be used. For T ON less than 100 μs the following relationship should be maintained. gm gav Max ON p p ( ) δ P P 4.9 Where δ = T f, f = pulse frequency. The magnitude of the gate voltage and current required for triggering a thyristor is inversely proportional to the junction temperature. The gate cathode junction also has a maximum reverse (i.e, gate negative with respect to the cathode) voltage specification. If there is a possibility of the reverse gate cathode voltage exceeding this limit a reverse voltage protection using diode as shown in Fig 4.6 should be used. A A R g E G E (a) K (b) K Fig. 4.6: Gate Cathode reverse voltage protection circuit. Exercise 4.2 1) Fill in the blank(s) with the appropriate word(s) i. Forward break over voltage of a thyristor decreases with increase in the current. ii. Reverse voltage of a thyristor is of the gate current. iii. Reverse saturation current of a thyristor with gate current. iv. In the pulsed gate current triggering of a thyristor the gate current pulse width should be larger than the time of the device. v. To prevent unwanted turn ON of a thyristor all spurious noise signals between the gate and the cathode must be less than the gate voltage. Version 2 EE IIT, Kharagpur 12

117 Answer: (i) gate; (ii) break down, independent; (iii) increases; (iv) Turn ON; (v) nontrigger. 2) A thyristor has a maximum average gate power dissipation limit of 0.2 watts. It is triggered with pulsed gate current at a pulse frequency of 10 KHZ and duly ratio of 0.4. Assuming the gate cathode voltage drop to be 1 volt. Find out the allowable peak gate current magnitude. Answer: On period of the gate current pulse is 0.4 T ON = δ T δ S = = 4 sec = 40 μs < 100 μs. fs 10 Therefore, pulsed gate power dissipation limit P gm can be used. From Equation 4.9 gm gav ( ) δ P P Max 0.2 or P gm watts =.5watts δ.5 But P gm = I g V g ; V g = 1V I g Max= = 0.5Amps Thyristor ratings Some useful specifications of a thyristor related to its steady state characteristics as found in a typical manufacturer s data sheet will be discussed in this section Voltage ratings Peak Working Forward OFF state voltage (V DWM ): It specifics the maximum forward (i.e, anode positive with respect to the cathode) blocking state voltage that a thyristor can withstand during working. It is useful for calculating the maximum RMS voltage of the ac network in which the thyristor can be used. A margin for 10% increase in the ac network voltage should be considered during calculation. Peak repetitive off state forward voltage (V DRM ): It refers to the peak forward transient voltage that a thyristor can block repeatedly in the OFF state. This rating is specified at a maximum allowable junction temperature with gate circuit open or with a specified biasing resistance between gate and cathode. This type of repetitive transient voltage may appear across a thyristor due to commutation of other thyristors or diodes in a converter circuit. Peak non-repetitive off state forward voltage (V DSM ): It refers to the allowable peak value of the forward transient voltage that does not repeat. This type of over voltage may be caused due to switching operation (i.e, circuit breaker opening or closing or lightning surge) in a supply network. Its value is about 130% of V DRM. However, V DSM is less than the forward break over voltage V BRF. Version 2 EE IIT, Kharagpur 13

118 Peak working reverse voltage (V DWM ): It is the maximum reverse voltage (i.e, anode negative with respect to cathode) that a thyristor can with stand continuously. Normally, it is equal to the peak negative value of the ac supply voltage. Peak repetitive reverse voltage (V RRM ): It specifies the peak reverse transient voltage that may occur repeatedly during reverse bias condition of the thyristor at the maximum junction temperature. Peak non-repetitive reverse voltage (V RSM ): It represents the peak value of the reverse transient voltage that does not repeat. Its value is about 130% of V RRM. However, V RSM is less than reverse break down voltage V BRR. Fig 4.7 shows different thyristor voltage ratings on a comparative scale. I A V BRR V RSM V RRM V RWM V DWM V DRM V DSM V BRF V AK Current ratings Fig. 4.7: Voltage ratings of a thyristor. Maximum RMS current (I rms ): Heating of the resistive elements of a thyristor such as metallic joints, leads and interfaces depends on the forward RMS current I rms. RMS current rating is used as an upper limit for dc as well as pulsed current waveforms. This limit should not be exceeded on a continuous basis. Maximum average current (I av ): It is the maximum allowable average value of the forward current such that i. Peak junction temperature is not exceeded ii. RMS current limit is not exceeded Manufacturers usually provide the forward average current derating characteristics which shows I av as a function of the case temperature (T c ) with the current conduction angle φ as a parameter. The current wave form is assumed to be formed from a half cycle sine wave of power frequency as shown in Fig 4.8. Version 2 EE IIT, Kharagpur 14

119 I av Amps φ = 180 φ = φ = 60 φ = 30 φ T C ( C) Fig. 4.8: Average forward current derating characteristics Maximum Surge current (I SM ): It specifies the maximum allowable non repetitive current the device can withstand. The device is assumed to be operating under rated blocking voltage, forward current and junction temperation before the surge current occurs. Following the surge the device should be disconnected from the circuit and allowed to cool down. Surge currents are assumed to be sine waves of power frequency with a minimum duration of ½ cycles. Manufacturers provide at least three different surge current ratings for different durations. For example I 1 sm = 3000 A for cycle 2 I = 2100 A for 3 cycles I sm sm = 1800 A for 5 cycles Alternatively a plot of I sm vs. applicable cycle numbers may also be provided. Maximum Squared Current integral ( i 2 dt): This rating in terms of A 2 S is a measure of the energy the device can absorb for a short time (less than one half cycle of power frequency). This rating is used in the choice of the protective fuse connected in series with the device. Latching Current (I L ): After Turn ON the gate pulse must be maintained until the anode current reaches this level. Otherwise, upon removal of gate pulse, the device will turn off. Holding Current (I H ): The anode current must be reduced below this value to turn off the thyristor. Maximum Forward voltage drop (V F ): Usually specified as a function of the instantaneous forward current at a given junction temperature. Version 2 EE IIT, Kharagpur 15

120 Average power dissipation P av ): Specified as a function of the average forward current (I av ) for different conduction angles as shown in the figure 4.9. The current wave form is assumed to be half cycle sine wave (or square wave) for power frequency. P av φ = 180 i F ωt φ Fig. 4.9: Average power dissipation vs average forward current in a thyristor. In the above diagram 1 φ I av = i o F dθ 2π φ P av = v o F i F dθ 2π Gate Specifications ( ) ( ) Gate current to trigger (I GT ): Minimum value of the gate current below which reliable turn on of the thyristor can not be guaranteed. Usually specified at a given forward break over voltage. Gate voltage to trigger (V GT ): Minimum value of the gate cathode forward voltage below which reliable turn on of the thyristor can not be guaranteed. It is specified at the same break over voltage as I GT. Non triggering gate voltage (V GNT ): Maximum value of the gate-cathode voltage below which the thyristor can be guaranteed to remain OFF. All spurious noise voltage in the gate drive circuit must be below this level. Peak reverse gate voltage (V GRM ): Maximum reverse voltage that can appear between the gate and the cathode terminals without damaging the junction. I av Version 2 EE IIT, Kharagpur 16

121 Average Gate Power dissipation (P GAR ): Average power dissipated in the gate-cathode junction should not exceed this value for gate current pulses wider than 100 μs. Peak forward gate current (I GRM ): The forward gate current should not exceed this limit even on instantaneous basis. Exercise 4.3 1) Fill in the blank(s) with the appropriate word(s) i. Peak non-repetitive over voltage may appear across a thyristor due to or surges in a supply network. ii. V RSM rating of a thyristor is greater than the rating but less than the rating. iii. Maximum average current a thristor can carry depends on the of the thyristor and the of the current wave form. iv. The I SM rating of a thyristor applies to current waveforms of duration than half cycle of the power frequency where as the i 2 dt rating applies to current durations than half cycle of the power frequency. v. The gate non-trigger voltage specification of a thyristor is useful for avoiding unwanted turn on of the thyristor due to voltage signals at the gate. Answer: (i) switching, lightning; (ii) V RRM, V BRR ; (iii) case temperature, conduction angle; (iv) greater, less; (v) noise 2. A thyristor has a maximum average current rating 1200 Amps for a conduction angle of 180. Find the corresponding rating for Φ = 60. Assume the current waveforms to be half cycle sine wave. Answer: The form factor of half cycle sine waves for a conduction angle φ is given by 1 φ 2 1 I Sin θ dθ RMS 2π o 2 φ ( φ φ) π - Sin 2 F.F = = = Iav 1 1- Cos φ Sinθ dθ 2π o For φ = 180, F.F = π 2 RMS current rating of the thyristor = For φ = 60, F.F = 2 π π - 3 = Since RMS current rating should not exceeded π 1200 = 1885 Amps. 2 Version 2 EE IIT, Kharagpur 17

122 1200 π Maximum I av for φ = 60 = 4 π π = Amps. 4.6 Switching Characteristics of a Thyristor During Turn on and Turn off process a thyristor is subjected to different voltages across it and different currents through it. The time variations of the voltage across a thyristor and the current through it during Turn on and Turn off constitute the switching characteristics of a thyristor Turn on Switching Characteristics A forward biased thyristor is turned on by applying a positive gate voltage between the gate and cathode as shown in Fig i g v AK i A i A 0.9 I ON t V i i g R 0.1 I ON I ON t α Firing angle V i v AK 0.9 V ON v AK i A V ON t ON 0.1 V ON t Expanded scale t d t r t p Fig. 4.10: Turn on characteristics of a thyristor. Fig 4.10 shows the waveforms of the gate current (i g ), anode current (i A ) and anode cathode voltage (V AK ) in an expanded time scale during Turn on. The reference circuit and the associated waveforms are shown in the inset. The total switching period being much smaller compared to the cycle time, i A and V AK before and after switching will appear flat. As shown in Fig 4.10 there is a transition time t ON from forward off state to forward on state. This transition time is called the thyristor turn of time and can be divided into three separate intervals namely, (i) delay time (t d ) (ii) rise time (t r ) and (iii) spread time (t p ). These times are shown in Fig 4.10 for a resistive load. Version 2 EE IIT, Kharagpur 18

123 Delay time (t d ): After switching on the gate current the thyristor will start to conduct over the portion of the cathode which is closest to the gate. This conducting area starts spreading at a finite speed until the entire cathode region becomes conductive. Time taken by this process constitute the turn on delay time of a thyristor. It is measured from the instant of application of the gate current to the instant when the anode current rises to 10% of its final value (or V AK falls to 90% of its initial value). Typical value of t d is a few micro seconds. Rise time (tr): For a resistive load, rise time is the time taken by the anode current to rise from 10% of its final value to 90% of its final value. At the same time the voltage V AK falls from 90% of its initial value to 10% of its initial value. However, current rise and voltage fall characteristics are strongly influenced by the type of the load. For inductive load the voltage falls faster than the current. While for a capacitive load V AK falls rapidly in the beginning. However, as the current increases, rate of change of anode voltage substantially decreases. If the anode current rises too fast it tends to remain confined in a small area. This can give rise to local hot spots and damage the device. Therefore, it is necessary to limit the rate of rise of the dia ON state current dt by using an inductor in series with the device. Usual values of maximum di allowable A is in the range of A/μs. dt Spread time (tp): It is the time taken by the anode current to rise from 90% of its final value to 100%. During this time conduction spreads over the entire cross section of the cathode of the thyristor. The spreading interval depends on the area of the cathode and on the gate structure of the thyristor Turn off Switching Characteristics Once the thyristor is on, and its anode current is above the latching current level the gate loses control. It can be turned off only by reducing the anode current below holding current. The turn off time t q of a thyristor is defined as the time between the instant anode current becomes zero and the instant the thyristor regains forward blocking capability. If forward voltage is applied across the device during this period the thyristor turns on again. During turn off time, excess minority carriers from all the four layers of the thyristor must be removed. Accordingly t q is divided in to two intervals, the reverse recovery time (t rr ) and the gate recovery time (t qr ). Fig 4.11 shows the variation of anode current and anode cathode voltage with time during turn off operation on an expanded scale. Version 2 EE IIT, Kharagpur 19

124 i A v AK di A dt i g i A V i Q rr I rr t v AK v i i A t V rr t Expanded scale v i t rr t q t gr Fig. 4.11: Turn off characteristics of a thyristor. The anode current becomes zero at time t 1 and starts growing in the negative direction with the di same A dt till time t 2. This negative current removes excess carriers from junctions J 1 & J 3. At time t 2 excess carriers densities at these junctions are not sufficient to maintain the reverse current and the anode current starts decreasing. The value of the anode current at time t 2 is called the reverse recovery current (I rr ). The reverse anode current reduces to the level of reverse saturation current by t 3. Total charge removed from the junctions between t 1 & t 3 is called the reverse recovery charge (Q rr ). Fast decaying reverse current during the interval t 2 t 3 coupled with the di limiting inductor may cause a large reverse voltage spike (V dt rr ) to appear across the device. This voltage must be limited below the V RRM rating of the device. Up to time t 2 the voltage across the device (V AK ) does not change substantially from its on state value. However, after the reverse recovery time, the thyristor regains reverse blocking capacity and V AK starts following supply voltage v i. At the end of the reverse recovery period (t rr ) trapped charges still exist at the junction J 2 which prevents the device from blocking forward voltage just after t rr. These trapped charges are removed only by the process of recombination. The time taken for this recombination process to complete (between t 3 & t 4 ) is called the gate recovery time (t gr ). The time interval t q = t rr + t gr is called device turn off time of the thyristor. No forward voltage should appear across the device before the time t q to avoid its inadvertent turn on. A circuit designer must provide a time interval t c (t c > t q ) during which a reverse voltage is applied across the device. t c is called the circuit turn off time. Version 2 EE IIT, Kharagpur 20

125 The reverse recovery charge Q rr is a function of the peak forward current before turn off and its dia rate of decrease dt. Manufacturers usually provide plots of Q di rr as a function of A for dt different values of peak forward current. They also provide the value of the reverse recovery di current I rr for a given I A and A dt. Alternatively I rr can be evaluated from the given Q rr characteristics following similar relationships as in the case of a diode. As in the case of a diode the relative magnitudes of the time intervals t 1 t 2 and t 2 t 3 depends on the construction of the thyristor. In normal recovery converter grade thyristor they are almost equal for a specified forward current and reverse recovery current. However, in a fast recovery inverter grade thyristor the interval t 2 t 3 is negligible compared to the interval t 1 t 2. This helps reduce the total turn off time t q of the thyristor (and hence allow them to operate at higher switching frequency). However, large voltage spike due to this snappy recovery will appear across the device after the device turns off. Typical turn off times of converter and inverter grade thyristors are in the range of μs and 5-50 μs respectively. As has been mentioned in the introduction thyristor is the device of choice at the very highest power levels. At these power levels (several hundreds of megawatts) reliability of the thyristor power converter is of prime importance. Therefore, suitable protection arrangement must be made against possible overvoltage, overcurrent and unintended turn on for each thyristor. At the highest power level (HVDC transmission system) thyristor converters operate from network voltage levels in excess of several hundreds of kilo volts and conduct several tens of kilo amps of current. They usually employ a large number of thyristors connected in series parallel combination. For maximum utilization of the device capacity it is important that each device in this series parallel combination share the blocking voltage and on state current equally. Special equalizing circuits are used for this purpose. Exercise 4.4 1) Fill in the blank(s) with the appropriate word(s) i. A thyristor is turned on by applying a gate current pulse when it is ii. iii. iv. biased. Total turn on time of a thyristor can be divided into time time and time. During rise time the rate of rise of anode current should be limited to avoid creating local. A thyristor can be turned off by bringing its anode current below current and applying a reverse voltage across the device for duration larger than the time of the device. v. Reverse recovery charge of a thyristor depends on the of the forward current just before turn off and its. Version 2 EE IIT, Kharagpur 21

126 vi. Inverter grade thyristors have turn off time compared to a converter grade thyristor. Answer: (i) positive, forward; (ii) delay, rise, spread; (iii) hot spots (iv) holding, turn off; (v) magnitude, rate of decrease (vi) faster 2. With reference to Fig 4.10 find expressions for (i) turn on power loss and (ii) conduction power loss of the thyristor as a function of the firing angle. Neglect turn on delay time and spread time and assume linear variation of voltage and current during turn on period. Also assume constant on state voltage V H across the thyristor. Answer: (i) For a firing angle the forward bias voltage across the thyristor just before turn on is V ON = 2V i Sin ; V i = RMS value of supply voltage. Current after the thyristor turns on for a resistive load is V V R I ON i ON = = 2 Sin R Neglecting delay and spread time and assuming linear variation of voltage and current during turn on V ak = 2 V t i Sin 1 -. where V H has been neglected. t ON 2 V i Sin t i a = R t ON Total switching energy loss 2 t ON 2Vi t 2 ON E ON = v o ak i t t a dt = Sin 1 - dt R o t ON ton 2 2 2Vi 2 t ON 2 Vi 2 = Sin 1 - = Sin t R 2 3 3R E ON occurs once every cycle. If the supply frequency is f then average turn on power loss is given by. ON 2 Vi 2 P ON = E ON f = Sin t ON f 3R (ii) If the firing angle is the thyristor conducts for π- angle. Instantaneous current through the device during this period is 2 V i Sin ωt i a = R <ω t π R Where t ON & V H have been neglected for simplicity. total conduction energy loss over one cycle is Version 2 EE IIT, Kharagpur 22

127 1 2 V 2 V V ( ) πω π i i H E C = V aki a dt = V H Sinθ dθ = 1 + Cos ω ω α R ωr i H Average conduction power loss = P = E f = ( 1 + Cos ) C c 2 V V 2 π R Fuse i 1 V i 220 V 50 HZ i f 3. In the ideal single phase fully controlled converter T 1 & T 2 are fired at a firing angle after the positive going zero crossing of V i while T 3 & T 4 are fired angle after the negative going zero crossing of V i, If all thyristors have a turn off time of 100 μs, find out maximum allowable value of. Answer: As T 1 & T 2 are fired at an angle after positive going zero crossing of V i, T 3 & T 4 are subjected to a negative voltage of V i. Since this voltage remain negative for a duration (π- ) angle (after which V i becomes positive) for safe commutation 0 ( π - Max) ωt = off 4.7 The Triac Max The Triac is a member of the thyristor family. But unlike a thyristor which conducts only in one direction (from anode to cathode) a triac can conduct in both directions. Thus a triac is similar to two back to back (anti parallel) connected thyristosr but with only three terminals. As in the case of a thyristor, the conduction of a triac is initiated by injecting a current pulse into the gate terminal. The gate looses control over conduction once the triac is turned on. The triac turns off only when the current through the main terminals become zero. Therefore, a triac can be categorized as a minority carrier, a bidirectional semi-controlled device. They are extensively used in residential lamp dimmers, heater control and for speed control of small single phase series and induction motors Construction and operating principle Fig (a) and (b) show the circuit symbol and schematic cross section of a triac respective. As the Triac can conduct in both the directions the terms anode and cathode are not used for Triacs. The three terminals are marked as MT 1 (Main Terminal 1), MT 2 (Main Terminal 2) and the gate by G. As shown in Fig 4.12 (b) the gate terminal is near MT 1 and is connected to both Version 2 EE IIT, Kharagpur 23

128 N 3 and P 2 regions by metallic contact. Similarly MT 1 is connected to N 2 and P 2 regions while MT 2 is connected to N 4 and P 1 regions. MT1 N 2 MT2 N 3 N 3 P 2 G P 2 N 2 P 2 N 1 G MT1 N 1 P 1 (a) N 4 P 1 MT2 (b) Fig. 4.12: Circuit symbol and schematic construction of a Triac (a) Circuit symbol (b) Schematic construction. Since a Triac is a bidirectional device and can have its terminals at various combinations of positive and negative voltages, there are four possible electrode potential combinations as given below 1. MT 2 positive with respect to MT 1, G positive with respect to MT 1 2. MT 2 positive with respect to MT 1, G negative with respect to MT 1 3. MT 2 negative with respect to MT 1, G negative with respect to MT 1 4. MT 2 negative with respect to MT 1, G positive with respect to MT 1 The triggering sensitivity is highest with the combinations 1 and 3 and are generally used. However, for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2 and 3 are used. Trigger mode 4 is usually averded. Fig 4.13 (a) and (b) explain the conduction mechanism of a triac in trigger modes 1 & 3 respectively. Version 2 EE IIT, Kharagpur 24

129 G I G MT1 ( - ) I G MT1 ( + ) I G N 2 N 3 I G P 2 N 1 P 2 N 1 P 1 P 1 N 4 (a) MT2 ( + ) (b) MT2 ( - ) Fig. 4.13: Conduction mechanism of a triac in trigger modes 1 and 3 (a) Mode 1, (b) Mode 3. In trigger mode-1 the gate current flows mainly through the P 2 N 2 junction like an ordinary thyristor. When the gate current has injected sufficient charge into P 2 layer the triac starts conducting through the P 1 N 1 P 2 N 2 layers like an ordinary thyristor. In the trigger mode-3 the gate current I g forward biases the P 2 P 3 junction and a large number of electrons are introduced in the P 2 region by N 3. Finally the structure P 2 N 1 P 1 N 4 turns on completely. Version 2 EE IIT, Kharagpur 25

130 4.7.2 Steady State Output Characteristics and Ratings of a Triac I -V BO I g3 > I g2 > I g1 > I g = 0 I g = 0 -I g3 < I g2 < I g1 V BO V Fig. 4.14: Steady state V I characteristics of a Triac From a functional point of view a triac is similar to two thyristors connected in anti parallel. Therefore, it is expected that the V-I characteristics of Triac in the 1 st and 3 rd quadrant of the V-I plane will be similar to the forward characteristics of a thyristors. As shown in Fig. 4.14, with no signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak value is lower than the break over voltage (V BO ) of the device. However, the turning on of the triac can be controlled by applying the gate trigger pulse at the desired instance. Mode-1 triggering is used in the first quadrant where as Mode-3 triggering is used in the third quadrant. As such, most of the thyristor characteristics apply to the triac (ie, latching and holding current). However, in a triac the two conducting paths (from MT 1 to MT 2 or from MT 1 to MT 1 ) interact with each other in the structure of the triac. Therefore, the voltage, current and frequency ratings of triacs are considerably lower than thyristors. At present triacs with voltage and current ratings of 1200V and 300A (rms) are available. Triacs also have a larger on state voltage drop compared to a thyristor. Manufacturers usually specify characteristics curves relating rms device current and maximum allowable case temperature as shown in Fig Curves relating the device dissipation and RMS on state current are also provided for different conduction angles. Version 2 EE IIT, Kharagpur 26

131 A 200 Bidirectional ON state current (RMS) For all conduction angles Maximum allowable case temperature (T C ) Fig. 4.15: RMS ON state current Vs maximum case temperature. C Triac Switching and gate trigger circuit Unlike a thyristor a triac gets limited time to turn off due to bidirectional conduction. As a result the triacs are operated only at power frequency. Switching characteristics of a triac is similar to that of a thyristor. However, turn off of a triac is extremely sensitive to temperature variation and may not turn off at all if the junction temperature exceeds certain limit. Problem may arise when a triac is used to control a lagging power factor load. At the current zero instant (when the triac turns off) a reverse voltage will appear across the triac since the supply voltage is negative at that instant. The rate of rise of this voltage is restricted by the triac junction capacitance only. The resulting dv may turn on the triac again. Similar problem occurs when a triac is used to dt control the power to a resistive element which has a very low resistance before normal working condition is reached. If such a load (e.g. incandescent filament lamp) is switch on at full supply voltage very large junction capacitance charging current will turn ON the device. To prevent such condition an R-C snubber is generally used across a triac. The triac should be triggered carefully to ensure safe operation. For phase control application, the triac is switched on and off in synchronism with the mains supply so that only a part of each half cycle is applied across the load. To ensure clean turn ON the trigger signal must rise rapidly to provide the necessary charge. A rise time of about 1 μs will be desirable. Such a triac gate triggering circuit using a diac and an R-C timing network is shown in Fig Version 2 EE IIT, Kharagpur 27

132 LOAD R 1 V 1 R 2 D 1 R C 1 C Fig. 4.16: Triac triggering circuit using a diac. In this circuit as Vi increases voltage across C 1 increases due to current flowing through load, R 1, R 2 and C 1. The voltage drop across diac D 1 increases until it reaches its break over point. As D 1 conducts a large current pulse is injected into the gate of the triac. By varying R 2 the firing can be controlled from zero to virtually 100%. Exercise 4.5 1) Fill in the blank(s) with the appropriate word(s) i. A Triac is a minority carrier device ii. iii. iv. A Triac behaves like two connected thyristors. The gate sensitivity of a triac is maximum when the gate is with respect to MT 1 while MT 2 is positive with respect to MT 1 or the gate is with respect to MT 1 while MT 2 is negative with respect to MT 1 A Triac operates either in the or the quadrant of the i-v characteristics. v. In the quadrant the triac is fired with gate current while in the quadrant the gate current should be. vi. The maximum possible voltage and current rating of a Triac is considerably compared to thyristor due to of the two current carrying paths inside the structure of the triac. Version 2 EE IIT, Kharagpur 28

133 vii. viii. To avoid unwanted turn on of a triac due to large dv are used dt across triacs. For clean turn ON of a triac the of the gate current pulse should be as as possible. Answer: (i) bidirectional; (ii) anti parallel; (iii) positive, negative; (iv) first, third; (v) first, positive, third, negative (vi) lower, interaction; (vii) R-C shubbers; (viii) rise time, small. Version 2 EE IIT, Kharagpur 29

134 References 1. Dr. P.C. Sen, Power Electronics ; Tata McGrow Hill Publishing Company Limited; New Delhi. 2. Dr. P.S. Bimbhra, Power Electronics Khanna Publishers Version 2 EE IIT, Kharagpur 30

135 Lesson Summary Thyristor is a four layer, three terminal, minority carrier, semi-controlled device. The three terminals of a thyristor are called the anode, the cathode and the gate. A thyristor can be turned on by increasing the voltage of the anode with respect to the cathode beyond a specified voltage called the forward break over voltage. A thyristor can also be turned on by injecting a current pulse into the gate terminal when the anode voltage is positive with respect to the cathode. This is called gate triggering. A thyristor can block voltage of both polarity but conducts current only from anode to cathode. After a thyristor turns on the gate looses control. It can be turned off only by bringing the anode current below holding current. After turn on the voltage across the thyristor drops to a very low value (around 1 volt). In the reverse direction a thyristor blocks voltage up to reverse break down voltage. A thyristor has a very low conduction voltage drop but large switching times. For this reason thyristors are preferred for high power, low frequency line commutated application. A thyristor is turned off by bringing the anode current below holding current and simultaneously applying a negative voltage (cathode positive with respect to anode) for a minimum time called turn off time. A triac is functionally equivalent to two anti parallel connected thyristors. It can block voltages in both directions and conduct current in both directions. A triac has three terminals like a thyristor. It can be turned on in either half cycle by either a positive on a negative current pulse at the gate terminal. Triacs are extensively used at power frequency ac load (eg heater, light, motors) control applications. Version 2 EE IIT, Kharagpur 31

136 Practice Problems and Answers Version 2 EE IIT, Kharagpur 32

137 1. Explain the effect of increasing the magnitude of the gate current and junction temperature on (i) forward and reverse break down voltages, (ii) forward and reverse leakage currents. 15 V R Th i B N 1 N 2 2. The thyristor Th is triggered using the pulse transformer shown in figure. The pulse transformer operates at 10 KHZ with a duty cycle of 40%. The thyristor has maximum average gate power dissipation limit of 0.5 watts and a maximum allow able gate voltage limit of 10 volts. Assuming ideal pulse transformer, find out the turns ratio N 1 /N 2 and the value of R. Fuse i 1 V i 220 V 50 HZ i f 3. A thyristor full bridge converter is used to drive a dc motor as shown in the figure. The thyristors are fired at a firing angle = 0 when motor runs at rated speed. The motor has on armature resistance of 0.2 Ω and negligible armature inductance. Find out the peak surge current rating of the thyristors such that they are not damaged due to sudden loss of field excitation to the motor. The protective fuse in series with the motor is designed to disconnect the motor within 1 2 cycle of fault. Find out the rating of the 2 i dt thyristors. 4. Why is it necessary to maximize the peripheral contact area of the gate and the cathode regions? A thyristor used to control the voltage applied to a load resistance from a 220v, Version 2 EE IIT, Kharagpur 33

138 50HZ single phase ac supply has a maximum value of the dia dt dia dt rating of 50 A / μs. Find out the limiting inductor to be connected in series with the load resistance. THM 200V 200V - + C THA 20 A 5. In a voltage commutated dc dc thyristor chopper the main thyristor THM is commutated by connecting a pre-charged capacitor directly across it through the auxiliary thyristor THA as shown in the figure. The main thyristor THM has a turn off time off 50μs and maximum dv rating of 500v/ μs. Find out a suitable value of C for safe dt commutation of THM. Version 2 EE IIT, Kharagpur 34

139 Answers to Practice Problems Version 2 EE IIT, Kharagpur 35

140 1. i. Forward break down voltage reduces with increasing gate current. It increases with junction temperature up to certain value of the junction temperature and then falls rapidly with any further increase in temperature. Reverse break down voltage is independent of the gate current magnitude but decreases with increasing junction temperature. ii. Forward leakage current is independent of the gate current magnitude but increases with junction temperature. Reverse leakage current increases with both the junction temperature and the magnitude of the gate current. THM 200V 200V - + C THA 20 A 2. Figure shows the equivalent gate drive circuit of the thyristor. For this circuit one can write E = R i + V OR V = E - R i g g g g The diode D clamps the gate voltage to zero when E goes negative. Now for i g = O, V g = E. Since V g Max= 10 v E = 10 v N2 N2 15 But E = 15 = = 1.5 N N Gate pulse width = Sec = 40μs. <100μs. instantaneous gate power dissipation limit can be used. Pav Max 0.2 Vg i g Max = = = 0.5 watts δ 0.4 For maximum utilization of the gate power dissipation limit the gate load line ie V g = E i g R = 10 i g R should be tangent to the maximum power dissipation curve V g i g = 0.5 Let the operating V g and i g be V go & i go V = 10 - i R go go 2 go go go V i = 0.5 i R - 10 i = 0 go Version 2 EE IIT, Kharagpur 36

141 Since V g = 10 i g R is tangent to V g i g = 0.5 at V go, i go. Slope of the tangent of V g i g = 0.5 at (V go, i go ) = -R dvg - vg v - R = = = - di ( v go,igo) i ( v go,igo ) i g v v i 0.5 R = = = i i i go go go 2 2 go go go g 0.5 i - 10i = 0 or 10i = 1 or i = go 2 go go go igo R = = = 50 Ω i.01 2 go go go Back emf. V a t i a (normal) t i a (with field loss) 3. Figure shows the armature voltage (firm line) and armature current of the motor under normal operating condition at rated speed. If there is a sudden loss of field excitation back emf will become zero and armature current will be limited solely by the armature resistance. The peak magnitude of the fault current will be = 1556(Amps)..2 It the thyristors have to survive this fault at least for 1 2 cycle (after which the fuse blows) I sm > 1556 Amps. t The fuse blows within 1 2 cycle of the fault occurring. Therefore the thyristors must withstand the fault for at least 1 2 cycle. Therefore, the i 2 t rating of the thyristor should be Version 2 EE IIT, Kharagpur 37

142 2 i dt = ( 1556 Sin 100 π t) ( 1556) [ ] = 1 - Cos 200 π t dt = 1 10 ( 1556 ) = A Sec 2 4. At the beginning of the turn on process the thyristor starts conducting through the area adjacent to the gate. This area spreads at a finite speed. However, if rate of increase of anode current is lager than the rate of increase of the current conduction are, the current density increases with time. This may lead to thyristor failure due to excessive local heating. However, if the contact area between the gate and the cathode is large a thyristor will be able to handle a di relatively large a without being damaged. dt The maximum dia dt will occur when the thyristor is triggered at = 90. Then di L a = Sin 90 dt 0 Since di a dt 6 Max = A Sec L min = = H = 6.22 μh dia dt Max V C t off 200 V v THM dv / dt t i C 20 Amps. t Version 2 EE IIT, Kharagpur 38

143 5. As soon as THA is turned on the load current transfer from THM to C. the voltage across THM is the negative of the capacitance voltage. Figure shows the waveforms of voltage across the capacitor (v c ), voltage across the main thyristor (V THM ) and the capacitor current i c. From dv i figure = c dt c dv Now i c = 20 Amps & Max = 500 v μs dt i 20 dv Max dt c -8 C Min = = 6 = 4 10 F = 0.04 μf The circuit turn off time is the time taken by the capacitor voltage to reach zero from an initial value of 200v. This time must be greater than the turn off time of the device. dvc Now C = i c = 20 dt 20 Δt Δv c = c Δv = = 200 Δt = t = C C = off = 5 μf For safe commutation of THM the higher value of C must the chosen the required value of C = 5 μf. Version 2 EE IIT, Kharagpur 39

144 Module 5 DC to AC Converters Version 2 EE IIT, Kharagpur 1

145 Lesson 33 Introduction to Voltage Source Inverters Version 2 EE IIT, Kharagpur 2

146 After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Identify the essential components of a voltage source inverter. Explain the principle behind dc to ac conversion. Identify the basic topology of single-phase and three-phase inverters and explain its principle of operation. Explain the gate drive circuit requirements of inverter switches. The word inverter in the context of power-electronics denotes a class of power conversion (or power conditioning) circuits that operates from a dc voltage source or a dc current source and converts it into ac voltage or current. The inverter does reverse of what ac-to-dc converter does (refer to ac to dc converters). Even though input to an inverter circuit is a dc source, it is not uncommon to have this dc derived from an ac source such as utility ac supply. Thus, for example, the primary source of input power may be utility ac voltage supply that is converted to dc by an ac to dc converter and then inverted back to ac using an inverter. Here, the final ac output may be of a different frequency and magnitude than the input ac of the utility supply. [The nomenclature inverter is sometimes also used for ac to dc converter circuits if the power flow direction is from dc to ac side. However in this lesson, irrespective of power flow direction, inverter is referred as a circuit that operates from a stiff dc source and generates ac output. If the input dc is a voltage source, the inverter is called a voltage source inverter (VSI). One can similarly think of a current source inverter (CSI), where the input to the circuit is a current source. The VSI circuit has direct control over output (ac) voltage whereas the CSI directly controls output (ac) current. Shape of voltage waveforms output by an ideal VSI should be independent of load connected at the output.] The simplest dc voltage source for a VSI may be a battery bank, which may consist of several cells in series-parallel combination. Solar photovoltaic cells can be another dc voltage source. An ac voltage supply, after rectification into dc will also qualify as a dc voltage source. A voltage source is called stiff, if the source voltage magnitude does not depend on load connected to it. All voltage source inverters assume stiff voltage supply at the input. Some examples where voltage source inverters are used are: uninterruptible power supply (UPS) units, adjustable speed drives (ASD) for ac motors, electronic frequency changer circuits etc. Most of us are also familiar with commercially available inverter units used in homes and offices to power some essential ac loads in case the utility ac supply gets interrupted. In such inverter units, battery supply is used as the input dc voltage source and the inverter circuit converts the dc into ac voltage of desired frequency. The achievable magnitude of ac voltage is limited by the magnitude of input (dc bus) voltage. In ordinary household inverters the battery voltage may be just 12 volts and the inverter circuit may be capable of supplying ac voltage of around 10 volts (rms) only. In such cases the inverter output voltage is stepped up using a transformer to meet the load requirement of, say, 230 volts How to Get AC Output From DC Input Supply? Figs. 33.1(a) and 33.1(b) show two schematic circuits, using transistor-switches, for generation of ac voltage from dc input supply. In both the circuits, the transistors work in common emitter configuration and are interconnected in push-pull manner. In order to have a single control signal Version 2 EE IIT, Kharagpur 3

147 for the transistor switches, one transistor is of n-p-n type and the other of p-n-p type and their emitters and bases are shorted as shown in the figures. Both circuits require a symmetrical bipolar dc supply. Collector of n-p-n transistor is connected to positive dc supply (+E) and that of p-n-p transistor is connected to negative dc supply of same magnitude (-E). Load, which has been assumed resistive, is connected between the emitter shorting point and the power supply ground. In Fig. 33.1(a), the transistors work in active (amplifier) mode and a sinusoidal control voltage of desired frequency is applied between the base and emitter points. When applied base signal is positive, the p-n-p transistor is reverse biased and the n-p-n transistor conducts the load current. Similarly for negative base voltage the p-n-p transistor conducts while n-p-n transistor remains reverse biased. A suitable resistor in series with the base signal will limit the base current and keep it sinusoidal provided the applied (sinusoidal) base signal magnitude is much higher than the base to emitter conduction-voltage drop. Under the assumption of constant gain (h fe ) of the transistor over its working range, the load current can be seen to follow the applied base signal. Fig. 33.2(a) shows a typical load voltage (in blue color) and base signal (green color) waveforms. This particular figure also shows the switch power loss for n-p-n transistor (in brown color). The other transistor will also be dissipating identical power during its conduction. The quantities in Fig. 33.2(a) are in per unit magnitudes where the base values are input supply voltage (E) and the load resistance (R). Accordingly the base magnitudes of current and power are E/R and E 2 /R respectively. As can be seen, the power loss in switches is a considerable portion of circuit s input power and hence such circuits are unacceptable for large output power applications. As against the amplifier circuit of Fig. 33.1(a), the circuit of Fig. 33.1(b) works in switched mode. The conducting switch remains fully on having negligible on-state voltage drop and the non-conducting switch remains fully off allowing no leakage current through it. The load voltage waveform output by switched-mode circuit of Fig. 33.1(b) is rectangular with magnitude +E when the n-p-n transistor is on and E when p-n-p transistor is on. Fig. 33.2(b) shows one such waveform (in pink color). The on and off durations of the two transistors are controlled so that (i) the resulting rectangular waveform has no dc component (ii) has a fundamental (sinusoidal) component of desired frequency and magnitude and (iii) the frequencies of unwanted harmonic voltages are much higher than that of the fundamental component. The fundamental sine wave in Fig. 33.2(b), shown in blue color, is identical to the sinusoidal output voltage of Fig. 33.2(a). Both amplifier mode and switched mode circuits of Figs. 33.1(a) and 33.1(b) are capable of producing ac voltages of controllable magnitude and frequency, however, the amplifier circuit is not acceptable in power-electronic applications due to high switch power loss. On the other hand, the switched mode circuit generates significant amount of unwanted harmonic voltages along with the desired fundamental frequency voltage. As will be shown in some later lessons, the frequency spectrum of these unwanted harmonics can be shifted towards high frequency by adopting proper switching pattern. These high frequency voltage harmonics can easily be blocked using small size filter and the resulting quality of load voltage can be made acceptable. Version 2 EE IIT, Kharagpur 4

148 + E + E S LOAD (R) * * S LOAD (R) - E Fig (a): A push-pull active amplifier circuit - E Fig (b): A push-pull switched mode circuit Version 2 EE IIT, Kharagpur 5

149 The magnitude, phase and frequency of the fundamental voltage waveform in Fig. 33.2(b) is solely determined by the magnitude of supply voltage and the switching pattern of the push-pull circuit shown in Fig. 33.1(b). Thus, as long as the transistors work in the switch-mode (fully on or fully off), the output voltage is essentially load-independent What If The Load Is Not Resistive? Circuit of Fig. 33.1(b) will not be able to output proper voltage waveform for a non-resistive load for the reasons mentioned below. Transistors used in the circuit of Fig. 33.1(b) are meant to carry only unidirectional current (from collector to emitter) and thus if the upper (n-p-n) transistor is on, the current must enter the star (*) marked terminal of the load and this same terminal will get connected to the positive dc supply (+E), other load terminal being at ground potential. When n-p-n transistor turns off and p- n-p type turns on, the load voltage and current polarities reverse simultaneously (p-n-p transistor can only carry current coming out of star marked end of load). Such one to one matching between the instantaneous polarities of load voltage and load current can be achieved only in purely resistive loads. For a general load the instantaneous current polarity may be different from instantaneous load-voltage polarity. As pointed out in section 33.1, the inverter switching-pattern fixes the output waveform irrespective of the load. Thus the magnitude, phase and frequency of the fundamental voltage output by a VSI is independent of the nature of load. Thus it turns out that for a non-resistive load the switches in the circuit of Fig. 33.1(b) should be able to carry bidirectional current and at the same time be controllable. [A mechanical switch realized using an electromagnetic contactor is one example of the bi-directional current carrying controllable switch. However electromagnetic contactors are not capable of operating at high frequency, in the range of kilohertz, and may not be suitable for present application.] If an anti-parallel diode is connected across each transistor switch, as shown in Fig. 33.3(a), the combination can conduct a bi-directional current. Now the transistor in anti-parallel with the diode may be considered as a single switch. [A major difference exists between this bidirectional electronic switch and a bi-directional current carrying mechanical switch. The mechanical switch can be subjected to bi-directional voltage. When off, the mechanical switch can block both positive and negative voltage across its terminals. The electronic switch of Fig. 33.3(a) can block only one polarity of voltage, the one that keeps the diode reverse biased. Under this polarity of voltage the switch can remain off as long as the base (or the gate) terminal is not given the turn-on signal. When applied voltage polarity is reversed the diode starts conducting and so the switch is not able to block the flow of reverse current.] In spite of unidirectional voltage blocking capability, the new electronic switch (similar to the one shown in Fig. 33.3(a)) suffices for the inverter application as pointed out in the following paragraphs. The push-pull circuit operation is now revisited using bi-directional current carrying switches. The modified circuit is shown in Fig. 33.3(b). It may be noted that both IGBT and BJT type transistors, when bypassed by anti-parallel diode, qualify as bi-directional current carrying switches. However, IGBT switch is controlled by gate voltage whereas the BJT Version 2 EE IIT, Kharagpur 6

150 Gate (control) + Analogous to Input / Output Control S + E Q 1 SW 1 * D 1 LOAD _ Input / Output Fig. 33.3(a): Bi-directional controlled switch Q 2 D 2 SW 2 - E Fig (b): Modified push-pull circuit switch is controlled using base current. [IGBT switches are easier to use, are much faster and are available in higher voltage and current ratings. As a result BJT switches are becoming obsolete.] In the circuit of Fig. 33.3(b), n-p-n transistor (Q 1 ) together with diode (D 1 ) constitutes the upper switch (SW 1 ). Similarly lower switch (SW 2 ) consists of p-n-p transistor (Q 2 ) in antiparallel with diode (D 2 ). By applying positive base-to-emitter voltage of suitable magnitude to transistor Q 1, the upper switch is turned on. Once the upper switch (diode D 1 or transistor Q 1 ) is conducting star end of load is at +E potential and diode D 2 of lower switch gets reverse biased. Transistor Q 2 is also reverse biased due to application of positive base voltage to the transistors. Thus while switch SW 1 is conducting current, switch SW 2 is off and is blocking voltage of magnitude 2E. Similarly when applied base voltage to the transistors is made negative, Q 1 is reverse biased and Q 2 is forward biased. This results in SW 1 turning off and SW 2 turning on. Now SW 1 blocks a voltage of magnitude 2E. It may be interesting to see how diodes follow the switching command given to the transistor part of the switches. To illustrate this point some details of circuit operation with an inductive load, consisting of a resistor and an inductor in series, is considered. As is well known, current through such loads cannot change abruptly. The electrical inertial time constant of the load, given by its L (inductance) / R (resistance) ratio, may in general be large compared to the chosen switching time period of the transistor switches. Thus the transistors Q 1 and Q 2 may turn-on and turn-off several times before the load current direction changes. Let us consider the time instant when instantaneous load current is entering the star end of the load in Fig. 33.3(b). Now with the assumed load current direction when Q 1 is given turn-on signal current flows from positive dc supply, through transistor Q 1, to load. Next, when Q 1 is turned-off and Q 2 is turned on (but load current direction remaining unchanged) the load current finds its path through diode of lower switch (D 2 ). Whether D 2 or Q 2 conducts, voltage drop across SW 2 is virtually zero and it can be considered as a closed or a fully-on switch. In the following switching cycle when Q 1 is turned on again (load current direction still unchanged) the load current path reverts back from D 2 to Q 1. It may not be difficult to see how this happens. While current flowed through D 2 the load circuit got connected to negative emf (-E) of the supply. When Q 1 conducts the positive (+E) emf supports the load current. The natural choice for load current is to move from D 2 to Q 1. In fact turning on of Q 1 will make D 2 reverse biased. The reader may repeat a similar exercise when the instantaneous load current comes out of the star end of load. Thus it will be evident that diodes do not need a separate command to turn on and off. Irrespective of the load current direction, turning on of Q 1 makes SW 1 on and Version 2 EE IIT, Kharagpur 7

151 similarly turning off of Q 1 (with simultaneous turn-on of Q 2 ) makes SW 2 on. Q 1 and Q 2 are turned on in a complementary manner. It may not be difficult to see that the circuit of Fig. 33.3(b) will work satisfactorily for a purely resistive load and a series connected resistorcapacitor load too. The push-pull circuit of Fig. 33.3(b) has some technical demerits that have been discussed below. First, it needs a bipolar dc supply with identical magnitudes of positive and negative supply voltages. For practical reasons it would have been simpler if only one (uni-polar) dc source was required. In fact some circuit topologies realize a bi-polar dc supply by splitting the single dc voltage-source through capacitive potential divider arrangement. [A resistive potential divider will be terribly inefficient.] Two identical capacitors of large magnitude are put across the dc supply and the junction point of the capacitors is used as the neutral (ground) point of the bipolar dc supply. Fig. 33.3(c) shows one such circuit where a single dc supply has been split in two halves. In such circuits the voltages across the two capacitors may not remain exactly balanced due to mismatch in the loading patterns or mismatch in leakage currents of the individual capacitors. Also, unless the capacitors are of very large magnitude, there may be significant ripple in the capacitor voltages, especially at low switching frequencies. The requirement of splitting a single dc source is eliminated if a full bridge circuit, as mentioned in the next section, is used. The second demerit of the push-pull circuit shown in Fig. 33.3(b) is the requirement of two different kinds of transistors, one n-p-n type and the other p-n-p type. The switching speeds of n- p-n and p-n-p transistors are widely different unless they are produced carefully as matched pairs. In power electronic applications, n-p-n transistors are preferred as they can operate at higher switching frequencies. Similarly n-channel MOSFETs and IGBTs are preferred over their p-channel counterparts. The difficulty in using two n-p-n transistors in the above discussed pushpull circuit is that they can no longer have a common base and a common emitter point and thus it won t be possible to have a single base drive signal for controlling both of them. The base signals for the individual transistors will then need to be separate and isolated from each other. The difficulty in providing isolated base signals for the two transistors is, often, more than compensated by the improved capability of the circuit that uses both n-p-n transistors or n- channel IGBTs. The circuit in Fig. 33.3(c) shows identical transistors (n-channel IGBTs) for both upper and lower switches. The gate drive signals of the two transistors (IGBTs) now need to be different and isolated as the two emitter points are at different potentials. The circuit in Fig. 33.3(c) is better known as a half bridge inverter. Version 2 EE IIT, Kharagpur 8

152 P + _ 0.5E dc Q 1 D 1 E dc + _ O LOAD A + _ 0.5E dc Q 2 D 2 N Fig. 33.3(c): Topology of a 1-phase half bridge VSI 33.3 General Structure of Voltage Source Inverters Figs (a) and 33.4(b) show the typical power-circuit topologies of a single-phase and a three-phase voltage source inverter respectively. These topologies require only a single dc source and for medium output power applications the preferred devices are n-channel IGBTs. E dc is the input dc supply and a large dc link capacitor (C dc ) is put across the supply terminals. Capacitors and switches are connected to dc bus using short leads to minimize the stray inductance between the capacitor and the inverter switches. Needless to say that physical layout of positive and negative bus lines is also important to limit stray inductances. Q 1, Q 2, Q 3 etc. are fast and controllable switches. D 1, D 2, D 3 etc. are fast recovery diodes connected in anti-parallel with the switches. A, B and C are output terminals of the inverter that get connected to the ac load. A three-phase inverter has three load-phase terminals whereas a single-phase inverter has only one pair of load terminals. The current supplied by the dc bus to the inverter switches is referred as dc link current and has been shown as i dc in Figs 33.4(a) and 33.4(b). The magnitude of dc link current often changes in step (and some times its direction also changes) as the inverter switches are turned on and off. The step change in instantaneous dc link current occurs even if the ac load at the inverter output is drawing steady power. However, average magnitude of the dc link current remains positive if net power-flow is from dc bus to ac load. The net power-flow direction reverses if the ac load connected to the inverter is regenerating. Under regeneration, the mean magnitude of dc link current is negative. [The dc link current may conceptually be decomposed into its dc and ac components. The individual roles of the dc voltage source and the dc link capacitor may be clearly seen with respect to the dc and ac components of the dc link current. For the dc component of current the capacitor acts like open circuit. As expected, under steady state, the capacitor does not supply any dc current. The dc part of bus current is supplied solely by the dc source. A practical dc voltage source may have some resistance as well as some inductance in series with its internal emf. For dc component of bus current, the source voltage appears in series with its internal resistance (effect of source inductance is not felt). But for ac component of current, the internal dc emf of source appears as short and its series impedance (resistance in series with inductance) appears in parallel with the dc-link Version 2 EE IIT, Kharagpur 9

153 capacitor. Thus the ac component of current gets divided into these two parallel paths. However, the high frequency component of ac current mainly flows through the capacitor, as the capacitive impedance is lower at high frequencies. The step change in dc link current is associated with significant amount of high frequency components of current that essentially finds its path through the capacitor.] For an ideal input (dc) supply, with no series impedance, the dc link capacitor does not have any role. However a practical voltage supply may have considerable amount of output impedance. The supply line impedance, if not bypassed by a sufficiently large dc link capacitor, may cause considerable voltage spike at the dc bus during inverter operation. This may result in deterioration of output voltage quality, it may also cause malfunction of the inverter switches as the bus voltage appears across the non-conducting switches of the inverter. Also, in the absence of dc link capacitor, the series inductance of the supply line will prevent quick build up or fall of current through it and the circuit behaves differently from the ideal VSI where the dc voltage supply is supposed to allow rise and fall in current as per the demand of the inverter circuit. [It may not be possible to reduce supply line inductance below certain limit. Most dc supplies will inherently have rather significant series inductance, for example a conventional dc generator will have considerable armature inductance in series with the armature emf. Similarly, if the dc supply is derived after rectifying ac voltage, the ac supply line inductance will prevent quick change in rectifier output current. The effect of ac line inductance is reflected on the dc side as well, unless this inductance is effectively bypassed by the dc side capacitor. Even the connecting leads from the dc source to the inverter dc bus may contribute significantly to the supply line inductance in case the lead lengths are large and circuit lay out is poor. It may be mentioned here that an inductance, in series with the dc supply, may at times be welcome. The reason being that for some types of dc sources, like batteries, it is detrimental to carry high frequency ripple current. For such cases it is advantageous if the dc source has some series inductance. Due to series inductance of the source, the high frequency ripple will prefer to flow through the dc link capacitor and thus relieve the dc source.] The dc link capacitor should be put very close to the switches so that it provides a low impedance path to the high frequency component of the switch currents. The capacitor itself must be of good quality with very low equivalent series resistor (ESR) and equivalent series inductor (ESL). The length of leads that interconnect switches and diodes to the dc bus must also be minimum to avoid insertion of significant amount of stray inductances in the circuit. The overall layout of the power circuit has a significant effect over the performance of the inverter circuit. Version 2 EE IIT, Kharagpur 10

154 i dc i dc Q 1 D 1 Q 3 D 3 Q 1 D 1 Q 3 D 3 Q 5 D 5 E dc + _ C dc A LOAD B E dc + _ C dc A B C Q 2 D 2 Q 4 D 4 Q 2 D 2 Q 4 D 4 Q 6 D 6 Fig. 33.4(a): Topology of a 1-phase VSI Fig. 33.4(b): Topology of a 3-phase VSI [One of the thumb rules for good circuit layout is to put the conductor pairs carrying same magnitude but opposite direction of currents close by, the minimum distance between them being decided only by their voltage isolation requirement. Thus the positive and negative terminals of the dc bus should run close by. A twisted wire pair may be an example of two closely running wires.] The details of the inverter circuits shown in Figs. 33.4(a) and 33.4(b) are discussed in later lessons. However it may be mentioned here that these circuits are essentially extension of the half bridge circuit shown in Fig. 33.3(c). For example, the single-phase bridge circuit of Fig. 33.4(a) may be thought of as two half-bridge circuits sharing the same dc bus. Thus the single phase full-bridge (often, simply called as bridge ) circuit has two legs of switches, each leg consisting of an upper switch and a lower switch. Junction point of the upper and lower switches is the output point of that particular leg. Voltage between output point of legs and the midpotential of the dc bus is called as pole voltage referred to the mid potential of the dc bus. One may think of pole voltage referred to negative bus or referred to positive bus too but unless otherwise mentioned pole voltages are assumed to be referred to the mid-potential of the dc bus. The two pole voltages of the single-phase bridge inverter generally have same magnitude and frequency but their phases are apart. Thus the load connected between these two pole outputs (between points A and B ) will have a voltage equal to twice the magnitude of the individual pole voltage. The pole voltages of the 3-phase inverter bridge, shown in Fig. 33.4(b), are phase apart by each Need For Isolated Gate-Control Signals For The Switches As already mentioned the switches in bridge configurations of inverters, as in Figs. 33.3(c), 33.4(a) and 33.4(b), need to be provided with isolated gate (or base) drive signals. The individual control signal for the switches needs to be provided across the gate (base) and source (or emitter) terminals of the particular switch. The gate control signals are low voltage signals referred to the source (emitter) terminal of the switch. For n-channel IGBT and MOSFET switches, when gate to source voltage is more than threshold voltage for turn-on, the switch turns on and when it is less than threshold voltage the switch turns off. The threshold voltage is generally of the order of +5 volts but for quicker switching the turn-on gate voltage magnitude is kept around +15 volts Version 2 EE IIT, Kharagpur 11

155 where as turn-off gate voltage is zero or little negative (around 5 volts). It is to be remembered that the two switches of an inverter-leg are controlled in a complementary manner. When the upper switch of any leg is on, the corresponding lower switch remains off and vice-versa. When a switch is on its emitter and collector terminals are virtually shorted. Thus with upper switch on, the emitter of the upper switch is at positive dc bus potential. Similarly with lower switch on, the emitter of upper switch of that leg is virtually at the negative dc bus potential. Emitters of all the lower switches are solidly connected to the negative line of the dc bus. Since gate control signals are applied with respect to the emitter terminals of the switches, the gate voltages of all the upper switches must be floating with respect to the dc bus line potentials. This calls for isolation between the gate control signals of upper switches and between upper and lower switches. Only the emitters of lower switches of all the legs are at the same potential (since all of them are solidly connected to the negative dc bus) and hence the gate control signals of lower switches need not be isolated among themselves. As should be clear from the above discussion, the isolation provided between upper and lower switches must withstand a peak voltage stress equal to dc bus voltage. Gate-signal isolation for inverter switches is generally achieved by means of optical-isolator (opto-isolator) circuits. Fig.33.5 shows a typical optoisolator circuit. The circuit makes use of a commercially available opto-coupler IC, shown within dotted lines in the figure. Input stage of the IC is a light emitting diode (LED) that emits light when forward biased. The light output of the LED falls on reverse biased junction of an optical diode. The LED and the photo-diode are suitably positioned inside the opto-coupler chip to ensure that the light emitted by the LED falls on the photo-diode junction. The gate control pulses for the switch are applied to the input LED through a current limiting resistor of appropriate magnitude. These gate pulses, generated by the gate logic circuit, are essentially in the digital form. A high level of the gate signal may be taken as on command and a low level (at ground level) may be taken as off command. Under this assumption, the cathode of the LED is connected to the ground point of the gate-logic card and anode is fed with the logic card output. The circuit on the output (photo-diode) side is connected to a floating dc power supply, as shown in Fig The control (logic card) supply ground is isolated from the floating-supply ground of the output. In the figure the two grounds have been shown by two different symbols. The schematic connection shown in the figure indicates that the photo-diode is reverse biased. A resistor in series with the diode indicates the magnitude of the reverse leakage current of the diode. When input signal to LED is high, LED conducts and the emitted light falls on the reverse biased p-n junction. Irradiation of light causes generation of significant number of electron-hole pairs in the depletion region of the reverse biased diode. As a result magnitude of reverse leakage current of the diode increases appreciably. The resistor connected in series with the photo-diode now has higher voltage drop due to the increased leakage current. A signal comparator circuit senses this condition and outputs a high level signal, which is amplified before being output. Thus an isolated and amplified gate signal is obtained and may directly be connected to the gate terminal of the switch (often a small series resistor, as suggested by the switch manufacturer, is put between the output signal and the gate terminal of the switch). Version 2 EE IIT, Kharagpur 12

156 +V CC (floating) Photo-diode L E D Signal comparator and power amplifier circuit Output Control Ground Floating Ground Fig.33.5: A schematic opto-isolator circuit 33.5 Classification of Voltage Source Inverters Voltage source inverters can be classified according to different criterions. They can be classified according to number of phases they output. Accordingly there are single-phase or three-phase inverters depending on whether they output single or three-phase voltages. It is also possible to have inverters with two or five or any other number of output phases. Inverters can also be classified according to their ability in controlling the magnitude of output parameters like, frequency, voltage, harmonic content etc. Some inverters can output only fixed magnitude (though variable frequency) voltages whereas some others are capable of both variable voltage, variable frequency (VVVF) output. Output of some voltage source inverters is corrupted by significant amount of many low order harmonics like 3 rd, 5 th, 7 th, 11 th, 13 th order of the desired (fundamental) frequency voltage. Some other inverters may be free from low order harmonics but may still be corrupted by some high order harmonics. Inverters used for ac motor drive applications are expected to have less of low order harmonics in the output voltage waveform, even if it is at the cost of increased high order harmonics. Higher order harmonic voltage distortions are, in most ac motor loads, filtered away by the inductive nature of the load itself. Inverters may also be classified according to their topologies. Some inverter topologies are suitable for low and medium voltage ratings whereas some others are more suitable for higher voltage applications. The inverters shown in Figs. 33.3(c), 33.4(a) and 33.4(b) are two level inverters as the pole voltages may acquire either positive dc bus or negative dc bus potential. For higher voltage applications it may not be uncommon to have three level or five level inverters. Quiz Problems 1. A large capacitor, put across dc bus of a voltage source inverter, is intended to: (a) allow a low impedance path to the high frequency component of dc link current. (b) to minimize high frequency current ripple through the ideal dc source. (c) to maintain a constant dc link current. (d) to protect against switch failure. 2. A diode in anti-parallel with the controlled switch, like IGBT, is used in VSI to: (a) prevent reversal of dc link current. Version 2 EE IIT, Kharagpur 13

157 (b) allow a non-unity power factor load at the output. (c) protect the circuit against accidental reversal of dc bus polarity. (d) none of the above. 3. The inverter switches work in fully-on or fully-off mode to achieve: (a) easier gate control circuit for the switching devices. (b) minimum distortion in the output voltage waveform. (c) reduced losses in the switches. (d) satisfactory operation for non-resistive load at the output. 4. Gate (base) signals to the VSI switches, using n-channel IGBTs, need to be isolated to allow: (a) protection of switches against short at the inverter output terminals. (b) switches to be connected in bridge fashion. (c) lower losses in the gate drive circuit. (d) a dc link voltage higher than the switch voltage rating. (Answers to the quiz problems: 1-a, 2-b, 3-c, 4-b) Version 2 EE IIT, Kharagpur 14

158 Module 5 DC to AC Converters Version 2 EE IIT, Kharagpur 1

159 Lesson 34 Analysis of 1-Phase, Square - Wave Voltage Source Inverter Version 2 EE IIT, Kharagpur 2

160 After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Explain the operating principle of a single-phase square wave inverter. Compare the performance of single-phase half-bridge and full-bridge inverters. Do harmonic analysis of load voltage and load current output by a single-phase inverter. Decide on voltage and current ratings of inverter switches. Voltage source inverters (VSI) have been introduced in Lesson-33. A single-phase square wave type voltage source inverter produces square shaped output voltage for a single-phase load. Such inverters have very simple control logic and the power switches need to operate at much lower frequencies compared to switches in some other types of inverters, discussed in later lessons. The first generation inverters, using thyristor switches, were almost invariably square wave inverters because thyristor switches could be switched on and off only a few hundred times in a second. In contrast, the present day switches like IGBTs are much faster and used at switching frequencies of several kilohertz. As pointed out in Lesson-26, single-phase inverters mostly use half bridge or full bridge topologies. Power circuits of these topologies are redrawn in Figs. 34.1(a) and 34.1(b) for further discussions. P P i dc C + _ 0.5E dc Sw1 Sw1 Sw3 E dc + _ O LOAD A E dc + _ C dc A LOAD B C + _ 0.5E dc Sw2 N Fig. 34.1(a): A 1-phase half bridge VSI Sw2 Sw4 N Fig. 34.1(b): A 1-phase full-bridge VSI In this lesson, both the above topologies are analyzed under the assumption of ideal circuit conditions. Accordingly, it is assumed that the input dc voltage (E dc ) is constant and the switches are lossless. In half bridge topology the input dc voltage is split in two equal parts through an ideal and loss-less capacitive potential divider. The half bridge topology consists of one leg (one pole) of switches whereas the full bridge topology has two such legs. Each leg of the inverter consists of two series connected electronic switches shown within dotted lines in the figures. Each of these switches consists of an IGBT type controlled switch across which an uncontrolled diode is put in anti-parallel manner. These switches are capable of conducting bi-directional current but they need to block only one polarity of voltage. The junction point of the switches in each leg of the inverter serves as one output point for the load. In half bridge topology the single-phase load is connected between the mid-point of the input dc supply and the junction point of the two switches (in Fig. 34.1(a) these points are marked as O and A respectively). For ease of understanding, the switches Sw1 and Sw2 may be assumed to Version 2 EE IIT, Kharagpur 3

161 be controlled mechanical switches that open and close in response to the switch control signal. In fact in lesson-33 (section 33.2) it has been shown that the actual electronic switches mimic the function of the mechanical switches. Now, if the switches Sw1 and Sw2 are turned on alternately with duty ratio of each switch kept equal to 0.5, the load voltage (V AO ) will be square wave with a peak-to-peak magnitude equal to input dc voltage (E dc ). Fig. 34.2(a) shows a typical load voltage waveform output by the half bridge inverter. V AO acquires a magnitude of +0.5 E dc when Sw1 is on and the magnitude reverses to -0.5 E dc when Sw2 is turned on. Fig also shows the fundamental frequency component of the square wave voltage, its peak-to-peak magnitude being equal to 4. The two switches of the inverter leg are turned on in a complementary Edc π manner. For a general load, the switches should neither be simultaneously on nor be simultaneously off. Simultaneous turn-on of both the switches will amount to short circuit across the dc bus and will cause the switch currents to rise rapidly. For an inductive load, containing an inductance in series, one of the switches must always conduct to maintain continuity of load current. In Lesson-33 (section 33.2) a case of inductive load has been considered and it has been shown that the load current may not change abruptly even though the switching frequency is very high. Such a situation, as explained in lesson-33, demands that the switches must have bidirectional current carrying capability Harmonic Analysis of The Load Voltage And Load Current Waveforms The load voltage waveform shown in Fig. 34.2(a) can be mathematically described in terms of its Fourier s components as: 2Edc VAO = sin( ) nπ nwt (34.1) n= 1,3,5,7,...,,where n is the harmonic order and w is the frequency ( f ) of the square wave. f also 2 π happens to be the switching frequency of the inverter switches. As can be seen from the expression of Eqn. 34.1, the square wave load voltage consists of all the odd harmonics and their magnitudes are inversely proportional to their harmonic order. Accordingly, the fundamental Version 2 EE IIT, Kharagpur 4