Analysis and Design of Low-Phase-Noise Ring Oscillators

Transcription

1 Analysis and Design o Low-Phase-Noise Ring Oscillators Liang Dai and Ramesh Harjani University o Minnesota Minneapolis, MN 55455, USA harjani@ece.umn.edu ABSTRACT This paper presents a ramework or CMOS ring oscillator phase noise analysis or given power consumption speciications. This model considers both linear and nonlinear operations. It indicates that ast rail-to-rail switching has to be achieved or low phase noise and that the up-conversion o low-requency noise rom the current bias/control circuit can be signiicant. Our phase noise model is validated via simulation and measurement results. We also present a coupled-ring oscillator whose phase noise is 114dBc/Hz at a 600kHz oset rom the 960MHz carrier requency. 1. INTRODUCTION Voltage-controlled oscillators (VCO) are important building blocks in phase-locked loops (PLLs). The random luctuations in the output phase o the oscillator, in terms o jitter or phase noise, are extremely undesirable in most applications. The design o CMOS VCOs with low phase noise is an active research topic [1,, 3]. Due to their ease o implementation and large tuning range, CMOS ring oscillators are attractive candidates or system-on-a-chip designs. However, their phase noise perormance is usually worse than those with high-q resonant elements. There is direct trade-o between the power consumption and the oscillator phase noise perormance. It is desirable to minimize the phase noise or a given power consumption budget. In this paper we irst present a modiied linear phase noise model or ring oscillators. Modiications include the non-linear operation caused by voltage clipping. Next we extend this model to include the up-conversion o the low-requency noise rom the bias/tail devices. Finally, we validate our model via simulations and measurement results.. PHASE NOISE ANALYSIS In this section, we will derive the relation between the phase noise and the internal signal swing rom a simpliied model. Permission to make digital or hard copies o all or part o this work or personal or classroom use is granted without ee provided that copies are not made or distributed or proit or commercial advantage and that copies bear this notice and the ull citation on the irst page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior speciic permission and/or a ee. ISLPED '00, Rapallo,, Rapallo, Italy. Italy. Copyright 000 ACM /00/ $ Gm R C Limiter -Gm R C Limiter -Gm R C Limiter Figure 1: Modiied linear model or a 3-stage ring VCO Figure : supplies Sinusoidal waveorm clipped by power We show that, or a given power consumption speciication, in order to achieve phase noise comparable to LC-tank oscillators, sharp rail-to-rail voltage swings are needed, i.e., devices have to be switched on and o completely. Figure 1 shows a simpliied model or a 3-stage ring oscillator. The system is linear as long as the internal voltages are not clipped by the limiters. For this condition the singlesideband (SSB) phase noise can be shown to be represented by eqn.(1) [], where k is the Boltzmann s constant and T is the absolute temperature. The excess noise actor F accounts or the total noise rom the resistor R and the active device ( G m) [4]. V pp represents the peak-to-peak signal voltage. Here, we have only considered thermal noise. L{} = 64FkTR 9V pp (1) In reality, the waveorm is bounded by the power supplies or large amplitudes. Let us assume that the sinusoidal waveorm is symmetrically clipped as shown in Figure. Its Impulse Sensitivity Function (ISF or Γ) [3] can be approximated by Γ(ωt) = dv(ωt)/d(ωt) { dv(ωt)/d(ωt) max V pp cos (ωt) (or Vpp sin (ωt) < V dd ) 0 (or Vpp sin (ωt) V dd ) Hence eqn.(1) has to be modiied or V pp >V dd as shown in 89

2 eqn.(). Figure 3: Waveorm with sot slipping L{}= 18FkTR 9πV pp 56FkTRV dd 9πV 3 pp [ arcsin ( Vdd V pp ) ] + V dd V pp 1 V dd Vpp (or V pp V dd ) We use V pp in eqn.() to represent the peak-to-peak voltage o the sinusoidal waveorm as i there was no clipping. Eqns.(1) and () indicate that the phase noise is proportional to 1/Vpp or linear operation and is proportional to 1/Vpp 3 when clipped by the power supplies. The additional noise reduction results rom the act that Γ(ωt) is 0 when the voltage is clipped. Hence the period when the oscillator is susceptible to noise is reduced as the transitions take less time. In reality, the clipping is rarely as hard as shown in Figure. We model this sot clipping, shown in Figure 3 by v(ωt) = Vdd [ ] tanh Vpp sin (ωt) V dd The ISF is now given by eqn. (3) and the phase noise is then given by eqn.(4) L() = Γ(ωt) = 64FkTR 9V pp () cos (ωt) [ ] (3) V pp cosh Vpp V dd sin (ωt) 51FkTRV dd 7πV 3 pp (or V pp 8V dd 3π ) (or V pp 8V dd 3π ) (4) In Figure 4 we show the SSB phase noise at 600kHz oset rom a 900MHz carrier requency as a unction o dierent signal voltage swings predicted by both hard clipping and sot clipping models. Here we assume that F =4,R =1kΩ and V dd =3.3V. Both results indicate that the phase noise consists o two regions with regard to V pp: a1/vpp region without clipping and 1/Vpp 3 with clipping. The two equations provide slightly dierent break-even points between the two regions. The break-even point or the hard clipped model is V pp = V dd. While the break-even point or the sot clipped model is V pp =8V dd /(3π) 0.85V dd. The phase noise values predicted by the two models are the same or small values o V pp and only dier by 1.76dB or large values o V pp. Both models provide similar predictions or the phase noise. Hence, we expect the exact shape o the waveorm not to signiicantly impact the phase noise perormance. The models SSB Phase Noise (dbc/hz) LC-tank Our measurements Hard clipping -130 Reported results or LC-tank Sot clipping Vpp (V) Figure 4: SSB phase noise vs. V pp also suggest the additional reduction in phase noise when the voltage swing tends to exceed the power supply (V pp >V dd ). I active devices are used as loads instead o passive resistors, eqn.(4) has to be modiied slightly. The resistor thermal noise 4kT/R has to be replaced by 4γkTg ds0 or the active devices. The same derivation still holds. Eqn.(4) can now be rewritten as shown in eqn.(5), where I pp is the peak-to-peak current. Maximizing V pp is equivalent to maximizing the switching current. Eqn.(5) suggests that or a given power supply current, improving the current switching eiciency can reduce the phase noise. For a ully dierential ring oscillator with tail current supply, an ideal case would be that all the tail current is used or switching, i.e., a current switching eiciency o 100. In other circuit topologies, the maximal current or charging and discharging the load capacitors sets a lower bond on the phase noise or a given power. 64FγkTg ds0 (or V 9Ipp L() = pp 8V dd ) 3π 51FγkTg ds0 V dd (or V 7πIpp Vpp pp 8V dd ) 3π (5) The trade-o between power consumption and phase noise can also be seen rom eqn.(5). A simple way o scaling power consumption is to scale the device sizes. I all the device sizes are scaled by a actor o α, the internal currents will be scaled by α, and all the node voltages will remain unchanged. As a result, the power consumption is scaled by α. According to eqn.(5), when g ds0 becomes αg ds0 and I pp becomes αi pp, the phase noise is scaled by 1/α. Thereore, the phase noise is inversely proportional to the oscillator power consumption. In other words, the phase noise can be reduced by 3dB by doubling the power consumption. Another intuitive explanation to the trade-o between phase noise and power consumption is that when the device sizes are doubled, the signal doubles in amplitude and the noise only doubles in power. This results in a 3dB improvement in SNR. The remaining question to be answered is how to minimize the phase noise or a given power consumption. 90

3 Icntrl Mb 1:m M1 M MN Figure 5: Bias structure or an N-stage ring oscillator i / n ω = ω(gm) LPF (δω)/ i n / Φ δ gm=gm(iss) (s)= ω (s)/s (δφ) / ( gm) / Figure 6: Up-conversion mechanism or low requency noise in the tail and bias A survey o published literature suggests that the phase noise o LC-tank oscillators is close to 10dBc/Hz when the results are scaled to a 600kHz oset rom a 900MHz center requency [5, 6, 7]. They are located within the dashed ellipse in Figure 4. The phase noise curve or LCtank oscillators is also plotted in this igure or F =4,R = 1kΩ and Q = 6. Our calculation suggests that the phase noise or ring oscillators is likely to be signiicantly higher than that o LC-tank oscillators unless there is rail-to-rail switching, and eicient switching is the only possible approach. Figure 4 also shows the measurement results or our ring oscillators that match our analysis. Details are provided in a later section. 3. NOISE UP-CONVERSION In a ully dierential ring oscillator low-requency noise rom the bias and the tail devices is up-converted to the vicinity o the carrier requency by requency modulation. This is not modeled by our previous analysis or any previously published work. In this section, we analyze this noise upconversion mechanism and later validate it via simulations. An N-stage ring oscillator is generally biased as shown in Figure 5. Noise in the tail current causes the g m o the delay cell to change, hence varying the instantaneous oscillation requency. We will irst consider thermal noise, and then extend our analysis to include licker noise. This up-conversion mechanism is illustrated in Figure 6. First, the noise is band-limited by the poles at the drains o M b, M 1, M,..., M N. This low-pass iltered noise then modulates the g m o the delay cells, and results in requency ω(τ)dτ in the time domain, they satisy Φ(s) = Ω(s)/s in s-domain. The phase noise has a 1/ shape at low oset requencies and drops o at a aster rate or higher oset requencies. However, variation. Finally, since φ(t) = t since the low-pass bandwidth is usually in the same order as or even larger than the oscillation requency, the aster phase noise roll-o is rarely observed and it is o little interest. Additionally, we are usually more concerned with the up-conversion o the low-requency noise. This is more o an issue when licker noise is present and causes the phase noise to rise at a more rapid rate at low oset requencies. We treat the noise rom the bias transistor M b separately rom the noise contributed by transistors M 1,..N in Figure 5, because the noise rom M b is correlated or all stages while the noise rom M 1,..N is not. In the ollowing derivation, we assume that the current mirrors have a ratio o 1 : m as shown in Figure 5. In general, the oscillation requency is proportional to g m/c L, where C L is the load capacitance or the delay cell. As an example, = ( 3/)(g m/c L) or a 3-stage ring oscillator. Even though C L includes a voltage-dependent part, its variation is usually much smaller than the variation o g m in the presence o noise. We can thereore derive the relation in eqn.(6) using this assumption. δω = δg m (6) When operated in the long channel regime, the g m o each delay cell is given by g m = (k WI ss)/l, where I ss is the tail current. This is valid or all the reasonable gate overdrive voltages [8]. Considering eqn.(6), it can be shown that eqn.(7) is valid. δω = δg m = 1 δiss (7) g m The thermal noise density rom M b is i n/ =4kTγg ds0,b, where g ds0,b is the g ds0 or M b. The noise power is ampliied by m times by each tail device. We can also replace mg ds0,b with g ds0 or the tail devices. Hence the normalized variation in requency is given by eqn.(8). (δω / ω 0 g m = (δgm) / g m I ss = mkt γg ds0 I ss Finally we can write the resulting phase noise as shown in eqn.(9). (δφ = 1 (δω) = = mkt γg ds0 I ss (δω) / ω0 ( ω0 (8) (9) The noise rom M 1 to M N are treated in a similar manner to the noise rom M b except that the noise is uncorrelated or each tail device. Eqn.(7) has to be modiied as shown in eqn.(10) where g m,i and I ss,i are the g m and I ss or the ith delay cell. δω = 1 N δgm,i = 1 N δiss,i (10) g m,i I ss,i 91

4 Considering that there are N delay stages, the resulting phase noise expression is given by eqn.(11). Vdd (δφ = ktγg ds0 NI ss (11) M4 M5 The SSB phase noise L() is1/4 o(δφ /, since the phase noise is split equally on both sides o the carrier. Thereore, the total noise contributed by the bias transistor M b (eqn.(9)) and the N tail devices (eqn.(11)) is given by eqn.(1). L() = 1 (δφ 4 = ( 1 N + m) ktγg ds0 4I ss (1) Icntrl M6 Vout- Vin+ 3 1:m M M3 1 M1 Vout+ Vin- The up-conversion o licker noise can be treated in a similar ashion. I the licker noise is modeled as [9] i n = K I A ds C oxl e where K and A are licker noise parameters. Then eqn.(1) can be modiied or licker noise as shown in eqn.(13). L() = π( 1 N + m)k ω 0 8C oxl e I A ss 3 (13) Since m is usually much larger than 1/N, the up-conversion o the noise rom M b is likely to be more severe than that rom the tail devices. In practice, the licker noise rom M b could be a major noise source at low oset requencies. This is conirmed by our simulation and measurement results in the ollowing sections. 4. SIMULATION RESULTS In this section, we simulate the phase noise or a ring oscillator and show that the low requency noise in the current bias/control can aect the phase noise signiicantly. We also veriy the noise up-conversion process analyzed in the previous section. We consider the circuit in Figure 7 as an example. M 1 M 5 is a delay cell o a 3-stage ring oscillator and the current bias and requency control are supplied through M 6 (Figure5). We apply the analysis methodology proposed in [3] by injecting a current pulse into the nodes 1, and 3 throughout a complete clock cycle and observe the phase shit ater it settles into steady state again. The eective ISFs(Γ e s) which are modulated by the thermal and licker noise are calculated or each individual device. As mentioned in [3] or thermal noise the RMS values or the Γ e s is important and or licker noise the mean values o the Γ e s is important. Table 1 lists the RMS values or Γ e,thermal s and mean values or Γ e,licker s or all the transistors in the delay cell. It can be seen that the thermal noise contribution o all the devices are similar in magnitude, though the contribution o M,3 is slightly larger than the others. However, or licker noise the contributions o M 1 Figure 7: Dierential delay cell and bias transistor RMS/Mean or Γ M 1 M,3 M 4,5 M 6 Thermal (deg/sec 1/ Flicker (deg/sec) Table 1: Γ RMS,e,thermal and Γ e,licker and M 6 dominate, suggesting that the majority o the low requency phase noise is contributed by the bias devices. We have only included a single device M 6 in the bias. In reality, more devices are oten used or the bias. For example, a voltage-to-current converter is usually needed between the loop ilter and the VCO in a PLL. Any low requency noise generated in I cntrl is equivalent to an increase in the noise rom M 6 and could potentially dominate the low-requency phase noise. We veriy our noise up-conversion analysis by using the circuit in Figure 7. We vary the bias current, and observe the variation in requency in the steady state. Assuming I ss is proportional to I cntrl and ω/ I ss is the same or DC and any low requency noise in I ss, we veriy eqn.(7) in the previous section. Figure 8 provides the comparison between δω/ω and δi cntrl /I cntrl. In Figure 8, both δω/ω and δi cntrl /I cntrl are drawn as unctions o the bias current. In the simulation, δi cntrl is given a ixed value so that I cntrl is swept linearly. Thereore, the curve o δi cntrl /Icntrl drops at a slope o 0dB/decade. The two curves match extremely well or low bias currents. The error increases with larger bias current because o short channel eects and current mirror mismatch due to the channel length modulation. To take into account o short channel eects, the drain-tosource current can be modeled as shown in eqn.(14) [10]. I D = β (1 ɛ1)(vgs VT ) ɛ (14) where ɛ 1 and ɛ are empirical numbers. They approach 0 9

5 vs. I cntrl /I cntrl (db) / I cntrl /I cntrl Bias Current (ua) Figure 8: Simulation o requency variation vs. bias current variation or long channel devices and take on larger values or short channel devices. By ollowing a similar derivation as above, it can be shown that δω = 1 ɛ ɛ δiss I ss The actor (1 ɛ )/( ɛ ) becomes smaller or short channel devices. This explains why the curve δω/ drops more rapidly or large bias currents. As a result, both eqns. (1) ( and (13) have to be multiplied by 4 1 ɛ ɛ to account or short channel eects. When I cntrl increases, the mismatch between the drain voltages o M b and M 1 increases. This causes I ss not to increase as much as I cntrl. As a result, the oscillation requency becomes less sensitive to I cntrl, and the curve o δω/ alls urther below the curve o δi cntrl /I cntrl in Figure 8 or the increased bias currents. Despite the short channel eects and current mirror mismatch, our simulations conirm our model or noise upconversion. Our conclusions are urther strengthened by our measurement results in the next section. 5. EXPERIMENTAL RESULTS In addition to the ully dierential oscillator shown in Figure 7, we also designed the coupled-ring oscillator shown in Figure 9. Weighted current adders are used to determine how much current is drawn rom the ast and slow inverters to charge and discharge the load capacitors. Thereore, the oscillator requency is continuously tuned between the requencies set by the ast and slow inverters. We achieve complete rail-to-rail switching by using digital inverters. Additionally, this eliminates the current mirror bias structure. For both these reasons we expect less phase noise rom this circuit than rom the circuit in Figure 7. Both oscillator designs were abricated via MOSIS in a 0.5µm CMOS technology. Micro photographs or both designs are shown in Figs. 10 (a) and (b). Their outputs are measured with a spectrum analyzer and resulting phase Vin in1 in F S Weighted Current Adder (a) (c) Weighted Current Adder out in1 in Vout out F S Fast Slow (b) M M1 (d) M (wide) M1 (wide) M (narrow) M1 (narrow) Figure 9: coupled-ring oscillator (a) delay cell (b) strong and weak inverters (c) weighted current adder (d) complementary control generator noise is computed by taking the noise power spectral density normalized by the carrier power. Figure 10: Die photo or (a) the ring oscillator rom Figure 7 (b) the coupled-ring oscillator rom Figure 9 Figure 11 shows two experimental results or the dierential oscillator rom Figure 7 with a 1.38GHz center requency. In the irst experiment, a 100µF by-pass capacitor is connected between the bias point and ground so that most o the noise rom M 6 is iltered out and does not cause phase noise. In the second experiment, a 11.7nF capacitor is used instead. Due to the higher low-pass corner requency, some o the low requency noise rom M6 is up-converted to phase noise by requency modulation. With a large by-pass capacitor, the phase noise curve alls well into the 1/ region. With a small by-pass capacitor, the phase noise curve starts to rise at low oset requencies and enters the 1/ 3 region. This implies that the licker noise rom the bias transistor can dominate at low requencies which conirms our previous theoretical analysis. In practice, the bias point is an internal node and no large o-chip capacitor is available to by-pass the licker noise rom M 6. Thereore, or an integrated VCO design, the current mirror bias structure should be avoided i possible. The SSB phase noise or the coupled-ring oscillator was also measured and compared with the ully dierential ring oscillator in Figure 7. The results are shown in Figure 1. The 93

6 SSB Phase Noise (dbc/hz) uF 11.7nF Oset Frequency (Hz) SSB Phase Noise (dbc/hz) Coupled ring oscillator Fully dierential ring oscillator Oset Frequency (Hz) Figure 11: Phase noise with dierent by-pass capacitors center requency or the coupled-ring oscillator is 960MHz. For a air comparison, the phase noise o the ully dierential ring oscillator is also scaled to 960MHz. The measured SSB phase noise at a 600kHz oset requency is 114dBc/Hz or the coupled-ring oscillator. As we are unable to measure the actual voltage swings without loading the oscillator, we use simulation results or V pp as a guide. Our simulation indicates an unclipped V pp =6.48V. Its phase noise is 6dB lower than that measured or the ully dierential design in Figure 7. The majority o this dierence is due to the dierence in their internal voltage swings. According to our simulation the voltage swing or the dierential oscillator is 336mV, which accounts or about 8dB/Hz dierence in the SSB phase noise. Both results are marked in Figure 4 with circled plus signs. They match our theoretical predictions very well or airly typical values or F and R (F =4,R=1kΩ). The phase noise or the coupled ring oscillator rises aster at oset requencies that are less than 300kHz. Our simulation suggests that this is mostly due to the licker noise in the ast inverters. We would expect the phase noise due to both the licker noise and the thermal noise to decrease with aster transitions in smaller geometry processes. 6. CONCLUSIONS In this paper we have analyzed ring oscillator phase noise or both linear and non-linear conditions. We show that in order to achieve good phase noise perormance, comparable with LC-tank oscillators, a rail-to-rail voltage swing is needed and the oscillator has to operate in the hard-switching mode. Under the constraint o a ixed power budget, the only way to achieve this goal is to improve current switching eiciency. We also model the low requency noise up-conversion mechanism via the current bias circuits. Our simulation shows that the up-conversion o the noise rom the devices in the bias/control circuit is signiicant and can potentially dominate the phase noise. As a result, the bias/control circuit has to be designed careully. We have also presented experimental results to conirm our theoretical analysis. The Figure 1: SSB phase noise comparison between the coupled-ring oscillator and the dierential ring oscillator in Figure 7 measured SSB phase noise or a coupled-ring oscillator was 114dBc/Hz at 600kHz oset rom the center requency o 960MHz. 7. REFERENCES [1] Todd C. Weigandt, Beomsup Kim and Paul R. Gray, Analysis o Timing Jitter in CMOS Ring Oscillators, in Proc. IEEE Int. Symp. Circuits and Systems, volume 4, pp. 7 30, London, UK, June [] Behzad Razavi, A Study o Phase Noise in CMOS Oscillators, IEEE Journal o Solid-State Circuits, vol. 31, n. 3, pp , March [3] Ali Hajimiri and Thomas H. Lee, A General Theory o Phase Noise in Electrical Oscillators, IEEE Journal o Solid-State Circuits, vol. 33, n., pp , February [4] D. B. Leeson, A Simple Model o Feedback Oscillator Noise Spectrum, in Proc. o IEEE, pp , February [5] Jan Craninckx and Michel S. J. Steyaert, A 1.8-GHz CMOS Low-Phase-Noise Voltage-Controlled Oscillator with Prescaler, IEEE Journal o Solid-State Circuits, vol. 30, n. 1, pp , December [6] Jan Craninckx and Michiel S. J. Steyaert, A 1.8-GHz Low-Phase-Noise CMOS VCO Using Optimized Hollow Spiral Inductors, IEEE Journal o Solid-State Circuits, vol. 3, n. 5, pp , May [7] Peter Kinget, A Fully Integrated.7V 0.35µm CMOS VCO or 5GHz Wireless Applications, in IEEE ISSCC Digest o Technical Papers, pp. 6 7, San Francisco, Feburary [8] Thomas H. Lee, The Design o CMOS Radio-Frequency Integrated Circuits, ch. 3, Cambridge University Press, [9] Meta-Sotware, HSPICE User s Manual: Sotware or IC Design, version 96.1 Edition, February [10] Daniel P. Foty, MOSFET Modeling With SPICE: Principles and Practice, Prentice Hall,