Ultracompact, Precision 10.0 V/5.0 V/2.5 V/3.0 V Voltage References ADR01/ADR02/ADR03/ADR06

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1 Ultracompact, Precision. V/5. V/2.5 V/3. V Voltage References ADR/ADR2/ADR3/ADR6 FEATURES Ultracompact SC7 and TSOT packages Low temperature coefficient 8-lead SOIC: 3 ppm/ C 5-lead SC7, 5-lead TSOT: 9 ppm/ C Initial accuracy ±.% No external capacitor required Low noise μv p-p (. Hz to. Hz) Wide operating range ADR: 2. V to 4. V ADR2: 7. V to 4. V ADR3: 4.5 V to 4. V ADR6: 5. V to 4. V High output current ma Wide temperature range: 4 C to +25 C ADR/ADR2/ADR3 pin compatible to industrystandard REF/REF2/REF3 PIN CONFIGURATIONS TEMP GND V IN 2 3 ADR/ ADR2/ ADR3/ ADR6 TOP VIEW (Not to Scale) 5 4 TRIM V OUT Figure. 5-Lead, SC7/TSOT Surface-Mount Packages 2 3 ADR/ ADR2/ ADR3/ ADR6 TP 8 TP V IN TEMP 7 NIC 6 V OUT GND 4 TOP VIEW 5 TRIM (Not to Scale) NIC = NO INTERNAL CONNECT TP = TEST PIN (DO NOT CONNECT) Figure 2. 8-Lead, SOIC Surface-Mount Package APPLICATIONS Precision data acquisition systems High resolution converters Industrial process control systems Precision instruments PCMCIA cards GENERAL DESCRIPTION The ADR, ADR2, ADR3, and ADR6 are precision. V, 5. V, 2.5 V, and 3. V band gap voltage references featuring high accuracy, high stability, and low power. The parts are housed in tiny, 5-lead SC7 and TSOT packages, as well as in 8-lead SOIC versions. The SOIC versions of the ADR, ADR2, and ADR3 are drop-in replacements to the industry-standard REF, REF2, and REF3. The small footprint and wide operating range make the ADRx references ideally suited for generalpurpose and space-constrained applications. With an external buffer and a simple resistor network, the TEMP terminal can be used for temperature sensing and approximation. A TRIM terminal is provided on the devices for fine adjustment of the output voltage. The ADR, ADR2, ADR3, and ADR6 are compact, low drift voltage references that provide an extremely stable output voltage from a wide supply voltage range. They are available in 5-lead SC7 and TSOT packages, and 8-lead SOIC packages with A, B, and C grade selections. All parts are specified over the extended industrial ( 4 C to +25 C) temperature range. Table. Selection Guide Part Number ADR ADR2 ADR3 ADR6 Output Voltage. V 5. V 2.5 V 3. V ADRO, ADR2, and ADR3 are component-level compatible with REF, REF2, and REF3, respectively. No guarantees for system level compatibility are implied. SOIC versions of ADR/ADR2/ADR3 are pin-to-pin compatible with 8-lead SOIC versions of REF/REF2/REF3, respectively, with the additional temperature monitoring function. Rev. J Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Pin Configurations... General Description... Revision History... 2 Specifications... 3 ADR Electrical Characteristics... 3 ADR2 Electrical Characteristics... 4 ADR3 Electrical Characteristics... 5 ADR6 Electrical Characteristics... 6 Die Electrical Characteristics... 7 Absolute Maximum Ratings... 8 ESD Caution...8 Terminology...9 Typical Performance Characteristics... Applications... 5 Applying the ADR/ADR2/ADR3/ADR Negative Reference... 6 Low Cost Current Source... 6 Precision Current Source with Adjustable Output... 6 Programmable 4 to 2 ma Current Transmitter... 7 Precision Boosted Output Regulator... 7 Outline Dimensions... 8 Ordering Guides... 9 Thermal Resistance... 8 REVISION HISTORY 3/7 Rev. I to Rev. J Renamed Parameters and Definitions Section... 9 Changes to Temperature Monitoring Section... 5 Changes to Ordering Guide /5 Rev. H to Rev. I Changes to Table Updated Outline Dimensions... 9 Changes to Ordering Guide /4 Rev. G to Rev. H Changes to ADR6 Ordering Guide /4 Rev. F to Rev. G Changes to Table Changes to Table Changes to Table Changes to Table Changes to Ordering Guide /4 Rev. E to Rev. F Changes to ADR2 Electrical Characteristics, Table Changes to Ordering Guide /4 Rev. D to Rev. E Added C grade...universal Changes to Outline Dimensions... 9 Updated Ordering Guide /3 Rev. C to Rev D Added ADR6...Universal Change to Figure /3 Rev. B to Rev C Changes to Features Section... Changes to General Description Section... Changes to Figure 2... Changes to Specifications Section...2 Addition of Dice Electrical Characteristics and Layout...6 Changes to Absolute Maximum Ratings Section...7 Updated SOIC (R-8) Outline Dimensions... 9 Changes to Ordering Guide /3 Rev. A to Rev. B Added ADR3...Universal Added TSOT-5 (UJ) Package...Universal Updated Outline Dimensions /2 Rev. to Rev. A Changes to Features Section... Changes to General Description... Table I deleted... Changes to ADR Specifications...2 Changes to ADR2 Specifications...3 Changes to Absolute Maximum Ratings Section...4 Changes to Ordering Guide...4 Updated Outline Dimensions... 2 Rev. J Page 2 of 24

3 SPECIFICATIONS ADR ELECTRICAL CHARACTERISTICS VIN = 2. V to 4. V, TA = 25 C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit OUTPUT VOLTAGE VO A and C grades V INITIAL ACCURACY VOERR A and C grades mv. % OUTPUT VOLTAGE VO B grade V INITIAL ACCURACY VOERR B grade 5 mv.5 % TEMPERATURE COEFFICIENT TCVO A grade, 8-lead SOIC, 4 C < TA < +25 C 3 ppm/ C A grade, 5-lead TSOT, 4 C < TA < +25 C 25 ppm/ C A grade, 5-lead SC7, 4 C < TA < +25 C 25 ppm/ C B grade, 8-lead SOIC, 4 C < TA < +25 C 3 ppm/ C B grade, 5-lead TSOT, 4 C < TA < +25 C 9 ppm/ C B grade, 5-lead SC7, 4 C < TA < +25 C 9 ppm/ C C grade, 8-lead SOIC, 4 C < TA < +25 C 4 ppm/ C SUPPLY VOLTAGE HEADROOM VIN VO 2 V LINE REGULATION VO/ VIN VIN = 2. V to 4. V, 4 C < TA < +25 C 7 3 ppm/v LOAD REGULATION VO/ ILOAD ILOAD = ma to ma, 4 C < TA < +25 C, 4 7 ppm/ma VIN = 5. V QUIESCENT CURRENT IIN No load, 4 C < TA < +25 C.65 ma VOLTAGE NOISE en p-p. Hz to. Hz 2 μv p-p VOLTAGE NOISE DENSITY en khz 5 nv/ Hz TURN-ON SETTLING TIME tr 4 μs LONG-TERM STABILITY VO hours 5 ppm OUTPUT VOLTAGE HYSTERESIS VO_HYS 7 ppm RIPPLE REJECTION RATIO RRR fin = khz 75 db SHORT CIRCUIT TO GND ISC 3 ma VOLTAGE OUTPUT AT TEMP PIN VTEMP 55 mv TEMPERATURE SENSITIVITY TCVTEMP.96 mv/ C The long-term stability specification is noncumulative. The drift in subsequent hour periods is significantly lower than in the first hour period. Rev. J Page 3 of 24

4 ADR2 ELECTRICAL CHARACTERISTICS VIN = 7. V to 4. V, TA = 25 C, unless otherwise noted. Table 3. Parameter Symbol Conditions Min Typ Max Unit OUTPUT VOLTAGE VO A and C grades V INITIAL ACCURACY VOERR A and C grades 5 mv. % OUTPUT VOLTAGE VO B grade V INITIAL ACCURACY VOERR B grade 3 mv.6 % TEMPERATURE COEFFICIENT TCVO A grade, 8-lead SOIC, 4 C < TA < +25 C 3 ppm/ C A grade, 5-lead TSOT, 4 C < TA < +25 C 25 ppm/ C A grade, 5-lead SC7, 4 C < TA < +25 C 25 ppm/ C A grade, 5-lead SC7, 55 C < TA < +25 C 3 ppm/ C B grade, 8-lead SOIC, 4 C < TA < +25 C 3 ppm/ C B grade, 5-lead TSOT, 4 C < TA < +25 C 9 ppm/ C B grade, 5-lead SC7, 4 C < TA < +25 C 9 ppm/ C C grade, 8-lead SOIC, 4 C < TA < +25 C 4 ppm/ C SUPPLY VOLTAGE HEADROOM VIN VO 2 V LINE REGULATION VO/ VIN VIN = 7. V to 4. V, 4 C < TA < +25 C 7 3 ppm/v VIN = 7. V to 4. V, 55 C < TA < +25 C 7 4 ppm/v LOAD REGULATION VO/ ILOAD ILOAD = ma to ma, 4 C < TA < +25 C, 4 7 ppm/ma VIN =. V ILOAD = ma to ma, 55 C < TA < +25 C, 45 8 ppm/ma VIN =. V QUIESCENT CURRENT IIN No load, 4 C < TA < +25 C.65 ma VOLTAGE NOISE en p-p. Hz to. Hz μv p-p VOLTAGE NOISE DENSITY en khz 23 nv/ Hz TURN-ON SETTLING TIME tr 4 μs LONG-TERM STABILITY VO hours 5 ppm OUTPUT VOLTAGE HYSTERESIS VO_HYS 7 ppm 55 C < TA < +25 C 8 ppm RIPPLE REJECTION RATIO RRR fin = khz 75 db SHORT CIRCUIT TO GND ISC 3 ma VOLTAGE OUTPUT AT TEMP PIN VTEMP 55 mv TEMPERATURE SENSITIVITY TCVTEMP.96 mv/ C The long-term stability specification is noncumulative. The drift in subsequent hour periods is significantly lower than in the first hour period. Rev. J Page 4 of 24

5 ADR3 ELECTRICAL CHARACTERISTICS VIN = 4.5 V to 4. V, TA = 25 C, unless otherwise noted. Table 4. Parameter Symbol Conditions Min Typ Max Unit OUTPUT VOLTAGE VO A and C grades V INITIAL ACCURACY VOERR A and C grades 5 mv.2 % OUTPUT VOLTAGE VO B grades V INITIAL ACCURACY VOERR B grades 2.5 mv. % TEMPERATURE COEFFICIENT TCVO A grade, 8-lead SOIC, 4 C < TA < +25 C 3 ppm/ C A grade, 5-lead TSOT, 4 C < TA < +25 C 25 ppm/ C A grade, 5-lead SC7, 4 C < TA < +25 C 25 ppm/ C A grade, 5-lead SC7, 55 C < TA < +25 C 3 ppm/ C B grade, 8-lead SOIC, 4 C < TA < +25 C 3 ppm/ C B grade, 5-lead TSOT, 4 C < TA < +25 C 9 ppm/ C B grade, 5-lead SC7, 4 C < TA < +25 C 9 ppm/ C C grade, 8-lead SOIC, 4 C < TA < +25 C 4 ppm/ C SUPPLY VOLTAGE HEADROOM VIN VO 2 V LINE REGULATION VO/ VIN VIN = 4.5 V to 4. V, 4 C < TA < +25 C 7 3 ppm/v VIN = 4.5 V to 4. V, 55 C < TA < +25 C 7 4 ppm/v LOAD REGULATION VO/ ILOAD ILOAD = ma to ma, 4 C < TA < +25 C, 25 7 ppm/ma VIN = 7. V ILOAD = ma to ma, 55 C < TA < +25 C, 45 8 ppm/ma VIN = 7. V QUIESCENT CURRENT IIN No load, 4 C < TA < +25 C.65 ma VOLTAGE NOISE en p-p. Hz to. Hz 6 μv p-p VOLTAGE NOISE DENSITY en khz 23 nv/ Hz TURN-ON SETTLING TIME tr 4 μs LONG-TERM STABILITY VO hours 5 ppm OUTPUT VOLTAGE HYSTERESIS VO_HYS 7 ppm 55 C < TA < +25 C 8 ppm RIPPLE REJECTION RATIO RRR fin = khz 75 db SHORT CIRCUIT TO GND ISC 3 ma VOLTAGE OUTPUT AT TEMP PIN VTEMP 55 mv TEMPERATURE SENSITIVITY TCVTEMP.96 mv/ C The long-term stability specification is noncumulative. The drift in subsequent hour periods is significantly lower than in the first hour period. Rev. J Page 5 of 24

6 ADR6 ELECTRICAL CHARACTERISTICS VIN = 5. V to 4. V, TA = 25 C, unless otherwise noted. Table 5. Parameter Symbol Conditions Min Typ Max Unit OUTPUT VOLTAGE VO A and C grades V INITIAL ACCURACY VOERR A and C grades 6 mv.2 % OUTPUT VOLTAGE VO B grade V INITIAL ACCURACY VOERR B grade 3 mv. % TEMPERATURE COEFFICIENT TCVO A grade, 8-lead SOIC, 4 C < TA < +25 C 3 ppm/ C A grade, 5-lead TSOT, 4 C < TA < +25 C 25 ppm/ C A grade, 5-lead SC7, 4 C < TA < +25 C 25 ppm/ C B grade, 8-lead SOIC, 4 C < TA < +25 C 3 ppm/ C B grade, 5-lead TSOT, 4 C < TA < +25 C 9 ppm/ C B grade, 5-lead SC7, 4 C < TA < +25 C 9 ppm/ C C grade, 8-lead SOIC, 4 C < TA < +25 C 4 ppm/ C SUPPLY VOLTAGE HEADROOM VIN VO 2 V LINE REGULATION VO/ VIN VIN = 5. V to 4. V, 4 C < TA < +25 C 7 3 ppm/v LOAD REGULATION VO/ ILOAD ILOAD = ma to ma, 4 C < TA < +25 C, 4 7 ppm/ma VIN = 7. V QUIESCENT CURRENT IIN No load, 4 C < TA < +25 C.65 ma VOLTAGE NOISE en p-p. Hz to. Hz μv p-p VOLTAGE NOISE DENSITY en khz 5 nv/ Hz TURN-ON SETTLING TIME tr 4 μs LONG-TERM STABILITY VO hours 5 ppm OUTPUT VOLTAGE HYSTERESIS VO_HYS 7 ppm RIPPLE REJECTION RATIO RRR fin = khz 75 db SHORT CIRCUIT TO GND ISC 3 ma VOLTAGE OUTPUT AT TEMP PIN VTEMP 55 mv TEMPERATURE SENSITIVITY TCVTEMP.96 mv/ C The long-term stability specification is noncumulative. The drift in subsequent hour periods is significantly lower than in the first hour period. Rev. J Page 6 of 24

7 DIE ELECTRICAL CHARACTERISTICS VIN = up to 4. V, TA = 25 C, unless otherwise noted. Table 6. Parameter Symbol Conditions Min Typ Max Unit OUTPUT VOLTAGE ADRNBC VO 25 C V ADR2NBC VO 25 C V ADR3BNC VO 25 C V TEMPERATURE COEFFICIENT TCVO 4 C < TA < +25 C ppm/ C LINE REGULATION ADRNBC VO/ VIN VIN = 5. V to 4. V 7 ppm/v ADR2NBC VO/ VIN VIN = 7. V to 4. V 7 ppm/v ADR3BNC VO/ VIN VIN = 4.5 V to 4. V 7 ppm/v LOAD REGULATION VO/ ILOAD ILOAD = to ma 4 ppm/ma QUIESCENT CURRENT IIN No load.65 ma VOLTAGE NOISE en p-p. Hz to. Hz 25 μv p-p TEMP V IN GND TRIM DIE SIZE:.83mm.mm V OUT (SENSE) V OUT (FORCE) Figure 3. Die Layout Rev. J Page 7 of 24

8 ABSOLUTE MAXIMUM RATINGS Ratings at 25 C, unless otherwise noted. Table 7. Parameter Rating Supply Voltage 4. V Output Short-Circuit Duration to GND Indefinite Storage Temperature Range 65 C to +5 C Operating Temperature Range 4 C to +25 C Junction Temperature Range 65 C to +5 C Lead Temperature Range (Soldering, 6 sec) 3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 8. Thermal Resistance Package Type θja θjc Unit 5-Lead SC7 (KS-5) C/W 5-Lead TSOT (UJ-5) C/W 8-Lead SOIC (R-8) 3 43 C/W ESD CAUTION Rev. J Page 8 of 24

9 TERMINOLOGY Temperature Coefficient The change of output voltage with respect to operating temperature changes normalized by the output voltage at 25 C. This parameter is expressed in ppm/ C and can be determined by the following equation: VO [ ] ( TO ) VO ( T ) 6 TCVO ppm/ C = V ( 25 C) where: VO(25 C) = VO at 25 C. VO(T) = VO at Temperature. VO(T2) = VO at Temperature 2. O Line Regulation The change in output voltage due to a specified change in input voltage. This parameter accounts for the effects of self-heating. Line regulation is expressed in either percent per volt, parts-per-million per volt, or microvolts per volt change in input voltage. Load Regulation The change in output voltage due to a specified change in load current. This parameter accounts for the effects of self-heating. Load regulation is expressed in either microvolts per milliampere, parts-per-million per milliampere, or ohms of dc output resistance. Long-Term Stability Typical shift of output voltage at 25 C on a sample of parts subjected to a test of hours at 25 C. Δ V O = V ( t ) V ( t ) O VO ( t ) VO ( t) ΔV O[ ppm] = V ( t ) O O where: VO(t) = VO at 25 C at Time. VO(t) = VO at 25 C after hours of operation at 25 C. 6 Thermal Hysteresis Defined as the change of output voltage after the device is cycled through temperatures from +25 C to 4 C to +25 C and back to +25 C. This is a typical value from a sample of parts put through such a cycle. VO_HYS = VO(25 C) VO_TC VO ( 25 C) VO _ TC 6 VO _ HYS[ ppm] = V ( 25 C) O where: VO(25 C) = VO at 25 C. VO_TC = VO at 25 C after temperature cycle at +25 C to 4 C to +25 C and back to +25 C. Input Capacitor Input capacitors are not required on the ADR/ADR2/ ADR3/ADR6. There is no limit for the value of the capacitor used on the input, but a μf to μf capacitor on the input improves transient response in applications where the supply suddenly changes. An additional. μf in parallel also helps to reduce noise from the supply. Output Capacitor The ADR/ADR2/ADR3/ADR6 do not require output capacitors for stability under any load condition. An output capacitor, typically. μf, filters out any low-level noise voltage and does not affect the operation of the part. Alternatively, the load transient response can be improved with an additional μf to μf output capacitor in parallel. A capacitor here acts as a source of stored energy for a sudden increase in load current. The only parameter that degrades by adding an output capacitor is the turn-on time, and it depends on the size of the capacitor chosen. The majority of the shift is seen in the first 2 hours, and as time goes by, the drift decreases significantly. This drift is much smaller for the subsequent hours of time points than for the first. Rev. J Page 9 of 24

10 TYPICAL PERFORMANCE CHARACTERISTICS V OUT (V) V OUT (V) Figure 4. ADR Typical Output Voltage vs. Temperature Figure 7. ADR6 Typical Output Voltage vs. Temperature V OUT (V) SUPPLY CURRENT (ma) C +25 C 4 C Figure 5. ADR2 Typical Output Voltage vs. Temperature INPUT VOLTAGE (V) Figure 8. ADR Supply Current vs. Input Voltage V OUT (V) SUPPLY CURRENT (ma) C +25 C 4 C INPUT VOLTAGE (V) Figure 6. ADR3 Typical Output Voltage vs. Temperature Figure 9. ADR2 Supply Current vs. Input Voltage Rev. J Page of 24

11 I L = ma TO 5mA SUPPLY CURRENT (ma) C +25 C 4 C LOAD REGULATION (ppm/ma) 3 2 V IN = 8V V IN = 4V INPUT VOLTAGE (V) Figure. ADR3 Supply Current vs. Input Voltage Figure 3. ADR2 Load Regulation vs. Temperature.8 6 SUPPLY CURRENT (ma) C +25 C 4 C LOAD REGULATION (ppm/ma) I L = ma TO ma V IN = 4V V IN = 7V INPUT VOLTAGE (V) Figure. ADR6 Supply Current vs. Input Voltage Figure 4. ADR3 Load Regulation vs. Temperature LOAD REGULATION (ppm/ma) V IN = 4V V IN = 4V I L = ma TO ma LOAD REGULATION (ppm/ma) V IN = 4V V IN = 7V I L = ma TO ma Figure 2. ADR Load Regulation vs. Temperature Figure 5. ADR6 Load Regulation vs. Temperature Rev. J Page of 24

12 2 V IN = 4V TO 4V V IN = 6V TO 4V 8 LINE REGULATION (ppm/v) LINE REGULATION (ppm/v) Figure 6. ADR Line Regulation vs. Temperature Figure 9. ADR6 Line Regulation vs. Temperature 8 V IN = 8V TO 4V 5 LINE REGULATION (ppm/v) 4 4 DIFFERENTIAL VOLTAGE (V) C +25 C +25 C LOAD CURRENT (ma) Figure 7. ADR2 Line Regulation vs. Temperature Figure 2. ADR Minimum Input-Output Voltage Differential vs. Load Current 4 8 V IN = 5V TO 4V LINE REGULATION (ppm/mv) 2 2 DIFFERENTIAL VOLTAGE (V) C +25 C +25 C LOAD CURRENT (ma) Figure 8. ADR3 Line Regulation vs. Temperature Figure 2. ADR2 Minimum Input-Output Voltage Differential vs. Load Current Rev. J Page 2 of 24

13 6 5 DIFFERENTIAL VOLTAGE (V) o C +25 C +25 C μv/div LOAD CURRENT (ma) TIME (s/div) Figure 22. ADR3 Minimum Input-Output Voltage Differential vs. Load Current Figure 25. ADR2 Typical Noise Voltage. Hz to. Hz DIFFERENTIAL VOLTAGE (V) C +25 C +25 C 5μV/DIV LOAD CURRENT (ma) TIME (ms/div) Figure 23. ADR6 Minimum Input-Output Voltage Differential vs. Load Current Figure 26. ADR2 Typical Noise Voltage Hz to KHz.7 T A = 25 C V 8V QUIESCENT CURRENT (ma) V OUT 5V/DIV NO LOAD CAPACITOR NO INPUT CAPACITOR LOAD CURRENT (ma) TIME (2.ms/DIV) Figure 24. ADR Quiescent Current vs. Load Current Figure 27. ADR2 Line Transient Response Rev. J Page 3 of 24

14 NO LOAD CAPACITOR C IN =.μf NO LOAD CAPACITOR V IN 5V/DIV V IN V/DIV LOAD OFF LOAD ON V OUT mv/div V OUT 5V/DIV LOAD = 5mA TIME (.ms/div) TIME (4μs/DIV) Figure 28. ADR2 Load Transient Response Figure 3. ADR2 Turn-On Response C LOAD = nf V IN 5V/DIV LOAD OFF LOAD ON C L =.μf NO INPUT CAPACITOR V IN V/DIV V OUT mv/div V OUT 5V/DIV TIME (.ms/div) LOAD = 5mA TIME (4μs/DIV) Figure 29. ADR2 Load Transient Response Figure 32. ADR2 Turn-Off Response V IN V/DIV V IN V/DIV C IN =.μf NO LOAD CAPACITOR C L =.μf NO INPUT CAPACITOR V OUT 5V/DIV V OUT 5V/DIV TIME (4μs/DIV) TIME (4μs/DIV) Figure 3. ADR2 Turn-Off Response Figure 33. ADR2 Turn-On Response Rev. J Page 4 of 24

15 APPLICATIONS The ADR/ADR2/ADR3/ADR6 are high precision, low drift. V, 5. V, 2.5 V, and 3. V voltage references available in an ultracompact footprint. The 8-lead SOIC versions of the devices are drop-in replacements of the REF/REF2/REF3 sockets with improved cost and performance. These devices are standard band gap references (see Figure 35). The band gap cell contains two NPN transistors (Q8 and Q9) that differ in emitter area by 2. The difference in their VBE produces a proportional-to-absolute temperature current (PTAT) in R4, and, when combined with the VBE of Q9, produces a band gap voltage, VBG, that is almost constant in temperature. With an internal op amp and the feedback network of R5 and R6, VO is set precisely at. V, 5. V, 2.5 V, and 3. V for the ADR, ADR2, ADR6, and ADR3, respectively. Precision laser trimming of the resistors and other proprietary circuit techniques are used to further enhance the initial accuracy, temperature curvature, and drift performance of the ADR/ADR2/ADR3/ADR6. The PTAT voltage is made available at the TEMP pin of the ADR/ADR2/ADR3/ADR6. It has a stable.96 mv/ C temperature coefficient, such that users can estimate the temperature change of the device by knowing the voltage change at the TEMP pin. APPLYING THE ADR/ADR2/ADR3/ADR6 The devices can be used without any external components to achieve the specified performance. Because of the internal op amp amplifying the band gap cell to. V/5. V/2.5 V/3. V, power supply decoupling helps the transient response of the ADR/ADR2/ADR3/ADR6. As a result, a. μf ceramic type decoupling capacitor should be applied as close as possible to the input and output pins of the device. An optional μf to μf bypass capacitor can also be applied at the VIN node to maintain the input under transient disturbance. Output Adjustment The ADR/ADR2/ADR3/ADR6 trim terminal can be used to adjust the output voltage over a nominal voltage. This feature allows a system designer to trim system errors by setting the reference to a voltage other than. V/5. V/2.5 V/3. V. For finer adjustment, add a series resistor of 47 kω. With the configuration shown in Figure 36, the ADR can be adjusted from 9.7 V to.5 V, the ADR2 can be adjusted from 4.95 V to 5.2 V, the ADR6 can be adjusted from 2.8 V to 3.3 V, and the ADR3 can be adjusted from 2.3 V to 2.8 V. Adjustment of the output does not significantly affect the temperature performance of the device, provided the temperature coefficients of the resistors are relatively low. R2 U ADR/ ADR2/ ADR3/ ADR6 V IN V IN V OUT C.μF TEMP TRIM GND D3 R3 Figure 34. Basic Configuration V O C2.μF R R2 R3 R4 Q Q2 Q7 Q8 Q2 Q3 Q3 C Q4 Q5 2X X V BG R2 Q8 TRIM R27 Q9 TEMP R4 Q6 Q7 Q2 R32 R6 R24 R7 R R4 R42 GND V IN D D2 Q4 I Q23 Figure 35. Simplified Schematic Diagram U ADR/ ADR2/ ADR3/ ADR6 V IN V OUT TEMP TRIM GND R 47kΩ Q9 V O pot kω R2 kω Figure 36. Optional Trim Adjustment Temperature Monitoring As described at the end of the Applications section, the ADR/ ADR2/ADR3/ADR6 provide a TEMP output (Pin in Figure and Pin 3 in Figure 2) that varies linearly with temperature. This output can be used to monitor the temperature change in the system. The voltage at VTEMP is approximately 55 mv at 25 C, and the temperature coefficient is approximately.96 mv/ C (see Figure 37). A voltage change of 39.2 mv at the TEMP pin corresponds to a 2 C change in temperature. R Q V IN V O Rev. J Page 5 of 24

16 V IN = 5V SAMPLE SIZE = 5 +5V TO +5V U ADR/ ADR2/ ADR3/ ADR6 V IN V OUT V TEMP (V) ΔV TEMP /ΔT.96mV/ C V REF TEMP TRIM GND +5V U2 V+ OP77 V.45 5V Figure 37. Voltage at TEMP Pin vs. Temperature The TEMP function is provided as a convenience rather than a precise feature. Because the voltage at the TEMP node is acquired from the band gap core, current pulling from this pin has a significant effect on VOUT. Care must be taken to buffer the TEMP output with a suitable low bias current op amp, such as the AD86, AD82, or OP77, all of which result in less than a μv change in ΔVOUT (see Figure 38). Without buffering, even tens of microamps drawn from the TEMP pin can cause VOUT to fall out of specification. V TEMP.9mV/ C 5V V IN V+ OP77 U2 V NEGATIVE REFERENCE U ADR/ ADR2/ ADR3/ ADR6 V IN V OUT TEMP TRIM GND Figure 38. Temperature Monitoring Without using any matching resistors, a negative reference can be configured, as shown in Figure 39. For the ADR, the voltage difference between VOUT and GND is. V. Because VOUT is at virtual ground, U2 closes the loop by forcing the GND pin to be the negative reference node. U2 should be a precision op amp with a low offset voltage characteristic. LOW COST CURRENT SOURCE Unlike most references, the ADR/ADR2/ADR3/ADR6 employ an NPN Darlington in which the quiescent current remains constant with respect to the load current, as shown in Figure 24. As a result, a current source can be configured as shown in Figure 4 where ISET = (VOUT VL)/RSET. IL is simply the sum of ISET and IQ. Although simple, IQ varies typically from.55 ma to.65 ma, limiting this circuit to general-purpose applications. V O V IN ADR/ V ADR2/ OUT ADR3/ ADR6 GND Figure 39. Negative Reference I IN I Q.6mA R SET R L V L I SET = (V OUT V L )/R SET I L = I SET + I Q Figure 4. Low Cost Current Source PRECISION CURRENT SOURCE WITH ADJUSTABLE OUTPUT Alternatively, a precision current source can be implemented with the circuit shown in Figure 4. By adding a mechanical or digital potentiometer, this circuit becomes an adjustable current source. If a digital potentiometer is used, the load current is simply the voltage across Terminal B to Terminal W of the digital potentiometer divided by RSET. VREF D I L = () R SET where D is the decimal equivalent of the digital potentiometer input code. +2V U ADR/ ADR2/ ADR3/ ADR6 V IN V OUT TEMP TRIM GND V TO (5V + V L ) B AD52 kω A +2V U2 V+ OP77 5V TO V L V 2V W R SET R L kω kω Figure 4. Programmable ma to 5 ma Current Source V L I L Rev. J Page 6 of 24

17 To optimize the resolution of this circuit, dual-supply op amps should be used because the ground potential of ADR2 can swing from 5. V at zero scale to VL at full scale of the potentiometer setting. PROGRAMMABLE 4 TO 2 ma CURRENT TRANSMITTER Because of their precision, adequate current handling, and small footprint, the devices are suitable as the reference sources for many high performance converter circuits. One of these applications is the multichannel 6-bit, 4 to 2 ma current transmitter in the industrial control market (see Figure 42). This circuit employs a Howland current pump at the output to yield better efficiency, a lower component count, and a higher voltage compliance than the conventional design with op amps and MOSFETs. In this circuit, if the resistors are matched such that R = R, R2 = R2, R3 = R3, the load current is (R2 + R3) R VREF D IL = N (2) R3 2 where D is similarly the decimal equivalent of the DAC input code and N is the number of bits of the DAC. According to Equation 2, R3 can be used to set the sensitivity. R3 can be made as small as necessary to achieve the current needed within U4 output current driving capability. Alternatively, other resistors can be kept high to conserve power. In this circuit, the AD852 is capable of delivering 2 ma of current, and the voltage compliance approaches 5. V. U 5V VIN V OUT TEMP TRIM GND 5V U2 V DD RF IO V V REF AD5544 IO GND DIGITAL INPUT CODE 2% % FULL SCALE U = ADR/ADR2/ADR3/ADR6, REF U2 = AD5543/AD5544/AD5554 U3, U4 = AD852 V TO V +5V R R2 5kΩ 5kΩ U3 V X VP 5V C AD852 R' 5kΩ VN pf U4 R2' 5kΩ LOAD 5Ω 4 2mA Figure 42. Programmable 4 to 2 ma Transmitter R3 5Ω V O R3' 5Ω The Howland current pump yields a potentially infinite output impedance, that is highly desirable, but resistance matching is critical in this application. The output impedance can be determined using Equation 3. As shown by this equation, if the resistors are perfectly matched, ZO is infinite. Alternatively, if they are not matched, ZO is either positive or negative. If the latter is true, oscillation can occur. For this reason, connect V L Capacitor C in the range of pf to pf between VP and the output terminal of U4 to filter any oscillation. Vt R ZO = = (3) It R R2 RR2 In this circuit, an ADR provides the stable. V reference for the AD5544 quad 6-bit DAC. The resolution of the adjustable current is.3 μa/step; the total worst-case INL error is merely 4 LSBs. Such error is equivalent to.2 μa or a.6% system error, which is well below most systems requirements. The result is shown in Figure 43 with measurement taken at 25 C and 7 C; total system error of 4 LSBs at both 25 C and 7 C. INL (LSB) R L = 5Ω I L = ma TO 2mA 7 C 25 C CODE (Decimal) Figure 43. Result of Programmable 4 to 2 ma Current Transmitter PRECISION BOOSTED OUTPUT REGULATOR A precision voltage output with boosted current capability can be realized with the circuit shown in Figure 44. In this circuit, U2 forces VO to be equal to VREF by regulating the turn-on of N, thereby making the load current furnished by VIN. In this configuration, a 5 ma load is achievable at VIN of 5. V. Moderate heat is generated on the MOSFET, and higher current can be achieved with a replacement of a larger device. In addition, for a heavy capacitive load with a fast edging input signal, a buffer should be added at the output to enhance the transient response. V IN U ADR/ ADR2/ ADR3/ ADR6 V IN V OUT TEMP TRIM GND 2N72 5V V+ OP77 V U2 N R L 2Ω Figure 44. Precision Boosted Output Regulator C L μf V O Rev. J Page 7 of 24

18 OUTLINE DIMENSIONS PIN.65 BSC MAX.3.5. COPLANARITY SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-23-AA Figure Lead Thin Shrink Small Outline Transistor Package [SC7] (KS-5) Dimensions shown in millimeters 2.9 BSC BSC 2.8 BSC 2 3 * PIN.9 BSC.95 BSC *. MAX. MAX.5 SEATING.3 PLANE *COMPLIANT TO JEDEC STANDARDS MO-93-AB WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure Lead Thin Small Outline Transistor Package [TSOT] (UJ-5) Dimensions shown in millimeters 5. (.968) 4.8 (.89) 4. (.574) 3.8 (.497) (.244) 5.8 (.2284).25 (.98). (.4) COPLANARITY..27 (.5) BSC SEATING PLANE.75 (.688).35 (.532).5 (.2).3 (.22).25 (.98).7 (.67) 8.5 (.96).25 (.99) (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. J Page 8 of 24

19 ORDERING GUIDES ADR Ordering Guide Output Voltage Initial Accuracy VO (V) (mv) (%) Temperature Coefficient (ppm/ C) ADR/ADR2/ADR3/ADR6 Temperature Package Package Ordering Model Range Description Option Quantity ADRAR. 4 C to +25 C 8-Lead SOIC R-8 98 ADRAR-REEL7. 4 C to +25 C 8-Lead SOIC R-8, ADRARZ. 4 C to +25 C 8-Lead SOIC R-8 98 ADRARZ-REEL7. 4 C to +25 C 8-Lead SOIC R-8, ADRBR C to +25 C 8-Lead SOIC R-8 98 ADRBR-REEL C to +25 C 8-Lead SOIC R-8, ADRBRZ C to +25 C 8-Lead SOIC R-8 98 ADRBRZ-REEL C to +25 C 8-Lead SOIC R-8, ADRAUJ-REEL C to +25 C 5-Lead TSOT UJ-5 3, R8A ADRAUJ-R C to +25 C 5-Lead TSOT UJ-5 25 R8A ADRAUJZ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RE ADRBUJ-REEL C to +25 C 5-Lead TSOT UJ-5 3, R8B ADRBUJ-R C to +25 C 5-Lead TSOT UJ-5 25 R8B ADRBUJZ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RF ADRAKS-REEL C to +25 C 5-Lead SC7 KS-5 3, R8A ADRAKS-R C to +25 C 5-Lead SC7 KS-5 25 R8A ADRAKSZ-REEL C to +25 C 5-Lead SC7 KS-5 3, RE ADRBKS-REEL C to +25 C 5-Lead SC7 KS-5 3, R8B ADRBKS-R C to +25 C 5-Lead SC7 KS-5 25 R8B ADRBKSZ-REEL C to +25 C 5-Lead SC7 KS-5 3, RF ADRCRZ. 4 4 C to +25 C 8-Lead SOIC R-8 98 ADRCRZ-REEL. 4 4 C to +25 C 8-Lead SOIC R-8 2,5 ADRNBC 5.5 (typ) Die 36 Z = RoHS Compliant Part. Branding ADR2 Ordering Guide Model Output Voltage Initial Accuracy VO (V) (mv) (%) Temperature Coefficient (ppm/ C) Temperature Range Rev. J Page 9 of 24 Package Description Package Option Ordering Quantity ADR2AR C to +25 C 8-Lead SOIC R-8 98 ADR2AR-REEL C to +25 C 8-Lead SOIC R-8 2,5 ADR2AR-REEL C to +25 C 8-Lead SOIC R-8, ADR2ARZ C to +25 C 8-Lead SOIC R-8 98 ADR2ARZ-REEL C to +25 C 8-Lead SOIC R-8 2,5 ADR2ARZ-REEL C to +25 C 8-Lead SOIC R-8 2,5 ADR2BR C to +25 C 8-Lead SOIC R-8 98 ADR2BR-REEL C to +25 C 8-Lead SOIC R-8, ADR2BRZ C to +25 C 8-Lead SOIC R-8 98 ADR2BRZ-REEL C to +25 C 8-Lead SOIC R-8, ADR2AUJ-REEL C to +25 C 5-Lead TSOT UJ-5 3, R9A ADR2AUJ-R C to +25 C 5-Lead TSOT UJ-5 25 R9A ADR2AUJZ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RG ADR2BUJ-REEL C to +25 C 5-Lead TSOT UJ-5 3, R9B ADR2BUJ-R C to +25 C 5-Lead TSOT UJ-5 25 R9B ADR2BUJZ-R C to +25 C 5-Lead TSOT UJ-5 25 R9B ADR2BUJZ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RH ADR2AKS-REEL C to +25 C 5-Lead SC7 KS-5 3, R9A ADR2AKS-R C to +25 C 5-Lead SC7 KS-5 25 R9A Branding

20 Output Temperature Voltage Initial Accuracy Coefficient Temperature Package Package Ordering Model VO (V) (mv) (%) (ppm/ C) Range Description Option Quantity Branding ADR2AKSZ-REEL C to +25 C 5-Lead SC7 KS-5 3, RG ADR2BKS-REEL C to +25 C 5-Lead SC7 KS-5 3, R9B ADR2BKS-R C to +25 C 5-Lead SC7 KS-5 25 R9B ADR2BKSZ-REEL C to +25 C 5-Lead SC7 KS-5 3, RH ADR2CRZ C to +25 C 8-Lead SOIC R-8 98 ADR2CRZ-REEL C to +25 C 8-Lead SOIC R-8 2,5 ADR2NBC (typ) Die 36 Z = RoHS Compliant Part. ADR3 Ordering Guide Model Output Voltage Initial Accuracy VO (V) (mv) (%) Temperature Coefficient (ppm/ C) Temperature Range Package Description Package Option Ordering Quantity ADR3AR C to +25 C 8-Lead SOIC R-8 98 ADR3AR-REEL C to +25 C 8-Lead SOIC R-8, ADR3ARZ C to +25 C 8-Lead SOIC R-8 98 ADR3ARZ-REEL C to +25 C 8-Lead SOIC R-8, ADR3BR C to +25 C 8-Lead SOIC R-8 98 ADR3BR-REEL C to +25 C 8-Lead SOIC R-8, ADR3BRZ C to +25 C 8-Lead SOIC R-8 98 ADR3BRZ-REEL C to +25 C 8-Lead SOIC R-8, ADR3AUJ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RFA ADR3AUJ-R C to +25 C 5-Lead TSOT UJ-5 25 RFA ADR3AUJZ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RJ ADR3BUJ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RFB ADR3BUJ-R C to +25 C 5-Lead TSOT UJ-5 25 RFB ADR3BUJZ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RK ADR3AKS-REEL C to +25 C 5-Lead SC7 KS-5 3, RFA ADR3AKS-R C to +25 C 5-Lead SC7 KS-5 25 RFA ADR3AKSZ-REEL C to +25 C 5-Lead SC7 KS-5 3, RJ ADR3BKS-REEL C to +25 C 5-Lead SC7 KS-5 3, RFB ADR3BKS-R C to +25 C 5-Lead SC7 KS-5 25 RFB ADR3BKSZ-REEL C to +25 C 5-Lead SC7 KS-5 3, RK ADR3CRZ C to +25 C 8-Lead SOIC R-8 98 ADR3CRZ-REEL C to +25 C 8-Lead SOIC R-8 2,5 ADR3NBC (typ) Die 36 Z = RoHS Compliant Part. Branding Rev. J Page 2 of 24

21 ADR6 Ordering Guide Output Temperature Voltage Initial Accuracy Coefficient Temperature Package Package Ordering Model VO (V) (mv) (%) (ppm/ C) Range Description Option Quantity Branding ADR6AR C to +25 C 8-Lead SOIC R-8 98 ADR6AR-REEL C to +25 C 8-Lead SOIC R-8, ADR6ARZ C to +25 C 8-Lead SOIC R-8 98 ADR6ARZ-REEL C to +25 C 8-Lead SOIC R-8, ADR6BR C to +25 C 8-Lead SOIC R-8 98 ADR6BR-REEL C to +25 C 8-Lead SOIC R-8, ADR6BRZ C to +25 C 8-Lead SOIC R-8 98 ADR3BRZ-REEL C to +25 C 8-Lead SOIC R-8, ADR6AUJ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RWA ADR6AUJ-R C to +25 C 5-Lead TSOT UJ-5 25 RWA ADR6AUJZ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RL ADR6BUJ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RWB ADR6BUJ-R C to +25 C 5-Lead TSOT UJ-5 25 RWB ADR6BUJZ-REEL C to +25 C 5-Lead TSOT UJ-5 3, RM ADR6AKS-REEL C to +25 C 5-Lead SC7 KS-5 3, RWA ADR6AKS-R C to +25 C 5-Lead SC7 KS-5 25 RWA ADR6AKSZ-REEL C to +25 C 5-Lead SC7 KS-5 3, RL ADR6BKS-REEL C to +25 C 5-Lead SC7 KS-5 3, RWB ADR6BKS-R C to +25 C 5-Lead SC7 KS-5 25 RWB ADR6BKSZ-REEL C to +25 C 5-Lead SC7 KS-5 3, RM ADR6CRZ C to +25 C 8-Lead SOIC R-8 98 ADR6CRZ-REEL C to +25 C 8-Lead SOIC R-8 2,5 Z = RoHS Compliant Part. Rev. J Page 2 of 24

22 NOTES Rev. J Page 22 of 24

23 NOTES Rev. J Page 23 of 24

24 NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C /7(J) Rev. J Page 24 of 24