SP3222EB/3232EB. True +3.0V to +5.5V RS-232 Transceivers. Now Available in Lead Free Packaging

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1 SP3B/33B Tru 3.0V to 5.5V RS-3 Transcivrs FTURS Mts tru I/TI-3-F Standards from a 3.0V to 5.5V powr supply 50kps Transmission Rat Undr oad 1µ ow-powr Shutdown with Rcivrs ctiv (SP3B) Intropral with RS-3 down to.7v powr sourc nhancd SD Spcifications: ±15kV Human Body Modl ±15kV IC ir Discharg ±8kV IC Contact Discharg C1 V C1- C C- V- TOUT RIN SP33B VCC GND T1OUT R1IN R1OUT T1IN TIN ROUT Now vailal in ad Fr Packaging DSCRIPTION Th SP3B/33B sris is an RS-3 transcivr solution intndd for portal or hand-hld applications such as notook or palmtop computrs. Th SP3B/33B sris has a high-fficincy, charg-pump powr supply that rquirs only capacitors in 3.3V opration. This charg pump allows th SP3B/33B sris to dlivr tru RS- 3 prformanc from a singl powr supply ranging from 3.0V to 5.5V. Th SP3B/ 33B ar -drivr/-rcivr dvics. This sris is idal for portal or hand-hld applications such as notook or palmtop computrs. Th SD tolranc of th SP3B/ 33B dvics ar ovr ±15kV for oth Human Body Modl and IC ir discharg tst mthods. Th SP3B dvic has a low-powr shutdown mod whr th dvics' drivr outputs and charg pumps ar disald. During shutdown, th supply currnt falls to lss than 1µ. SCTION TB MOD Powr Supplis RS-3 Drivrs RS-3 Rcivrs xtrnal Componnts Shutdown TT 3-Stat No. of Pins SP3B SP33B 3.0V to 5.5V 4 Ys 3.0V to 5.5V 4 No Ys 18, 0 No 16 Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 1

2 BSOUT MXIMUM RTINGS Ths ar strss ratings only and functional opration of th dvic at ths ratings or any othr aov thos indicatd in th opration sctions of th spcifications low is not implid. xposur to asolut maximum rating conditions for xtndd priods of tim may affct rliaility and caus prmannt damag to th dvic. V CC V to 6.0V V (NOT 1) V to 7.0V V- (NOT 1) V to -7.0V V V- (NOT 1)... 13V I CC (DC V CC or GND currnt)... ±100m Input Voltags TxIN, N V to 6.0V RxIN... ±5V Output Voltags TxOUT... ±13.V RxOUT V to (V CC 0.3V) Short-Circuit Duration TxOUT... Continuous Storag Tmpratur C to 150 C Powr Dissipation Pr Packag 0-pin SSOP (drat 9.5mW/ o C aov 70 o C) mW 18-pin PDIP (drat 15.mW/ o C aov 70 o C)... 10mW 18-pin SOIC (drat 15.7mW/ o C aov 70 o C) mW 0-pin TSSOP (drat 11.1mW/ o C aov 70 o C) mW 16-pin SSOP (drat 9.69mW/ o C aov 70 o C) mW 16-pin PDIP (drat 14.3mW/ o C aov 70 o C) mW 16-pin Wid SOIC (drat 11.mW/ o C aov 70 o C) mW 16-pin TSSOP (drat 10.5mW/ o C aov 70 o C) mW 16-pin nsoic (drat 13.57mW/ C aov 70 C) mW NOT 1: V and V- can hav maximum magnituds of 7V, ut thir asolut diffrnc cannot xcd 13V. NOT : Drivr Input hystrsis is typically 50mV. Unlss othrwis notd, th following spcifications apply for V CC = 3.0V to 5.5V with T MB = T MIN to T MX, C 1 to C 4 = PRMTR MIN. TYP. MX. UNITS CONDITIONS DC CHRCTRISTICS Supply Currnt m no load, T MB = 5 C, V CC = 3.3V, TxIN = V CC or GND Shutdown Supply Currnt µ SHDN = GND, T MB = 5 C, V CC = 3.3V, TxIN = V CC or GND OGIC INPUTS ND RCIVR OUTPUTS Input ogic Thrshold OW GND 0.8 V TxIN, N, SHDN, Not Input ogic Thrshold HIGH.0 V CC V V CC = 3.3V, Not.4 V V CC = 5.0V, Not Input akag Currnt ±0.01 ±1.0 µ TxIN, N, SHDN, T MB = 5 C, V IN = 0V to V CC Output akag Currnt ±0.05 ±10 µ rcivrs disald, V OUT = 0V to V CC Output Voltag OW 0.4 V I OUT = 1.6m Output Voltag HIGH V CC -0.6 V CC -0.1 V I OUT = -1.0m DRIVR OUTPUTS Output Voltag Swing ±5.0 ±5.4 V 3k load to ground at all drivr outputs, T MB = 5 C Output Rsistanc 300 V CC = V = V- = 0V, T OUT = V Output Short-Circuit Currnt ±35 ±60 m V OUT = 0V CTRIC CHRCTRISTICS Output akag Currnt ±5 µ V OUT = ±1V,V CC = 0V, or 3.0V to 5.5V, drivrs disald Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation

3 CTRIC CHRCTRISTICS Unlss othrwis notd, th following spcifications apply for V CC = 3.0V to 5.5V with T MB = T MIN to T MX, C 1 to C 4 =. Typical Valus apply at V CC = 3.3V or 5.5V and T MB = 5 o C. P RMTR M IN. T YP. MX. RCIVR INPUTS UNITS CONDITIONS Input Voltag Rang -5 5 V Input Thrshold OW V V CC V CC =3.3V =5.0V Input Thrshold HIGH V V CC V CC =3.3V =5.0V Input Hystrsis 0. 3 V Input Rsistanc k TIMING CHRCTRISTICS Maximum Data Rat 50 kps R = 3k, C =1000pF, on drivr switching Rcivr Propagation Dlay µs t, RxIN to RxOUT, C =150pF PH, RxIN to RxOUT, C =150pF tph Rcivr Output nal Tim 00 ns Rcivr Output Disal Tim 00 ns Drivr Skw 100 ns Rcivr Skw 50 ns Transition-Rgion Slw Rat 30 V / µs tp H tp H - tph - t H P, T = 5 o C MB o V CC = 3.3V, R = 3K, T = 5 C, MB masurmnts takn from -3.0V to 3.0V or 3.0V to -3.0V Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 3

4 TYPIC PRFORMNC CHRCTRISTICS Unlss othrwis notd, th following prformanc charactristics apply for V CC = 3.3V, 50kps data rats, all drivrs loadd with 3k, charg pump capacitors, and T MB = 5 C Transmittr Output Voltag (V) TxOUT TxOUT - T1 at 50Kps T at 15.6Kps ll TX loadd 3K // Coad Slw rat (V/µs) T1 at 50Kps T at 15.6Kps ll TX loadd 3K // Coad Slw Slw oad Capacitanc (pf) oad Capacitanc (pf) Figur 1. Transmittr Output Voltag vs oad Capacitanc. Figur. Slw Rat vs oad Capacitanc. Supply Currnt (m) 35 T1 at Full Data Rat T at 1/16 Data Rat ll TX loadd 3K // Coad 50Kps 15Kps 0Kps oad Capacitanc (pf) Supply Currnt (m) Transmittr at 50Kps 1 Transmittr at 15.6Kps ll transmittrs loadd with 3K // 1000pf Supply Voltag (V) Figur 3. Supply Currnt vs oad Capacitanc whn Transmitting Data. Figur 4. Supply Currnt vs Supply Voltag. Transmittr Output Voltag (V) TxOUT T1 at 50Kps T at 15.6Kps ll TX loadd 3K // 1000 pf TxOUT Supply Voltag (V) Figur 5. Transmittr Output Voltag vs Supply Voltag. Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation

5 PIN DSCRIPTION PIN NUMBR NM FUNCTION SP3B DIP/SO SSOP TSSOP SP33B N Rcivr nal. pply logic OW for normal opration. pply logic HIGH to disal th rcivr outputs (high-z stat) C 1 Positiv trminal of th voltag doulr charg-pump capacitor. 1 V 5.5V gnratd y th charg pump. 3 3 C 1- Ngativ trminal of th voltag doulr charg-pump capacitor C Positiv trminal of th invrting charg-pump capacitor C - Ngativ trminal of th invrting charg-pump capacitor V V gnratd y th charg pump T 1OUT RS-3 drivr output T OUT RS-3 drivr output R 1IN RS-3 rcivr input R IN RS-3 rcivr input R 1OUT TT/CMOS rcivr output R OUT TT/CMOS rcivr output T 1IN TT/CMOS drivr input T IN TT/CMOS drivr input G ND Ground V CC 3.0V to 5.5V supply voltag SHDN Shutdown Control Input. Driv HIGH for normal dvic opration. Driv OW to shutdown th drivrs (high-z output) and th on- oard powr supply N.C. No Connct. - 11, 14 - Tal 1. Dvic Pin Dscription Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 5

6 SP3B SHDN VCC GND T1OUT R1IN R1OUT N.C. T1IN TIN N.C. N C1 V C1- C C- V- TOUT RIN ROUT N C1 V C1- C C- V- TOUT RIN SP3B SHDN VCC GND T1OUT R1IN R1OUT T1IN TIN ROUT DIP/SO SSOP/TSSOP Figur 6. Pinout Configurations for th SP3B C1 V C1- C C- V- TOUT RIN SP33B VCC GND T1OUT R1IN R1OUT T1IN TIN ROUT Figur 7. Pinout Configuration for th SP33B Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation

7 VCC VCC C5 C1 C 19 VCC SP3B SSOP TSSOP V V- 3 7 *C3 C4 C5 C1 C C1 4 C1-5 C 6 C- C1 4 C1-5 C 6 C- 17 VCC SP3B DIP/SO V V- 3 7 *C3 C4 OGIC INPUTS 13 T1IN 1 TIN T1OUT TOUT 17 8 RS-3 OUTPUTS OGIC INPUTS 1 T1IN 11 TIN T1OUT TOUT 15 8 RS-3 OUTPUTS OGIC OUTPUTS 15 R1OUT 10 ROUT 1 GND 18 5k 5k R1IN RIN 16 N 0 SHDN 9 RS-3 INPUTS *can rturnd to ithr VCC or GND OGIC OUTPUTS 13 R1OUT 10 ROUT 1 GND 16 5k 5k R1IN RIN 14 N 18 SHDN 9 RS-3 INPUTS *can rturnd to ithr VCC or GND Figur 8. SP3B Typical Oprating Circuits VCC C5 C1 C 1 C1 3 C1-4 C 5 C- 16 VCC SP33B V V- 6 *C3 C4 OGIC INPUTS 11 T1IN 10 TIN T1OUT TOUT 14 7 RS-3 OUTPUTS OGIC OUTPUTS 1 R1OUT R1IN 13 5k 9 ROUT RIN 8 5k RS-3 INPUTS GND 15 *can rturnd to ithr VCC or GND Figur 9. SP33B Typical Oprating Circuit Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation

8 DSCRIPTION Th SP3B/33B transcivrs mt th I/TI-3 and V.8/V.4 communication protocols and can implmntd in attrypowrd, portal, or hand-hld applications such as notook or palmtop computrs. Th SP3B/33B dvics all fatur Sipx's propritary on-oard charg pump circuitry that gnrats x V CC for RS-3 voltag lvls from a singl 3.0V to 5.5V powr supply. This sris is idal for 3.3V-only systms, mixd 3.3V to 5.5V systms, or 5.0V-only systms that rquir tru RS-3 prformanc. Th SP3B/33B sris hav drivrs that oprat at a typical data rat of 50kps fully loadd. Th SP3B and SP33B ar -drivr/- rcivr dvics idal for portal or hand-hld applications. Th SP3B faturs a 1µ shutdown mod that rducs powr consumption and xtnds attry lif in portal systms. Its rcivrs rmain activ in shutdown mod, allowing xtrnal dvics such as modms to monitord using only 1µ supply currnt. THORY OF OPRTION Th SP3B/33B sris ar mad up of thr asic circuit locks: 1. Drivrs,. Rcivrs, and 3. th Sipx propritary charg pump. Drivrs Th drivrs ar invrting lvl transmittrs that convrt TT or CMOS logic lvls to ±5.0V I/TI-3 lvls invrtd rlativ to th input logic lvls. Typically, th RS-3 output voltag swing is ±5.5V with no load and at last ±5V minimum fully loadd. Th drivr outputs ar protctd against infinit short-circuits to ground without dgradation in rliaility. Drivr outputs will mt I/TI-56 lvls of ±3.7V with supply voltags as low as.7v. Th drivrs can guarant a data rat of 50kps fully loadd with 3K in paralll with 1000pF, nsuring compatiility with PC-to-PC communication softwar. Th slw rat of th drivr output is intrnally limitd to a maximum of 30V/µs in ordr to mt th I standards (I RS-3D.1.7, Paragraph 5). Th transition of th loadd output from HIGH to OW also mts th monotonicity rquirmnts of th standard. Figur 10 shows a loopack tst circuit usd to th RS-3 drivrs. Figur 11 shows th tst rsults of th loopack circuit with all drivrs activ at 10kps with RS-3 loads in paralll with 1000pF capacitors. Figur 1 shows th tst rsults whr on drivr was activ at 50kps and all drivrs loadd with an RS-3 rcivr in paralll with a 1000pF capacitor. solid RS-3 data transmission rat of 50kps provids compatiility with many dsigns in prsonal computr priphrals and N applications. Th SP3B drivr's output stags ar turnd off (tri-stat) whn th dvic is in shutdown mod. Whn th powr is off, th SP3B dvic prmits th outputs to drivn up to ±1V. Th drivr's inputs do not hav pull-up rsistors. Dsignrs should connct unusd inputs to V CC or GND. In th shutdown mod, th supply currnt falls to lss than 1µ, whr SHDN = OW. Whn th SP3B dvic is shut down, th dvic's drivr outputs ar disald (tri-statd) and th charg pumps ar turnd off with V pulld down to V CC and V- pulld to GND. Th tim rquird to xit shutdown is typically 100µs. Connct SHDN to V CC if th shutdown mod is not usd. Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation

9 VCC C5 VCC C1 C C1 C1- C C- SP3B SP33B V V- C3 C4 OGIC INPUTS TxIN TxOUT OGIC OUTPUTS RxOUT 5k RxIN N* *SHDN VCC GND 1000pF * SP3B only Figur 10. SP3B/33B Drivr oopack Tst Circuit Figur 11. Drivr oopack Tst Rsults at 10kps Figur 1. Drivr oopack Tst Rsults at 50 kps Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation

10 Rcivrs Th rcivrs convrt I/TI-3 lvls to TT or CMOS logic output lvls. Th SP3B rcivrs hav an invrting tri-stat output. Ths rcivr outputs (RxOUT) ar tristatd whn th nal control N = HIGH. In th shutdown mod, th rcivrs can activ or inactiv. N has no ffct on TxOUT. Th truth tal logic of th SP3B drivr and rcivr outputs can found in Tal. Sinc rcivr input is usually from a transmission lin whr long cal lngths and systm intrfrnc can dgrad th signal, th inputs hav a typical hystrsis margin of 300mV. This nsurs that th rcivr is virtually immun to noisy transmission lins. Should an input lft unconnctd, a 5k pulldown rsistor to ground will commit th output of th rcivr to a HIGH stat. Charg Pump Th charg pump is a Sipxpatntd dsign (5,306,954) and uss a uniqu approach compard to oldr lssfficint dsigns. Th charg pump still rquirs four xtrnal capacitors, ut uss a fourphas voltag shifting tchniqu to attain symmtrical 5.5V powr supplis. Th intrnal powr supply consists of a rgulatd dual charg pump that provids output voltags 5.5V rgardlss of th input voltag (V CC ) ovr th 3.0V to 5.5V rang. In most circumstancs, dcoupling th powr supply can achivd adquatly using a ypass capacitor at C5 (rfr to Figurs 8 and 9). SHDN N TxOUT 0 0 Tri-stat 0 1 Tri-stat 1 0 ctiv 1 1 ctiv RxOUT ctiv Tri-stat ctiv Tri-stat Tal. SP3B Truth Tal ogic for Shutdown and nal Control In applications that ar snsitiv to powr-supply nois, dcoupl V CC to ground with a capacitor of th sam valu as charg-pump capacitor C1. Physically connct ypass capacitors as clos to th IC as possil. Th charg pumps oprat in a discontinuous mod using an intrnal oscillator. If th output voltags ar lss than a magnitud of 5.5V, th charg pumps ar nald. If th output voltag xcd a magnitud of 5.5V, th charg pumps ar disald. This oscillator controls th four phass of th voltag shifting. dscription of ach phas follows. Phas 1 V SS charg storag During this phas of th clock cycl, th positiv sid of capacitors C 1 and C ar initially chargd to V CC. C l is thn switchd to GND and th charg in C 1 is transfrrd to C. Sinc C is connctd to V CC, th voltag potntial across capacitor C is now tims V CC. Phas V SS transfr Phas two of th clock conncts th ngativ trminal of C to th V SS storag capacitor and th positiv trminal of C to GND. This transfrs a ngativ gnratd voltag to C 3. This gnratd voltag is rgulatd to a minimum voltag of -5.5V. Simultanous with th transfr of th voltag to C 3, th positiv sid of capacitor C 1 is switchd to V CC and th ngativ sid is connctd to GND. Phas 3 V DD charg storag Th third phas of th clock is idntical to th first phas th charg transfrrd in C 1 producs V CC in th ngativ trminal of C 1, which is applid to th ngativ sid of capacitor C. Sinc C is at V CC, th voltag potntial across C is tims V CC. Phas 4 V DD transfr Th fourth phas of th clock conncts th ngativ trminal of C to GND, and transfrs this positiv gnratd voltag across C to C 4, th V DD storag capacitor. Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 10

11 This voltag is rgulatd to 5.5V. t this voltag, th intrnal oscillator is disald. Simultanous with th transfr of th voltag to C 4, th positiv sid of capacitor C 1 is switchd to V CC and th ngativ sid is connctd to GND, allowing th charg pump cycl to gin again. Th charg pump cycl will continu as long as th oprational conditions for th intrnal oscillator ar prsnt. Sinc oth V and V ar sparatly gnratd from V CC ; in a noload condition V and V will symmtrical. Oldr charg pump approachs that gnrat V from V will show a dcras in th magnitud of V compard to V du to th inhrnt infficincis in th dsign. Th clock rat for th charg pump typically oprats at 50kHz. Th xtrnal capacitors can as low as with a 16V rakdown voltag rating. SD Tolranc Th SP3B/33B sris incorporats ruggdizd SD clls on all drivr output and rcivr input pins. Th SD structur is improvd ovr our prvious family for mor ruggd applications and nvironmnts snsitiv to lctrostatic dischargs and associatd transints. Th improvd SD tolranc is at last ±15kV without damag nor latch-up. Thr ar diffrnt mthods of SD tsting applid: a) MI-STD-883, Mthod ) IC ir-discharg c) IC Dirct Contact Th Human Body Modl has n th gnrally accptd SD tsting mthod for smiconductors. This mthod is also spcifid in MI-STD- 883, Mthod for SD tsting. Th prmis of this SD tst is to simulat th human ody s potntial to stor lctrostatic nrgy and discharg it to an intgratd circuit. Th simulation is prformd y using a tst modl as shown in Figur 18. This mthod will tst th IC s capaility to withstand an SD transint during normal handling such as in manufacturing aras whr th ICs tnd to handld frquntly. Th IC , formrly IC801-, is gnrally usd for tsting SD on quipmnt and systms. For systm manufacturrs, thy must guarant a crtain amount of SD protction sinc th systm itslf is xposd to th outsid nvironmnt and human prsnc. Th prmis with IC is that th systm is rquird to withstand an amount of static lctricity whn SD is applid to points and surfacs of th quipmnt that ar accssil to prsonnl during normal usag. Th transcivr IC rcivs most of th SD currnt whn th SD sourc is applid to th connctor pins. Th tst circuit for IC is shown on Figur 19. Thr ar two mthods within IC , th ir Discharg mthod and th Contact Discharg mthod. With th ir Discharg Mthod, an SD voltag is applid to th quipmnt undr tst (UT) through air. This simulats an lctrically chargd prson rady to connct a cal onto th rar of th systm only to find an unplasant zap just for th prson touchs th ack panl. Th high nrgy potntial on th prson dischargs through an arcing path to th rar panl of th systm for h or sh vn touchs th systm. This nrgy, whthr dischargd dirctly or through air, is prdominantly a function of th discharg currnt rathr than th discharg voltag. Varials with an air discharg such as approach spd of th ojct carrying th SD potntial to th systm and humidity will tnd to chang th discharg currnt. For xampl, th ris tim of th discharg currnt varis with th approach spd. Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 11

12 V CC = 5V 5V C 1 C 5V 5V C 4 C 3 V DD Storag Capacitor V SS Storag Capacitor Figur 13. Charg Pump Phas 1 V CC = 5V C 1 C 10V C 4 C 3 V DD Storag Capacitor V SS Storag Capacitor Figur 14. Charg Pump Phas [ T ] 6V a) C GND 1 T GND ) C- -6V T Ch1.00V Ch.00V M 1.00µs Ch1 5.48V Figur 15. Charg Pump Wavforms V CC = 5V 5V C 1 C 5V 5V C 4 C 3 V DD Storag Capacitor V SS Storag Capacitor Figur 16. Charg Pump Phas 3 V CC = 5V 10V C 1 C C 4 C 3 V DD Storag Capacitor V SS Storag Capacitor Figur 17. Charg Pump Phas 4 Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 1

13 R C R S SW1 SW DC Powr Sourc C S Dvic Undr Tst Figur 18. SD Tst Circuit for Human Body Modl Th Contact Discharg Mthod applis th SD currnt dirctly to th UT. This mthod was dvisd to rduc th unprdictaility of th SD arc. Th discharg currnt ris tim is constant sinc th nrgy is dirctly transfrrd without th air-gap arc. In situations such as hand hld systms, th SD charg can dirctly dischargd to th quipmnt from a prson alrady holding th quipmnt. Th currnt is transfrrd on to th kypad or th srial port of th quipmnt dirctly and thn travls through th PCB and finally to th IC. Th circuit modls in Figurs 18 and 19 rprsnt th typical SD tsting circuits usd for all thr mthods. Th C S is initially chargd with th DC powr supply whn th first switch (SW1) is on. Now that th capacitor is chargd, th scond switch (SW) is on whil SW1 switchs off. Th voltag stord in th capacitor is thn applid through R S, th currnt limiting rsistor, onto th dvic undr tst (DUT). In SD tsts, th SW switch is pulsd so that th dvic undr tst rcivs a duration of voltag. R RCC R S Contact-Discharg Modul R V SW1 SW DC Powr Sourc C S Dvic Undr Tst R S and R V add up to 330 for IC Figur 19. SD Tst Circuit for IC Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 13

14 For th Human Body Modl, th currnt limiting rsistor (R S ) and th sourc capacitor (C S ) ar 1.5k an 100pF, rspctivly. For IC , th currnt limiting rsistor (R S ) and th sourc capacitor (C S ) ar 330 an 150pF, rspctivly. Th highr C S valu and lowr R S valu in th IC modl ar mor stringnt than th Human Body Modl. Th largr storag capacitor injcts a highr voltag to th tst point whn SW is switchd on. Th lowr currnt limiting rsistor incrass th currnt charg onto th tst point. I t=0ns t t=30ns Figur 0. SD Tst Wavform for IC Dvic Pin Human Body IC Tstd Modl ir Discharg Dirct Contact vl Drivr Outputs ±15kV ±15kV ±8kV 4 Rcivr Inputs ±15kV ±15kV ±8kV 4 Tal 3. Transcivr SD Tolranc vls Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 14

15 N D S DTI 1 1 INDX R D x 1 NX R R1 Gaug Plan Saing Plan Ø DTI 0 Pin SSOP JDC MO-153 () Variation SYMBO MIN NOM MX c D ø 0º 1.5 RF 4º 8º WITH D FINISH c 1 Sating Plan Not: Dimnsions in (mm) BS MT Sction - 0 PIN SSOP Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 15

16 N D S DTI 1 1 INDX R D x 1 NX R R1 Gaug Plan Saing Plan Ø DTI 16 Pin SSOP JDC MO-153 (C) Variation SYMBO MIN NOM MX c D ø 0º 1.5 RF 4º 8º WITH D FINISH 1 Sating Plan Not: Dimnsions in (mm) c BS MT Sction - Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 16

17 1 INDX R 1 c 1 3 TOP VIW B FRONT VIW SID VIW D Bas Plan D1 3 1 Sating Plan SYMBO PDIP JDC MS-001 VRITION BB N = 1 Pins Dimnsions in Inchs: Controlling Dimnsion Dimnsions in Millimtrs Convrsion Factor: 1 Inch = 5.0 mm MIN NOM MX MIN NOM MX c D BSC BSC BSC 0.01 BSC B D SIPX Pkg Signoff Dat/Rv: J Nov1-05/ Rv Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 17

18 D 1 D1 3 INDX R N 1 3 N/ 1 18 PIN PDIP JDC MS-001 (C) Variation SYMBO MIN NOM MX c D D B BSC.300 BSC Not: Dimnsions in (mm) C c B Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 18

19 D SID VIW / 1/ 1 1 Sating Plan INDX R (0.5D X 0.51) TOP VIW 1 3 () FRONT VIW Gaug Plan h h ø1 ø R1 R ø Sating Plan ø1 c 1 PIN WSOIC JDC MS-013 Variation Dimnsions in Inchs Convrsion Factor: SYMBO Dimnsions in Millimtrs: Controlling Dimnsion 1 Inch = 5.0 mm MIN NOM MX MIN NOM MX c h BSC 7.50 BSC 1.7 BSC BSC 0.95 BSC BSC R RF 0.5 BSC RF BSC - - R ø 0º - 8º 0º - 8º ø1 5º - 15º 5º - 15º ø 0º - - 0º - - D RF RF SIPX Pkg Signoff Dat/Rv: J Oct11-05/ Rv Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 19

20 D Ø1 / 1 Gaug Plan 1/ Sating Plan Ø1 Ø INDX R (D/ X 1/) 1 3 VIW C TOP VIW B B S VIW C 18 Pin WSOIC JDC MS-013 (B) Variation SYMBO MIN NOM MX c D BSC DSC 7.50 BSC 1.7 BSC ø 0º 1.04 RF 0.5 BSC - 8º ø1 5º - 15º 1 WITH PTING c SID VIW Sating Plan Not: Dimnsions in (mm) BS MT SCTION B-B Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 0

21 D Ø1 / 1 1/ Sating Plan Ø1 Gaug Plan Ø INDX R (D/ X 1/) 1 3 TOP VIW VIW C B 16 Pin SOIC JDC MS-013 () Variation SYMBO MIN NOM MX c D BSC DSC 7.50 BSC 1.7 BSC ø 0º 1.04 RF 0.5 BSC - 8º ø1 5º - 15º 1 B SID VIW S VIW C Sating Plan Not: Dimnsions in (mm) WITH PTING c BS MT SCTION B-B Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 1

22 D Ø 1 1 INDX R D x 1 Saing Plan Ø3 DTI Ø1 S DTI 1 Sating Plan B B 16 Pin TSSOP JDC MO-153 (B) Variation SYMBO MIN NOM MX c D BSC Ø1 0º 0.65 BSC 4º 8º ø ø º RF 1º RF RF C Sction B-B Not: Dimnsions in (mm) Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation

23 D Ø 1 Saing Plan Ø Ø 1 INDX R D x 1 DTI S DTI B B 0 Pin TSSOP JDC MO-153 (C) Variation SYMBO MIN NOM MX c D BSC Ø1 0º 0.65 BSC - 8º ø ø º RF 1º RF RF C Sction B-B Not: Dimnsions in (mm) Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 3

24 D SID VIW / 1 1 Sating Plan INDX R (D/ X 1/) TOP VIW 1 3 1/ () h ø1 h ø R1 Gaug Plan R ø Sating Plan ø1 c FRONT VIW SYMBO 1 Pin NSOIC JDC MS-01 Variation C Dimnsions in Millimtrs: Controlling Dimnsion Dimnsions in Inchs Convrsion Factor: 1 Inch = 5.0 mm MIN NOM MX MIN NOM MX c h BSC 3.90 BSC 1.7 BSC BSC BSC BSC RF 0.5 BSC RF BSC R R ø 0º - 8º 0º - 8º ø1 5º - 15º 5º - 15º ø 0º - - 0º - - D.0 BSC BSC SIPX Pkg Signoff Dat/Rv: J Oct1-05 / Rv Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 4

25 Dat:11/0/05 SP3B/SP33B Tru 3.0V to 5.5V RS-3 Transcivrs Copyright 005 Sipx Corporation 5 0 Part Numr Tmpratur Rang Packag Typ SP3BC... 0 C to 70 C... 0-Pin SSOP SP3BC/TR... 0 C to 70 C... 0-Pin SSOP SP3BCP... 0 C to 70 C Pin PDIP SP3BCT... 0 C to 70 C Pin WSOIC SP3BCT/TR... 0 C to 70 C Pin WSOIC SP3BCY... 0 C to 70 C... 0-Pin TSSOP SP3BCY/TR... 0 C to 70 C... 0-Pin TSSOP SP3B C to 85 C... 0-Pin SSOP SP3B/TR C to 85 C... 0-Pin SSOP SP3BP C to 85 C Pin PDIP SP3BT C to 85 C Pin WSOIC SP3BT/TR C to 85 C Pin WSOIC SP3BY C to 85 C... 0-Pin TSSOP SP3BY/TR C to 85 C... 0-Pin TSSOP SP33BC... 0 C to 70 C Pin SSOP SP33BC/TR... 0 C to 70 C Pin SSOP SP33BCP... 0 C to 70 C Pin PDIP SP33BCT... 0 C to 70 C Pin WSOIC SP33BCT/TR... 0 C to 70 C Pin WSOIC SP33BCN... 0 C to 70 C Pin NSOIC SP33BCN/TR... 0 C to 70 C Pin NSOIC SP33BCY... 0 C to 70 C Pin TSSOP SP33BCY/TR... 0 C to 70 C Pin TSSOP SP33B C to 85 C Pin SSOP SP33B/TR C to 85 C Pin SSOP SP33BP C to 85 C Pin PDIP SP33BT C to 85 C Pin WSOIC SP33BT C to 85 C Pin WSOIC SP33BN C to 85 C Pin NSOIC SP33BN/TR C to 85 C Pin NSOIC SP33BY C to 85 C Pin TSSOP SP33BY/TR C to 85 C Pin TSSOP vailal in lad fr packaging. To ordr add "-" suffix to part numr. xampl: SP33BN/TR = standard; SP33BN-/TR = lad fr /TR = Tap and Rl ORDRING INFORMTION Pack quantity is 1,500 for WSOIC, SSOP or 0 pin TSSOP and,500 for NSOIC or 16 pin TSSOP. CICK HR TO ORDR SMPS Corporation NOG XCNC Hadquartrs and Sals Offic 33 South Hillviw Driv Milpitas, C T: (408) FX: (408) Sipx Corporation rsrvs th right to mak changs to any products dscrid hrin. Sipx dos not assum any liaility arising out of th application or us of any product or circuit dscrid hrin; nithr dos it convy any licns undr its patnt rights nor th rights of othrs.