7926-pixel CCD Linear Image Sensor (B/W) For the availability of this product, please contact the sales office.

Transcription

1 ILX8A 796-pixel CCD Linear Image Seor (B/W) For the availability of this product, please contact the sales office. Description The ILX8A is a reduction type CCD linear seor 4 pin DIP (Ceramic) developed for high resolution copiers. This seor reads A3-size documents at a deity of 6 DPI (Dot Per Inch). A built-in timing generator and clock-drivers eure direct drive at V logic for easy use. In addition reset pulse can switch between internal generation and external input. Features Number of effective pixels: 796 pixels Pixel size: 7µm 7µm (7µm pitch) Built-in timing generator and clock-drivers Ultra high seitivity Ultra low lag/low dark voltage Output method Maximum operating frequency:.mhz Absolute Maximum Ratings Supply voltage VDD V VDD 6 V Operation temperature to +6 C Storage temperature 3 to +8 C Pin Configuration (Top View) VGG 4 3 VDD VDD 3 RS/SH VOUT 4 VDD VDD φrog 6 9 VDD 7 8 VDD VDD 8 7 RSSW 9 6 T4 T T T 3 Sony reserves the right to change products and specificatio without prior notice. This information does not convey any licee by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits. E96X33-PS

2 D7 D8 D98 S S S79 S796 D99 D D6 ILX8A Block Diagram VOUT VGG 4 VDD VDD VDD VDD T4 T3 T Clock-drivers Output amplifier Sample-and-hold circuit Feed through suppression circuit CCD analog shift register Read out gate Read out gate CCD analog shift register Clock-drivers Clock-pulse generator Sample-and-hold pulse generator Mode selector Read out gate pulse generator VDD VDD VDD RSSW RS/SH T φrog

3 ILX8A Pin Description Pin No Symbol VGG VDD VOUT φrog VDD VDD RSSW T T T3 T4 VDD VDD VDD RS/SH VDD Output circuit gate bias 9V power supply Signal output Clock pulse V power supply V power supply Description RS pulse external, internal selection (External RS VDD, Internal RS ) Test pin (V) Test pin () Test pin (V) Test pin () V power supply 9V power supply 9V power supply Clock pulse or S/H switch 9V power supply Clock pulse Output mode is changeable as follows. 9pin pin VDD φrs Internal RS without S/H Internal RS with S/H VDD External RS without S/H 3

4 ILX8A Recommended Voltage Item Min. Typ. Max. Unit VDD V VDD V Note) Rules for raising and lowering power supply voltage. To raise power supply voltage, first raise VDD (9V) and then VDD (V). To lower voltage, first lower VDD (V) and then VDD (9V). Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacity of C pf Input capacity of φrog CφROG pf Input capacity of RS/SH C RS/SH pf frequency f. MHz φrs frequency fφrs. MHz 4

5 ILX8A Electrooptical Characteristics (Ta = C, V DD = 9V, VDD = V, Light source = 3K, = MHz, Internal φrs mode without S/H, IR cut filter, CM-S (t =.mm)) Item Symbol Min. Typ. Max. Unit Remarks Seitivity R V/(lx s) Seitivity R 4.6 V/(lx s) 3 Seitivity nonuniformity PRNU. % 4 Saturation output voltage VSAT.. V Saturation exposure SE.7.39 lx s 6 Even and odd black level DC difference V.. mv 7 Dark voltage average VDRK.3 mv 8 Dark signal nonuniformity DSNU.6 mv 9 Image lag IL. % 9V supply current IVDD 6 3 ma V supply current IVDD 6 ma Total trafer efficiency TTE 9 97 % Output impedance ZO 6 Ω Offset level VOS 3. V Dynamic range DR 3 In accorcance with the given electrooptical characteristics, the even black level is defined as the mean value of D8, D, D, D4, and D6. For the seitivity test light is applied with a uniform inteity of illumination. W lamp (84K). 4 PRNU is defined as indicated below. Ray incidence conditio are the same as for. (VMAX VMIN)/ PRNU = [%] VAVE 6 Where the 796 pixels are divided into blocks of, even and odd pixels, respectively (Even and odd last blocks are 87.) The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. Use below the minimum value of the saturation output voltage. Saturation exposure is defined as follows. SE = VSAT R Indicates the DC difference in value between odd black level and even black level. optical signal accumulated time τ int stands at ms. The difference between the maximum and mean values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time τ int stands at ms. VOUT = mv (Typ.)

6 ILX8A VOS is defined as indicated below. Vout VOS Dynamic range is defined as follows. DR = VSAT VDRK When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical signal accumulated time is in proportion to the dark voltage. 6

7 ILX8A Application Circuit (External φrs) When noise influence into output signal is large, connect pi indicated by (A) to the analog power supply and pi indicated by (D) to the digital power supply, and also use a decoupling capacitor of large capacitance. VGG (A) VDD (A) VOUT (A) VDD (D) VDD (D) VDD (D) VDD (A) VDD (A) VDD (D) (A) (A) φrog PSSW (D) T (D) (A) RS/SH (D) (D) (D) T4 (D) T3 (D) T (D) 9V V.µ.µ µ/6v µ/6v Output signal φrs µ µ/v kω φrog SA7 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 7

8 D D D3 D4 D D6 D6 D7 D8 D9 D D96 D97 D98 S S S3 S4 D793 D794 D79 D796 D99 D D6 D7 D8 D9 D ILX8A Clock Timing Diagram (External φrs) φrog φrs VOUT Dummy signal (98 pixels) Optical black (8 pixels) Effective picture elements signal (796 pixels) Dummy signal (8 pixels) line output period (84 pixels) 8

9 ILX8A Clock pulse Waveform Conditio, φrog pulse related t8 t9 φrog t t t3 Internal φrs mode t8 t9 t4 t External φrs mode Vout t t t t4 t t9 t8 φrs t7 t6 t t3 t 9

10 ILX8A Item Symbol Min. Typ. Max. Unit φrog, pulse timing t 3 φrog, pulse timing t3 φrog pulse high level period t pulse high level period t4 4 pulse low level period t 4 φrs pulse low level period t6, φrs pulse timing t7 6 + t4 + t Input clock pulse rise/fall time t8, t9 Input clock pulse voltage High level Low level V, VφROG VφRS V V Signal output delay time Internal φrs External φrs t t t t The frequency of is MHz.

11 Output voltage rate Output voltage rate MTF Relative seitivity ILX8A Example of Representative Characteristics (VDD = 9V, VDD = V, Ta = C). Spectral seitivity characteristics (Standard characteristics) Wavelength [nm] MTF of main scanning direction (Standard characteristics) Spatial frequency [cycle/mm] Dark signal output temperature characteristics (Typical characteristics) Normalized spatial frequency Integration time output voltage characteristics (Typical characteristics) Ta Ambient temperature [ C] τ int integration time [ms]

12 ILX8A Operational frequency characteristics of the VDD supply current (Typical characteristics) Operational frequency characteristics of the VDD supply current (Typical characteristics) 6 IVDD VDD supply current [ma] IVDD VDD supply current [ma] f clock frequency [MHz] f clock frequency [MHz] 6 Offset level vs. VDD characteristics (Typical characteristics) 6 Offset level vs. VDD characteristics (Typical characteristics) Ta = C Ta = C VOS Offset level [V] 4 3 VOS VDD VOS Offset level [V] 4 3 ~.3 VOS VDD ~ VDD [V] Offset level vs. Temperature characteristics (Typical characteristics) VDD [V] VOS Offset level [V] 4 3 ~ VOS Ta.8mV/ C Ta Ambient temperature [ C]

13 ILX8A Notes on Handling ) Static charge prevention CCD image seors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Itall a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image seor. e) For the shipment of mounted substrates use boxes treated for the prevention of static charges. ) Regulation for raising and lowering the power supply voltage. When raising the supply voltage, first raise VDD (9V) and then VDD (V). Similarly, lower VDD (V) first and then VDD (9V). 3) Soldering a) Make sure the package temperature does not exceed 8 C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 3W soldering iron and solder each pin in less then seconds. For repairs and remount, cool sufficienty. c) To dismount an imaging device do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface blow it off with an air blow. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condeation, preheat or precool when moving to a room with great temperature differences. ) Exposure to high temperatures or humity will affect the characteristics. Accordingly avoid storage or usage in such conditio. 6) CCD image seors are precise optical equipment that should not be subject to mechanical shocks. 3

14 4. ±..97 ±.3 3. ±..8 ±..9. ±. 9. ±.. ±. (AT STAND OFF).6 ±.3 to 9 ILX8A Package Outline Unit: mm 4Pin DIP (4mil) 7. ±.9 9. ±.8.48 (7µm 796Pixels) 4 3 V No. Pixel H 68. ±. st. pin Index.7.4 ±..46 ±. PACKAGE STRUCTURE PACKAGE MATERIAL Ceramic LEAD TREATMENT GOLD PLATING LEAD MATERIAL 4ALLOY PACKAGE WEIGHT.8g.3 M. The height from the bottom to the seor surface is.4 ±.3mm.. The thickness of the cover glass is.8mm, and the refractive index is.. 4