ILX554B pixel CCD Linear Sensor (B/W) for Single 5V Power Supply Bar-code Reader

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1 248-pixel CCD Linear Seor (B/W) for Single 5V Power Supply Bar-code Reader Description The ILX554B is a rectangular reduction type CCD linear image seor designed for bar code POS hand scanner and optical measuring equipment use. A built-in timing generator and clock-drivers eure single 5V power supply for easy use. 22 pin DIP (Cer-DIP) Features Number of effective pixels: 248 pixels Pixel size: 4µm 56µm (4µm pitch) Block Diagram Single 5V power supply Ultra-high seitivity Built-in timing generator and clock-drivers Built-in sample-and-hold circuit Maximum clock frequency: 2MHz Absolute Maximum Ratings Supply voltage VDD 6 V Operating temperature to +6 C Storage temperature 3 to +8 C Pin Configuration (Top View) VOUT 22 SHSW VDD GND D38 D37 S246 S247 S248 D33 D32 S S2 S3 D3 D4 Output amplifier S/H circuit VOUT Readout gate CCD analog shift register Clock-drivers Readout gate pulse generator Mode selector Clock pulse generator/ Sample-and-hold pulse generator GND VDD SHSW Sony reserves the right to change products and specificatio without prior notice. This information does not convey any licee by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits. E752A22-PS

2 Pin Description Pin No. Symbol Description VOUT SHSW Signal output Switch (with S/H or without S/H) Clock pulse input Readout gate pulse input Pin No. Symbol Description GND GND VDD 5V power supply Mode Description Mode in use With S/H Without S/H Pin 4 (SHSW) GND VDD Recommended Supply voltage VDD V Input Clock voltage Condition VIH VDD V VIL.5 V This is applied to the all pulses applied externally. (, ) Clock Characteristics Symbol Input capacity of C pf Input capacity of C pf 2

3 Electro-optical Characteristics (Ta = 25 C, VDD = 5V, Clock frequency: MHz, Light source = 32K, IR cut filter: CM-5S (t =.mm), Without S/H mode) Symbol Remarks Seitivity R V/(lx s) Note Seitivity 2 R2 35 V/(lx s) Note 2 Seitivity nonuniformity PRNU 5.. % Note 3 Saturation output voltage VSAT.8. V Dark voltage average VDRK mv Note 4 Dark signal nonuniformity DSNU mv Note 4 Image lag IL % Note 5 Dynamic range DR 333 Note 6 Saturation exposure SE.4 lx s Note 7 5V current coumption IVDD 5. ma Total trafer efficiency TTE % Output impedance ZO 25 Ω Offset level VOS 2.85 V Note 8 Note). For the seitivity test light is applied with a uniform inteity of illumination. 2. Light sourse: LED λ = 66nm 3. PRNU is defined as indicated below. Ray incidence conditio are the same as for Note. (VMAX VMIN)/2 PRNU = [%] VAVE The maximum output of all the valid pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. 4. Integration time is ms. 5. Typical value is used for clock pulse and readout pulse. VOUT = 5mV. 6. DR = VSAT VDRK When optical integration time is shorter, the dynamic range sets wider because dark voltage is in proportion to optical integration time. 7. SE = VSAT R 8. VOS is defined as indicated below. Vout D D D SI VOS GND 3

4 Clock Timing Diagram (without S/H mode) D D2 D3 D4 D5 D D D2 D3 D4 D3 D3 D32 S S2 S3 S4 S245 S246 S247 S248 D33 D34 D35 D36 D37 D38 VOUT Dummy signal (32 pixels) Optical black (8 pixels) Effective picture elements signal (248 pixels) Dummy signal (6 pixels) -line output period (286 pixels) Without S/H mode (Pin 4 VDD) Note) 288 or more clock pulse are required. 4

5 Clock Timing Diagram (with S/H mode) D D D2 D3 D4 D5 D D D2 D3 D4 D3 D3 D32 S S2 S3 S4 S245 S246 S247 S248 D33 D34 D35 D36 D37 D38 VOUT Dummy signal (33 pixels) Optical black (8 pixels) Effective picture elements signal (248 pixels) Dummy signal (6 pixels) -line output period (287 pixels) With S/H mode (Pin 4 GND) Note) 288 or more clock pulse are required. 5

6 Timing (For all modes) t t2 t3 t4 Symbol pulse rise/fall time t, t2 pulse duty % t4 / (t3 + t4), Timing t6 t8 t7 t5 t9 Symbol, pulse timing t5 3, pulse timing 2 t9 3 pulse rise/fall time t6, t8 pulse period t7 5 6

7 , VOUT Timing (Note ) (Note 3) t t VOUT VOUT (Note 2) t2 Symbol -VOUT t VOUT 2 t VOUT (with S/H) 3 t Note ) fck = MHz, pulse duty = 5%, pulse rise/fall time = Note 2) Output waveform when internal S/H is in use. Note 3) indicates the correspondence of clock pulse and data period. 7

8 Example of Representative Characteristics Spectral seitivity () (Ta = 25 C) Wavelength [nm] 8 9 Dark voltage rate vs. Ambient temperature () Dark voltage rate Ta Ambient temperature [ C] 8

9 Output voltage rate vs. Integration time () Current coumption rate vs. Clock frequency () 2. Output voltage rate Current coumption rate Integration time [ms] Clock frequency [MHz] Offset level vs. VDD () Offset level vs. Ambient temperature () Offset level [V] Offset level [V] VDD [V] Ambient temperature [ C] 9

10 Application Circuit (Without S/H mode) Note) VDD.µ 22µ/V VOUT SHSW VDD GND Ω Ω VOUT 3kΩ Note) This circuit diagram is the case when internal S/H mode is not used. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

11 Notes on Handling ) Static charge prevention CCD image seors are easily damaged by static discharge. Before handling, be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an eath band. c) Itall a conductive mat on the floor or working table to prevent the generation of static electricity. d) lonized air is recommended for discharge when handling CCD image seors. e) For the shipment of mounted substrates use carto treated for the prevention of static charges. 2) Notes on handling CCD Cer-DIP package The following points should be observed when handling and italling this package. a) () Compressive strength: 39N/surface (Do not apply any load more than.7mm iide the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Teile strength: 29N/surface (4) Torsional strength:.9nm Upper ceramic layer 39N 29N 29N.9Nm Lower ceramic layer () Low-melting glass (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for itallation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack because the upper and lower ceramic layers are shielded by low-melting glass. () Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with a soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 8 C. b) Solder dipping in a mounting furnace causes demage to the glass abd other defects. Use a grounded 3W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount image seors, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type.

12 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface blow it off with an air blower. (For dirt stuck through static electricity, ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in case to protect from dust and dirt. To prevent dew condeation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditio. 6) CCD image seors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on. Use the output signal added 225 pulses or above to clock pulse. 2

13 4. ± ±.5 5. ±.3. ±.5 to 9 ILX554B.25 Package Outline : mm 22 pin DIP (4mil) 6.46 ± ± (4µm X 248Pixels) 22 2 V H No. Pixel PACKAGE STRUCTURE PACKAGE MATERIAL Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 5.2g DRAWING NUMBER LS-A2(E).3 M. The height from the bottom to the seor surface is 2.45 ±.3mm. 2. The thickness of the cover glass is.7mm, and the refractive index is.5. 3 Sony Corporation

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