ILX526A pixel CCD Linear Image Sensor (B/W)

Transcription

1 D4 D D4 D S S S3 S999 S3 D6 D6 3-pixel CCD Linear Image Seor (B/W) ILX6A Description The ILX6A is a rectangular reduction type CCD linear image seor designed for bar code POS hand scanner and optical measuring equipment use. A built-in timing generator and clock-drivers eure single V power supply for easy use. pin DIP (Cer-DIP) Features Number of effective pixels: 3 pixels Pixel size: 7µm µm (7µm pitch) Single V power supply Internal Structure High seitivity: 3V/(lx s) Built-in timing generator and clock-drivers Built-in sample-and-hold circuit Electrical shutter function Clock frequency: khz (Min), MHz (Max) Absolute Maximum Ratings Supply voltage 6 V Operating temperature to +6 C Storage temperature 3 to +8 C Pin Configuration (Top View) Vgg T 3 3 S/HSW Vgg Clock-drivers CCD analog shift register Readout gate Readout gate pulse generator Shutter pulse generator Readout gate CCD analog shift register Clock-drivers Clock pulse generator 6 7 Output Amplifier S/H circuit S/HSW T Sony reserves the right to change products and specificatio without prior notice. This information does not convey any licee by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits. E9783-PS

2 ILX6A Pin Description Pin No. Symbol Description Vgg T S/HSW Output circuit gate bias Clock pulse input Readout gate pulse input Electrical Shutter pulse input V TEST Switch (with S/H or without S/H) V Signal output V Mode Description Mode in Use With S/H Without S/H pin S/HSW Recommended Voltage 4... V Input Pin Capacity Symbol Input capacity of pin C pf Input capacity of pin C pf Input capacity of pin C pf

3 ILX6A Electro-optical Characteristics (Note ) Ta = C, = V, Clock frequency: khz, Light source = 3K, IR cut filter: CM-S (t =.mm), Without S/H mode Symbol Remarks Seitivity Seitivity Seitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure V current coumption Total trafer efficiency Output impedance Offset level R R PRNU VSAT VDRK DSNU IL DR SE I TTE ZO VOS V/(lx s) V/(lx s) % V mv mv % lx s ma % Ω V Note Note 3 Note 4 Note Note 6 Note 7 Note 8 Note 9 Note Note). In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D4, D6 to D. The odd black level is defined as the average value of D, D7 to D3.. For the seitivity test light is applied with a uniform inteity of illumination. 3. Light source: LED λ = 66nm 4. PRNU is defined as indicated below. Ray incidence conditio are the same as for Note. PRNU = (VMAX VMIN)/ [%] Where the 3 pixels are divided into blocks of even and odd pixels, respectively, the maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE.. Integration time is ms. 6. The difference between the maximum and average values of the dark output voltage is calculated for even and odd respectively. Integration time is ms. 7. Typical value is used for clock pulse and readout pulse. = mv. 8. DR = When optical integration time is shorter, the dynamic range sets wider because dark voltage is in proportion to optical integration time. 9. SE = VSAT VDRK VSAT R VAVE. Vos is defined as indicated below. D D D3 D4 D S VOS 3

4 D D D D3 D4 D D D3 D4 D3 D4 D S S S3 S4 S997 S998 S999 S3 D6 D7 D8 D9 D6 D6 D6 D63 D64 D6 ILX6A Clock Timing Diagram (With S/H mode) 3 or more clock pulses are required. Optical black (3 pixels) Dummy signal ( pixels) Effective picture elements signal (3 pixels) -Line output period (366 pixels) Dummy signal ( pixels) 4

5 D D D D3 D4 D D D3 D4 D D3 D4 D S S S3 S997 S998 S999 S3 D6 D7 D8 D9 D6 D6 D6 D63 D64 D6 ILX6A Clock Timing Diagram (Without S/H mode) 3 or more clock pulses are required. Optical black (3 pixels) Dummy signal ( pixels) Effective picture elements signal (3 pixels) -Line output period (366 pixels) Dummy signal ( pixels)

6 ILX6A Input Clock Voltage Condition VIH 4.. V This is applied to the all external pulses. (,, ) VIL.. V Timing (For all modes) t t t3 t4 Symbol pulse rise/fall time t, t pulse Duty 4 6 % t4/ (t3 + t4), Timing t6 t7 t8 t t9 Symbol, pulse timing t (/8) τ (/4) τ (3/8) τ, pulse timing t9 (/8) τ (/4) τ (3/8) τ pulse rise/fall time t6, t8 pulse period t7 6τ τ τ Note) τ is the period of. 6

7 ILX6A, Timing t t t3 t4 t Symbol φ SHUT pulse rise/fall time t, t3 φ SHUT pulse period t 4 φ SHUT, φ CLK pulse timing t4 φ SHUT, φ CLK pulse timing t, Timing t6 t7 Symbol, pulse timing t6, t7 τ 7

8 ILX6A - Timing t8 3 t9 Symbol - output delay time t8 3 - output delay time t9 3 fck = khz, Duty = %, rise/fall time = is data period Using internal sample-and-hold circuit Application Circuit (Without S/H mode (Note)) V Vgg.µ µ/v 3kΩ SA T 4 3 S/HSW Note) This circuit diagram is the case when internal S/H is not used. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 8

9 Output voltage rate Relative seitivity ILX6A Example of Representative Characteristics ( = V, Ta = C) Spectral seitivity characteristics (Standard characteristics) Wavelength [nm] Dark signal output temperature characteristics (Standard characteristics) Ta Ambient temperature [ C] 9

10 Output voltage rate ILX6A Offset level vs. Temperature characteristics (Standard characteristics) 4 VOS Ta.mV/ C 4 Offset level vs. characteristics (Standard characteristics) Ta = C VOS Offset level [V] 3 VOS Offset level [V] 3 VOS Ta Ambient temperature [ C] [V] 4 Supply current vs. characteristics (Standard characteristics) Ta = C Output voltage vs. Integration time (Standard characteristics) I Supply current [ma] [V] τ Integration time [ms]

11 ILX6A Notes of Handling ) Static charge prevention CCD image seors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Itall a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image seor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. ) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and italling cer-dip packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: () Compressive strength: 39N/surface (Do not apply load more than.7mm iide the outer perimeter of the glass portion.) () Shearing strength: 9N/surface (3) Teile strength: 9N/surface (4) Torsional strength:.9nm Upper ceramic layer Lower ceramic layer 39N () Low-melting glass 9N 9N.9Nm () (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for itallation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, () Applying repetitive bending stress to the external leads. () Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. () Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 8 C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 3W soldering iron and solder each pin in less then seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type.

12 ILX6A 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condeation, preheat or precool when moving to a room with great temperature differences. ) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditio. 6) CCD image seors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on.

13 4. ± ±.. ±. 9.. ±..6 (AT STAND OFF) to 9 ILX6A. Package Outline : mm pin DIP (4mil) 3. ±.. ±.8. (7µm 3Pixels) V H No. Pixel PACKAGE STRUCTURE PACKAGE MATERIAL Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL 4 ALLOY PACKAGE WEIGHT 3.g.3 M. The height from the bottom to the seor surface is.6 ±.3mm.. The thickness of the cover glass is.7mm, and the refractive index is.. 3