Diagonal 8mm (Type 1/2) CCD Image Sensor for EIA Black-and-White Video Cameras

Transcription

1 ICX08DLA Diagonal 8mm (Type /) CCD Image Sensor for EIA Black-and-White ideo Cameras Description The ICX08DLA is an interline CCD solid-state image sensor suitable for EIA black-and-white video cameras with a diagonal 8mm (Type /) system. Smear, sensitivity, D-range, S/N and other characteristics have been greatly improved compared with the ICX08BLA. High sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip features a field period readout system and an electronic shutter with variable charge-storage time. This chip is compatible with and can replace the ICX08BLA. 0 pin DIP (Cer-DIP) Pin Features Low smear ( 0dB compared with the ICX08BLA) H 0 High sensitivity (+.0dB compared with the ICX08BLA) Pin High D range (+.db compared with the ICX08BLA) Optical black position High S/N (Top iew) High resolution and low dark current Excellent antiblooming characteristics Continuous variable-speed shutter Substrate bias: Adjustment free (external adjustment also possible with 6 to ) Reset gate pulse: p-p adjustment free (drive also possible with 0 to 9) Horizontal register: drive Device Structure Interline CCD image sensor Image size: Diagonal 8mm (Type /) Number of effective pixels: 768 (H) x 9 () approx. 80K pixels Total number of pixels: 8 (H) x 08 () approx. 0K pixels Chip size: 7.9mm (H) x 6.mm () Unit cell size: 8.µm (H) x 9.8µm () Optical black: Horizontal (H) direction : Front pixels, rear 0 pixels ertical () direction : Front pixels, rear pixels Number of dummy bits: Horizontal ertical (even fields only) Substrate material: Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. E99C99

2 ICX08DLA Note) Note) : Photo sensor 6 φrg GG DSUB SS RD NC Hφ Hφ ertical Register OUT DD L φ φsub φ φ φ Block Diagram and Pin Configuration (Top iew) Horizontal Register Pin Description Pin No. Symbol Description Pin No. Symbol Description φ ertical register transfer clock GG Output circuit gate bias φ ertical register transfer clock DSUB Substrate bias circuit supply voltage φ ertical register transfer clock SS Output circuit source φsub Substrate clock 6 φ ertical register transfer clock 6 RD Reset drain bias 7 L Protective transistor bias 7 φrg Reset gate clock 8 8 NC 9 DD Output circuit supply voltage 9 Hφ Horizontal register transfer clock 0 OUT Signal output 0 Hφ Horizontal register transfer clock

3 ICX08DLA Absolute Maximum Ratings Item Substrate clock φsub Supply voltage Clock input voltage DD, RD, DSUB, OUT, SS DD, RD, DSUB, OUT, SS φsub φ, φ, φ, φ φ, φ, φ, φ φsub oltage difference between vertical clock input pins oltage difference between horizontal clock input pins Hφ, Hφ φ φrg, GG φrg, GG φsub L φsub Pins other than and φsub L Storage temperature Operating temperature Ratings Unit Remarks 0. to to +8 to +0 to +0 to +0 to + to +7 7 to +7 0 to + to +0 6 to to +0 0 to to +60 C C +7 (Max.) when clock width < 0µs, clock duty factor < 0.%.

4 ICX08DLA Bias Conditions [when used in substrate bias internal generation mode] Item Output circuit supply voltage Reset drain voltage Output circuit gate voltage Output circuit source Protective transistor bias Substrate bias circuit supply voltage Substrate clock Symbol Min. Typ. Max. Unit Remarks DD RD GG SS L DSUB φsub Grounded with 90Ω resistor..0. RD = DD L setting is the L voltage of the vertical transfer clock waveform, or the same power supply as the L power supply for the driver should be used. (When CXD67AN is used.) Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. Bias Conditions [when used in substrate bias external adjustment mode] Item Output circuit supply voltage Reset drain voltage Output circuit gate voltage Output circuit source Protective transistor bias Substrate bias circuit supply voltage Substrate voltage adjustment range Substrate voltage adjustment precision Symbol Min. Typ. Max. Unit Remarks DD RD GG SS L DSUB SUB SUB Grounded with 90Ω resistor % RD = DD L setting is the L voltage of the vertical transfer clock waveform, or the same power supply as the L power supply for the driver should be used. (When CXD67AN is used.) Connect to or leave open. The setting value of the substrate voltage (SUB) is indicated on the back of the image sensor by a special code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated voltage. The adjustment precision is ±%. However, this setting value has not significance when used in substrate bias internal generation mode. SUB code SUB code one character indication Code and optimal setting correspond to each other as follows. E f G h J K L m N P Q R S T U W Optimal setting <Example> "L" SUB = 9.0 DC Characteristics Item Symbol Min. Typ. Max. Unit Remarks Output circuit supply current IDD ma

5 ICX08DLA Clock oltage Conditions Item Symbol Min. Typ. Max. Unit Waveform diagram Remarks Readout clock voltage T..0. H, H H = (H + H)/ H, H L, L, L, L L = (L + L)/ φ p-p φ = Hn Ln (n = to ) ertical transfer clock voltage H H H H H H HH 0. High-level coupling HL 0. High-level coupling LH 0. Low-level coupling LL 0. Low-level coupling Horizontal transfer clock voltage φh HL p-p Reset gate clock voltage RGL φrg RGLH RGLL p-p Low-level coupling Substrate clock voltage φsub p-p Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven with the following specifications. Reset gate clock voltage Item Symbol Min. Typ. Max. Unit RGL φrg p-p Waveform diagram Remarks

6 ICX08DLA Clock Equivalent Circuit Constant Item Capacitance between vertical transfer clock and Capacitance between vertical transfer clocks Capacitance between horizontal transfer clock and Capacitance between horizontal transfer clocks Capacitance between reset gate clock and Capacitance between substrate clock and ertical transfer clock series resistor ertical transfer clock ground resistor Cφ, Cφ Cφ, Cφ Cφ, Cφ Cφ, Cφ CφH CφH CφHH CφRG CφSUB R, R, R, R 68 Ω R Symbol Min. Typ. Max. Unit Remarks 800 pf 00 pf 0 pf 70 pf 6 pf 6 pf 7 pf 8 pf 00 pf Ω φ φ R Cφ R Hφ Hφ Cφ Cφ CφHH Cφ Cφ CφH CφH R Cφ R Cφ Cφ R φ φ ertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit 6

7 ICX08DLA Drive Clock Waveform Conditions () Readout clock waveform 00% 90% T II II φm 0% 0% tr twh tf φm 0 () ertical transfer clock waveform φ φ H HH H HH HH HH H HL HL HL H HL L LH L LH L LL L LL φ φ HH HH H H HH HH H HL HL HL H HL LH L LH L LL L LL L H = (H + H)/ L = (L + L)/ φ = Hn Ln (n = to ) 7

8 ICX08DLA () Horizontal transfer clock waveform tr twh tf 90% φh twl 0% HL () Reset gate clock waveform tr twh tf RGH twl RG waveform RGLH RGLL Point A φrg RGL + 0. RGL Hφ waveform +. RGLH is the maximum value and RGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, RGL is the average value of RGLH and RGLL. RGL = (RGLH + RGLL)/ Assuming RGH is the minimum value during the interval twh, then: φrg = RGH RGL 8

9 ICX08DLA () Substrate clock waveform 00% 90% φm SUB 0% 0% φsub tr twh tf φm Clock Switching Characteristics Item Readout clock ertical transfer clock Horizontal transfer clock During imaging During parallelserial conversion T φ, φ, φ, φ Hφ Symbol Hφ Hφ twh twl tr tf Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max µs ns ns µs Remarks During readout Reset gate clock φrg ns Substrate clock φsub µs During drain charge When vertical transfer clock driver CXD67AN is used. tf tr ns. two Item Symbol Unit Remarks Min. Typ. Max. Horizontal transfer clock Hφ, Hφ 6 0 ns The overlap period for twh and twl of horizontal transfer clocks Hφ and Hφ is two. 9

10 ICX08DLA Image Sensor Characteristics (Ta = C) Item Sensitivity Saturation signal Smear ideo signal shading Dark signal Dark signal shading Flicker Lag Symbol Min. Typ. Max. Unit Measurement method Remarks S sat Sm m m % SH 0 % % dt dt F Lag 0. m m % % Ta = 60 C Zone 0 and I Zone 0 to II' Ta = 60 C Ta = 60 C Zone Definition of ideo Signal Shading 768 (H) H 8 0 H 8 9 () Zone 0, I Zone II, II' 0 0 Ignored region Effective pixel region 0

11 ICX08DLA Image Sensor Characteristics Measurement Method Measurement conditions ) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (When used with substrate bias external adjustment, set the substrate voltage to the value indicated on the device.) ) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [ A] in the drive circuit example is used. Definition of standard imaging conditions ) Standard imaging condition I: Use a pattern box (luminance: 706cd/m, color temperature of 00K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM00S (t =.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. ) Standard imaging condition II: Image a light source (color temperature of 00K) with a uniformity of brightness within % at all angles. Use a testing standard lens with CM00S (t =.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm.. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of /0 s, measure the signal output (s) at the center of the screen and substitute the value into the following formula. S = s x 0 60 [m]. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 0 times the intensity with the average value of the signal output, 00m, measure the minimum value of the signal output.. Smear Set to standard imaging condition II. With the lens diaphragm at F.6 to F8, adjust the luminous intensity to 00 times the intensity with the average value of the signal output, 00m. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (Sm [m]) of the signal output and substitute the value into the following formula. Sm = Sm 00 x 00 x 0 x 00 [%] (/0 method conversion value). ideo signal shading Set to standard imaging condition II. With the lens diaphragm at F.6 to F8, adjust the luminous intensity so that the average value of the signal output is 00m. Then measure the maximum (max [m]) and minimum (min [m]) values of the signal output and substitute the values into the following formula. SH = (max min)/00 x 00 [%]

12 ICX08DLA. Dark signal Measure the average value of the signal output (dt [m]) with the device ambient temperature 60 C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring, measure the maximum (dmax [m]) and minimum (dmin [m]) values of the dark signal output and substitute the values into the following formula. dt = dmax dmin [m] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 00m, and then measure the difference in the signal level between fields ( f [m]). Then substitute the value into the following formula. F = ( f/00) x 00 [%] 8. Lag Adjust the signal output value generated by strobe light to 00m. After setting the strobe light so that it strobes with the following timing, measure the residual signal (lag). Substitute the value into the following formula. Lag = (lag/00) x 00 [%] FLD Strobe light timing Light Signal output 00m lag (lag) Output

13 ICX08DLA 0 XSUB X X XSG X XSG X CXD67AN /0 Hφ Hφ RG /6 / k / k / 6..9k 7k./0 M 0.0 [ A] CCD OUT./6 9 DD Hφ Hφ NC φrg RD ss DSUB GG φ φ φ φsub φ L OUT Drive Circuit (substrate bias internal generation mode) ICX08DLA (BOTTOM IEW) 00

14 Hφ Hφ NC φrg RD ss DSUB GG φ φ φ φsub ICX08DLA 0 XSUB X X XSG X XSG X CXD67AN /0 Hφ Hφ RG /6 / / / k 70k 00k 7k 0. 9k / k / k 7k k 7k k 0. M./0 0.0 [ A] CCD OUT./6 9 φ DD L OUT Drive Circuit (substrate bias external adjustment mode) ICX08DLA (BOTTOM IEW)

15 Relative Response ICX08DLA Spectral Sensitivity Characteristics (Includes lens characteristics, excludes light source characteristics) Wave Length [nm] Sensor Readout Clock Timing Chart Odd Field Even Field unit : µs

16 ICX08DLA Drive Timing Chart (ertical Sync) FLD D BLK HD CCD OUT

17 ICX08DLA Drive Timing Chart (Horizontal Sync) HD BLK H H RG SUB 7

18 ICX08DLA Notes on Handling ) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. ) Soldering a) Make sure the package temperature does not exceed 80 C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 0W soldering iron and solder each pin in less than seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. ) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. ) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Upper ceramic 9N Lower ceramic Compressive strength Low melting point glass 9N 9N 0.9Nm Shearing strength Tensile strength Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. 8

19 ICX08DLA c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not to perform the following actions as this may cause cracks. Applying repeated bending stress to the outer leads. Heating the outer leads for an extended period with a soldering iron. Rapidly cooling or heating the package. Applying any load or impact to a limited portion of the low melting point glass using tweezers or other sharp tools. Prying at the upper or lower ceramic using the low melting point glass as a fulcrum. Note that the same cautions also apply when removing soldered products from boards. e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) ) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 9

20 .0 ± ± ~ 7... ± 0... (.0) ~ 0 to 9 ~ ICX08DLA Package Outline Unit: mm 0pin DIP (600mil) A (.0) (.7) 0 0 C (R0.7) φ. B H 8.0 ± M B'. A is the center of the effective image area.. The two points B of the package are the horizontal reference. The point B' of the package is the vertical reference.. The bottom C of the package is the height reference.. The center of the effective image area, relative to B and B' is (H, ) = (9.0, 7.) ± 0.mm.. The rotation angle of the effective image area relative to H and is ±. 6. The height from the bottom C to the effective image area is. ± 0.mm. 7. The tilt of the effective image area relative to the bottom C is less than 60µm. PACKAGE STRUCTURE 8. The thickness of the cover glass is 0.7mm, and the refractive index is.. 9. The notch and the hole on the bottom must not be used for reference of fixing. PACKAGE MATERIAL Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL ALLOY PACKAGE WEIGHT.6g 0